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-rw-r--r--src/arch/x86/boot/cbmem.c10
-rw-r--r--src/mainboard/emulation/qemu-i440fx/memory.c8
-rw-r--r--src/northbridge/intel/haswell/northbridge.c4
-rw-r--r--src/northbridge/intel/haswell/raminit.c6
4 files changed, 11 insertions, 17 deletions
diff --git a/src/arch/x86/boot/cbmem.c b/src/arch/x86/boot/cbmem.c
index 6a1226368e..bdc695c85d 100644
--- a/src/arch/x86/boot/cbmem.c
+++ b/src/arch/x86/boot/cbmem.c
@@ -55,4 +55,12 @@ unsigned long __attribute__((weak)) get_top_of_ram(void)
}
#endif /* !__PRE_RAM__ */
-#endif
+#else
+
+void *cbmem_top(void)
+{
+ /* Top of cbmem is at lowest usable DRAM address below 4GiB. */
+ return (void *)get_top_of_ram();
+}
+
+#endif /* DYNAMIC_CBMEM */
diff --git a/src/mainboard/emulation/qemu-i440fx/memory.c b/src/mainboard/emulation/qemu-i440fx/memory.c
index 027deb9c49..a189d750bb 100644
--- a/src/mainboard/emulation/qemu-i440fx/memory.c
+++ b/src/mainboard/emulation/qemu-i440fx/memory.c
@@ -44,11 +44,3 @@ unsigned long get_top_of_ram(void)
{
return qemu_get_memory_size() * 1024;
}
-
-#if CONFIG_DYNAMIC_CBMEM
-void *cbmem_top(void)
-{
- /* Top of cbmem is at lowest usable DRAM address below 4GiB. */
- return (void *)get_top_of_ram();
-}
-#endif
diff --git a/src/northbridge/intel/haswell/northbridge.c b/src/northbridge/intel/haswell/northbridge.c
index 9f027343e4..ac61ca47ee 100644
--- a/src/northbridge/intel/haswell/northbridge.c
+++ b/src/northbridge/intel/haswell/northbridge.c
@@ -535,14 +535,14 @@ static void northbridge_init(struct device *dev)
MCHBAR32(0x5500) = 0x00100001;
}
-void *cbmem_top(void)
+unsigned long get_top_of_ram(void)
{
u32 reg;
/* The top the reserve regions fall just below the TSEG region. */
reg = pci_read_config32(dev_find_slot(0, PCI_DEVFN(0, 0)), TSEG);
- return (void *)(reg & ~((1 << 20) - 1));
+ return (reg & ~((1 << 20) - 1));
}
static void northbridge_enable(device_t dev)
diff --git a/src/northbridge/intel/haswell/raminit.c b/src/northbridge/intel/haswell/raminit.c
index c1095a7eb7..a90b360116 100644
--- a/src/northbridge/intel/haswell/raminit.c
+++ b/src/northbridge/intel/haswell/raminit.c
@@ -202,12 +202,6 @@ void sdram_initialize(struct pei_data *pei_data)
report_memory_config();
}
-void *cbmem_top(void)
-{
- /* Top of cbmem is at lowest usable DRAM address below 4GiB. */
- return (void *)get_top_of_ram();
-}
-
unsigned long get_top_of_ram(void)
{
/*