diff options
| -rw-r--r-- | src/arch/arm/armv7/bootblock.S | 33 | ||||
| -rw-r--r-- | src/mainboard/emulation/qemu-armv7/memlayout.ld | 14 |
2 files changed, 39 insertions, 8 deletions
diff --git a/src/arch/arm/armv7/bootblock.S b/src/arch/arm/armv7/bootblock.S index e1879c0b30..47813a78f8 100644 --- a/src/arch/arm/armv7/bootblock.S +++ b/src/arch/arm/armv7/bootblock.S @@ -62,14 +62,43 @@ init_stack_loop: cmp r0, r1 bne init_stack_loop + /* Set stackpointer in internal RAM */ + ldr sp, =_estack + + /* + * For platforms where the flash is memory mapped (qemu), check if the + * bootblock needs to relocate itself. + */ +check_position: + adr r0, check_position + ldr r1, =check_position + + cmp r0, r1 + beq call_bootblock + + /* Calculate source */ + ldr r2, =_program + sub r1, r1, r2 + sub r1, r0, r1 + /* Get destination */ + ldr r0, =_program + /* Get size */ + ldr r2, =_eprogram + sub r2, r2, r0 + + bl memcpy + + /* Get absolute address */ + ldr lr, =call_bootblock + /* Directly modify pc as branch instruction changes the state */ + mov pc, lr + call_bootblock: /* Restore parameter passed in by maskrom/vendor firmware. */ ldr r0, =maskrom_param str r10, [r0] - /* Set stackpointer in internal RAM to call bootblock main() */ - ldr sp, =_estack ldr r0,=0x00000000 /* * The current design of cpu_info places the struct at the top of the diff --git a/src/mainboard/emulation/qemu-armv7/memlayout.ld b/src/mainboard/emulation/qemu-armv7/memlayout.ld index 9d76d9ddd0..4ddc6d2adc 100644 --- a/src/mainboard/emulation/qemu-armv7/memlayout.ld +++ b/src/mainboard/emulation/qemu-armv7/memlayout.ld @@ -28,14 +28,16 @@ SECTIONS { /* TODO: does this thing emulate SRAM? */ - BOOTBLOCK(0x00000, 64K) - FMAP_CACHE(0x10000, 2K) + REGION(flash, 0, CONFIG_ROM_SIZE, 4K) DRAM_START(0x60000000) STACK(0x60000000, 64K) - ROMSTAGE(0x60010000, 128K) - RAMSTAGE(0x60030000, 16M) - + BOOTBLOCK(0x60010000, 128K) + FMAP_CACHE(0x60030000, 4K) + TIMESTAMP(0x60031000, 1K) /* TODO: Implement MMU support and move TTB to a better location. */ - TTB(0x61030000, 16K) + TTB(0x60034000, 16K) + ROMSTAGE(0x60038000, 128K) + RAMSTAGE(0x60060000, 16M) + POSTRAM_CBFS_CACHE(0x61060000, 8M) } |