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-rw-r--r--src/cpu/samsung/exynos5250/dmc_init_ddr3.c14
-rw-r--r--src/cpu/samsung/exynos5250/setup.h4
-rw-r--r--src/mainboard/google/snow/romstage.c2
3 files changed, 14 insertions, 6 deletions
diff --git a/src/cpu/samsung/exynos5250/dmc_init_ddr3.c b/src/cpu/samsung/exynos5250/dmc_init_ddr3.c
index 5bb8a372ff..132471de74 100644
--- a/src/cpu/samsung/exynos5250/dmc_init_ddr3.c
+++ b/src/cpu/samsung/exynos5250/dmc_init_ddr3.c
@@ -61,7 +61,8 @@ static void reset_phy_ctrl(void)
udelay(500);
}
-int ddr3_mem_ctrl_init(struct mem_timings *mem, unsigned long mem_iv_size)
+int ddr3_mem_ctrl_init(struct mem_timings *mem, unsigned long mem_iv_size,
+ int mem_reset)
{
unsigned int val;
struct exynos5_phy_control *phy0_ctrl, *phy1_ctrl;
@@ -71,9 +72,14 @@ int ddr3_mem_ctrl_init(struct mem_timings *mem, unsigned long mem_iv_size)
phy0_ctrl = (struct exynos5_phy_control *)EXYNOS5_DMC_PHY0_BASE;
phy1_ctrl = (struct exynos5_phy_control *)EXYNOS5_DMC_PHY1_BASE;
dmc = (struct exynos5_dmc *)EXYNOS5_DMC_CTRL_BASE;
- printk(BIOS_SPEW, "ddr3_mem_ctrl_init: reset phy: ");
- reset_phy_ctrl();
- printk(BIOS_SPEW, "done\n");
+
+ if (mem_reset) {
+ printk(BIOS_SPEW, "%s: reset phy: ", __func__);
+ reset_phy_ctrl();
+ printk(BIOS_SPEW, "done\n");
+ } else {
+ printk(BIOS_SPEW, "%s: skip mem_reset.\n", __func__);
+ }
/* Set Impedance Output Driver */
printk(BIOS_SPEW, "ddr3_mem_ctrl_init: Set Impedance Output Driver\n");
diff --git a/src/cpu/samsung/exynos5250/setup.h b/src/cpu/samsung/exynos5250/setup.h
index 4f7f58cbeb..f205b4d176 100644
--- a/src/cpu/samsung/exynos5250/setup.h
+++ b/src/cpu/samsung/exynos5250/setup.h
@@ -702,9 +702,11 @@ void mem_ctrl_init(void);
* which the DMC uses to decide how to split a memory
* chunk into smaller chunks to support concurrent
* accesses; may vary across boards.
+ * @param mem_reset Reset memory during initialization.
* @return 0 if ok, SETUP_ERR_... if there is a problem
*/
-int ddr3_mem_ctrl_init(struct mem_timings *mem, unsigned long mem_iv_size);
+int ddr3_mem_ctrl_init(struct mem_timings *mem, unsigned long mem_iv_size,
+ int mem_reset);
void tzpc_init(void);
/*
diff --git a/src/mainboard/google/snow/romstage.c b/src/mainboard/google/snow/romstage.c
index 41b88e1e5f..edbe00919f 100644
--- a/src/mainboard/google/snow/romstage.c
+++ b/src/mainboard/google/snow/romstage.c
@@ -184,7 +184,7 @@ void main(void)
mem->mpll_mdiv,
mem->frequency_mhz);
- ret = ddr3_mem_ctrl_init(mem, DMC_INTERLEAVE_SIZE);
+ ret = ddr3_mem_ctrl_init(mem, DMC_INTERLEAVE_SIZE, 1);
if (ret) {
printk(BIOS_ERR, "Memory controller init failed, err: %x\n",
ret);