diff options
| -rw-r--r-- | src/drivers/intel/fsp2_0/Kconfig | 11 | ||||
| -rw-r--r-- | src/drivers/intel/fsp2_0/Makefile.inc | 3 |
2 files changed, 14 insertions, 0 deletions
diff --git a/src/drivers/intel/fsp2_0/Kconfig b/src/drivers/intel/fsp2_0/Kconfig index 8e64c6b0d2..3951e9a959 100644 --- a/src/drivers/intel/fsp2_0/Kconfig +++ b/src/drivers/intel/fsp2_0/Kconfig @@ -172,4 +172,15 @@ config FSP_PLATFORM_MEMORY_SETTINGS_VERSIONS This allows deployed systems to bump their version number with the same FSP which will trigger a retrain of the memory. +config FSP_PEIM_TO_PEIM_INTERFACE + bool + help + This option allows SOC user to create specific PPI for Intel FSP + usage, coreboot will provide required PPI structure definitions + along with all APIs as per EFI specification. + +if FSP_PEIM_TO_PEIM_INTERFACE +source "src/drivers/intel/fsp2_0/ppi/Kconfig" +endif + endif diff --git a/src/drivers/intel/fsp2_0/Makefile.inc b/src/drivers/intel/fsp2_0/Makefile.inc index 79fe5f8d3e..f26a776133 100644 --- a/src/drivers/intel/fsp2_0/Makefile.inc +++ b/src/drivers/intel/fsp2_0/Makefile.inc @@ -82,4 +82,7 @@ ifneq ($(call strip_quotes,$(CONFIG_FSP_HEADER_PATH)),) CPPFLAGS_common+=-I$(CONFIG_FSP_HEADER_PATH) endif +# Include PPI directory of CONFIG_FSP_PEIM_TO_PEIM_INTERFACE is enable +subdirs-$(CONFIG_FSP_PEIM_TO_PEIM_INTERFACE) += ppi + endif |