3 files changed, 27 insertions, 0 deletions

diff --git a/src/soc/rockchip/rk3399/clock.c b/src/soc/rockchip/rk3399/clock.c
index 383a761d60..eb413a1329 100644
--- a/src/soc/rockchip/rk3399/clock.c
+++ b/src/soc/rockchip/rk3399/clock.c
@@ -181,6 +181,13 @@ enum {
 	CLK_TSADC_DIV_CON_MASK		= 0x3ff,
 	CLK_TSADC_DIV_CON_SHIFT		= 0,
 
+	/* CLKSEL_CON44 */
+	CLK_PCLK_EDP_PLL_SEL_MASK	= 1,
+	CLK_PCLK_EDP_PLL_SEL_SHIFT	= 15,
+	CLK_PCLK_EDP_PLL_SEL_CPLL	= 0,
+	CLK_PCLK_EDP_DIV_CON_MASK	= 0x3f,
+	CLK_PCLK_EDP_DIV_CON_SHIFT	= 8,
+
 	/* CLKSEL_CON47 & CLKSEL_CON48 */
 	ACLK_VOP_PLL_SEL_MASK		= 0x3,
 	ACLK_VOP_PLL_SEL_SHIFT		= 6,
@@ -838,3 +845,21 @@ int rkclk_was_watchdog_reset(void)
 	/* Bits 5 and 4 are "second" and "first" global watchdog reset. */
 	return read32(&cru_ptr->glb_rst_st) & 0x30;
 }
+
+void rkclk_configure_edp(unsigned int hz)
+{
+	int src_clk_div;
+
+	src_clk_div = CPLL_HZ / hz;
+	assert((src_clk_div - 1 <= 63) && (src_clk_div * hz == CPLL_HZ));
+
+	write32(&cru_ptr->clksel_con[44],
+		RK_CLRSETBITS(CLK_PCLK_EDP_PLL_SEL_MASK <<
+			      CLK_PCLK_EDP_PLL_SEL_SHIFT |
+			      CLK_PCLK_EDP_DIV_CON_MASK <<
+			      CLK_PCLK_EDP_DIV_CON_SHIFT,
+			      CLK_PCLK_EDP_PLL_SEL_CPLL <<
+			      CLK_PCLK_EDP_PLL_SEL_SHIFT |
+			      (src_clk_div - 1) <<
+			      CLK_PCLK_EDP_DIV_CON_SHIFT));
+}
diff --git a/src/soc/rockchip/rk3399/display.c b/src/soc/rockchip/rk3399/display.c
index 5199bf3d34..c7ca8916ba 100644
--- a/src/soc/rockchip/rk3399/display.c
+++ b/src/soc/rockchip/rk3399/display.c
@@ -65,6 +65,7 @@ void rk_display_init(device_t dev)
 	case VOP_MODE_EDP:
 		printk(BIOS_DEBUG, "Attempting to set up EDP display.\n");
 		rkclk_configure_vop_aclk(vop_id, 200 * MHz);
+		rkclk_configure_edp(25 * MHz);
 
 		/* select edp signal from vop0 */
 		write32(&rk3399_grf->soc_con20, RK_CLRBITS(1 << 5));
diff --git a/src/soc/rockchip/rk3399/include/soc/clock.h b/src/soc/rockchip/rk3399/include/soc/clock.h
index 82bf215389..3047f738b0 100644
--- a/src/soc/rockchip/rk3399/include/soc/clock.h
+++ b/src/soc/rockchip/rk3399/include/soc/clock.h
@@ -119,5 +119,6 @@ void rkclk_configure_vop_aclk(u32 vop_id, u32 aclk_hz);
 void rkclk_ddr_reset(u32 ch, u32 ctl, u32 phy);
 int rkclk_was_watchdog_reset(void);
 uint32_t rkclk_i2c_clock_for_bus(unsigned bus);
+void rkclk_configure_edp(unsigned int hz);
 
 #endif	/* __SOC_ROCKCHIP_RK3399_CLOCK_H__ */