diff options
| -rw-r--r-- | src/cpu/intel/model_6ex/Config.lb | 1 | ||||
| -rw-r--r-- | src/cpu/intel/model_6ex/model_6ex_init.c | 51 | ||||
| -rw-r--r-- | src/cpu/intel/model_6fx/model_6fx_init.c | 22 | ||||
| -rw-r--r-- | src/cpu/intel/speedstep/Config.lb | 1 | ||||
| -rw-r--r-- | src/cpu/intel/speedstep/acpi.c | 137 | ||||
| -rw-r--r-- | src/cpu/x86/smm/smmrelocate.S | 8 |
6 files changed, 202 insertions, 18 deletions
diff --git a/src/cpu/intel/model_6ex/Config.lb b/src/cpu/intel/model_6ex/Config.lb index 79ff9b1eec..5aef8ff955 100644 --- a/src/cpu/intel/model_6ex/Config.lb +++ b/src/cpu/intel/model_6ex/Config.lb @@ -11,4 +11,5 @@ dir /cpu/x86/cache dir /cpu/x86/smm dir /cpu/intel/microcode dir /cpu/intel/hyperthreading +dir /cpu/intel/speedstep driver model_6ex_init.o diff --git a/src/cpu/intel/model_6ex/model_6ex_init.c b/src/cpu/intel/model_6ex/model_6ex_init.c index 3a5b59a541..d056bda733 100644 --- a/src/cpu/intel/model_6ex/model_6ex_init.c +++ b/src/cpu/intel/model_6ex/model_6ex_init.c @@ -111,30 +111,41 @@ static void enable_vmx(void) #define PMG_CST_CONFIG_CONTROL 0xe2 #define PMG_IO_BASE_ADDR 0xe3 #define PMG_IO_CAPTURE_ADDR 0xe4 -#define PMB0 0x510 /* analogous to P_BLK in cpu.asl */ -#define PMB1 0x0 /* IO port that triggers SMI once cores are in the same state. - See CSM Trigger, at PMG_CST_CONFIG_CONTROL[6:4] */ + +/* MWAIT coordination I/O base address. This must match + * the \_PR_.CPU0 PM base address. + */ +#define PMB0_BASE 0x510 + +/* PMB1: I/O port that triggers SMI once cores are in the same state. + * See CSM Trigger, at PMG_CST_CONFIG_CONTROL[6:4] + */ +#define PMB1_BASE 0x800 #define HIGHEST_CLEVEL 3 static void configure_c_states(void) { msr_t msr; msr = rdmsr(PMG_CST_CONFIG_CONTROL); - msr.lo |= (1 << 15); // Lock configuration - msr.lo |= (1 << 10); // redirect IO-based CState transition requests to MWAIT + msr.lo |= (1 << 15); // config lock until next reset. + msr.lo |= (1 << 10); // Enable I/O MWAIT redirection for C-States msr.lo &= ~(1 << 9); // Issue a single stop grant cycle upon stpclk - msr.lo &= ~7; msr.lo |= HIGHEST_CLEVEL; // support at most C3 // TODO Do we want Deep C4 and Dynamic L2 shrinking? + + /* Number of supported C-States */ + msr.lo &= ~7; + msr.lo |= HIGHEST_CLEVEL; // support at most C3 + wrmsr(PMG_CST_CONFIG_CONTROL, msr); - // set P_BLK address - msr = rdmsr(PMG_IO_BASE_ADDR); - msr.lo = PMB0+4 | (PMB1<<16); + /* Set Processor MWAIT IO BASE (P_BLK) */ + msr.hi = 0; + msr.lo = ((PMB0_BASE + 4) & 0xffff) | (((PMB1_BASE + 9) & 0xffff) << 16); wrmsr(PMG_IO_BASE_ADDR, msr); - // set C_LVL controls - msr = rdmsr(PMG_IO_CAPTURE_ADDR); - msr.lo = PMB0+4 | (HIGHEST_CLEVEL-2)<<16; // -2 because LVL0+1 aren't counted + /* set C_LVL controls */ + msr.hi = 0; + msr.lo = (PMB0_BASE + 4) | ((HIGHEST_CLEVEL - 2) << 16); // -2 because LVL0+1 aren't counted wrmsr(PMG_IO_CAPTURE_ADDR, msr); } @@ -160,6 +171,19 @@ static void configure_misc(void) wrmsr(IA32_MISC_ENABLE, msr); } +#define PIC_SENS_CFG 0x1aa +static void configure_pic_thermal_sensors(void) +{ + msr_t msr; + + msr = rdmsr(PIC_SENS_CFG); + + msr.lo |= (1 << 21); // inter-core lock TM1 + msr.lo |= (1 << 4); // Enable bypass filter + + wrmsr(PIC_SENS_CFG, msr); +} + #if CONFIG_USBDEBUG_DIRECT static unsigned ehci_debug_addr; #endif @@ -205,7 +229,8 @@ static void model_6ex_init(device_t cpu) /* Configure Enhanced SpeedStep and Thermal Sensors */ configure_misc(); - /* TODO: PIC thermal sensor control */ + /* PIC thermal sensor control */ + configure_pic_thermal_sensors(); /* Start up my cpu siblings */ intel_sibling_init(cpu); diff --git a/src/cpu/intel/model_6fx/model_6fx_init.c b/src/cpu/intel/model_6fx/model_6fx_init.c index d716efbd48..37eb81fabf 100644 --- a/src/cpu/intel/model_6fx/model_6fx_init.c +++ b/src/cpu/intel/model_6fx/model_6fx_init.c @@ -126,9 +126,16 @@ static void enable_vmx(void) #define PMG_IO_BASE_ADDR 0xe3 #define PMG_IO_CAPTURE_ADDR 0xe4 -#define PMB0_BASE 0x580 +/* MWAIT coordination I/O base address. This must match + * the \_PR_.CPU0 PM base address. + */ +#define PMB0_BASE 0x510 + +/* PMB1: I/O port that triggers SMI once cores are in the same state. + * See CSM Trigger, at PMG_CST_CONFIG_CONTROL[6:4] + */ #define PMB1_BASE 0x800 -#define CST_RANGE 2 +#define HIGHEST_CLEVEL 3 static void configure_c_states(void) { msr_t msr; @@ -141,6 +148,10 @@ static void configure_c_states(void) msr.lo &= ~(1 << 9); // Issue a single stop grant cycle upon stpclk msr.lo |= (1 << 3); // Dynamic L2 + /* Number of supported C-States */ + msr.lo &= ~7; + msr.lo |= HIGHEST_CLEVEL; // support at most C3 + wrmsr(PMG_CST_CONFIG_CONTROL, msr); /* Set Processor MWAIT IO BASE */ @@ -148,9 +159,9 @@ static void configure_c_states(void) msr.lo = ((PMB0_BASE + 4) & 0xffff) | (((PMB1_BASE + 9) & 0xffff) << 16); wrmsr(PMG_IO_BASE_ADDR, msr); - /* Set IO Capture Address */ + /* Set C_LVL controls and IO Capture Address */ msr.hi = 0; - msr.lo = ((PMB0_BASE + 4) & 0xffff) | (( CST_RANGE & 0xffff) << 16); + msr.lo = (PMB0_BASE + 4) | ((HIGHEST_CLEVEL - 2) << 16); // -2 because LVL0+1 aren't counted wrmsr(PMG_IO_CAPTURE_ADDR, msr); } @@ -229,6 +240,9 @@ static void model_6fx_init(device_t cpu) x86_setup_mtrrs(36); x86_mtrr_check(); + /* Setup Page Attribute Tables (PAT) */ + // TODO set up PAT + #if CONFIG_USBDEBUG_DIRECT set_ehci_debug(ehci_debug_addr); #endif diff --git a/src/cpu/intel/speedstep/Config.lb b/src/cpu/intel/speedstep/Config.lb new file mode 100644 index 0000000000..6a75160fbb --- /dev/null +++ b/src/cpu/intel/speedstep/Config.lb @@ -0,0 +1 @@ +object acpi.o diff --git a/src/cpu/intel/speedstep/acpi.c b/src/cpu/intel/speedstep/acpi.c new file mode 100644 index 0000000000..5bbb52fc02 --- /dev/null +++ b/src/cpu/intel/speedstep/acpi.c @@ -0,0 +1,137 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2009 coresystems GmbH + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; version 2 of + * the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, + * MA 02110-1301 USA + */ + +#include <types.h> +#include <console/console.h> +#include <arch/acpi.h> +#include <arch/acpigen.h> +#include <arch/cpu.h> +#include <cpu/x86/msr.h> +#include <device/device.h> + +// XXX: PSS table values for power consumption are for Merom only + +int determine_total_number_of_cores(void) +{ + device_t cpu; + int count = 0; + for(cpu = all_devices; cpu; cpu = cpu->next) { + if ((cpu->path.type != DEVICE_PATH_APIC) || + (cpu->bus->dev->path.type != DEVICE_PATH_APIC_CLUSTER)) { + continue; + } + if (!cpu->enabled) { + continue; + } + count++; + } + return count; +} + +int get_fsb(void) +{ + u32 fsbcode=(rdmsr(0xcd).lo >> 4) & 7; + switch (fsbcode) { + case 0: return 266; + case 1: return 133; + case 2: return 200; + case 3: return 166; + case 5: return 100; + } + printk_debug("Warning: No supported FSB frequency. Assuming 200MHz\n"); + return 200; +} + +void generate_cpu_entries(void) +{ + int len_sc, len_pr, len_ps; + int coreID, cpuID, pcontrol_blk=0x510, plen=6; + msr_t msr; + len_sc = acpigen_write_scope("\\_PR_"); + int totalcores = determine_total_number_of_cores(); + int cores_per_package = (cpuid_ebx(1)>>16) & 0xff; + int numcpus = totalcores/cores_per_package; // this assumes that all CPUs share the same layout + printk_debug("Found %d CPU(s) with %d core(s) each.\n", numcpus, cores_per_package); + + for (cpuID=1; cpuID <=numcpus; cpuID++) { + for (coreID=1; coreID<=cores_per_package; coreID++) { + if (coreID>1) { + pcontrol_blk = 0; + plen = 0; + } + len_pr = acpigen_write_processor((cpuID-1)*cores_per_package+coreID-1, pcontrol_blk, plen); + len_pr += acpigen_write_empty_PCT(); + len_pr += acpigen_write_PSD_package(cpuID-1,cores_per_package,SW_ANY); + len_pr += acpigen_write_name("_PSS"); + + int max_states=8; + int busratio_step=2; +#define IA32_PLATFORM_ID 0x017 +#define IA32_PERF_STS 0x198 + msr = rdmsr(IA32_PERF_STS); + int busratio_min=(msr.lo >> 24) & 0x1f; + int busratio_max=(msr.hi >> (40-32)) & 0x1f; + int vid_min=msr.lo & 0x3f; + msr = rdmsr(IA32_PLATFORM_ID); + int vid_max=msr.lo & 0x3f; + int clock_max=get_fsb()*busratio_max; + int clock_min=get_fsb()*busratio_min; + printk_debug("clocks between %d and %d MHz.\n", clock_min, clock_max); +#define MEROM_MIN_POWER 16000 +#define MEROM_MAX_POWER 35000 + int power_max=MEROM_MAX_POWER; + int power_min=MEROM_MIN_POWER; + + int num_states=(busratio_max-busratio_min)/busratio_step; + while (num_states > max_states-1) { + busratio_step <<= 1; + num_states >>= 1; + } + printk_debug("adding %x P-States between busratio %x and %x, incl. P0\n", num_states+1, busratio_min, busratio_max); + int vid_step=(vid_max-vid_min)/num_states; + int power_step=(power_max-power_min)/num_states; + int clock_step=(clock_max-clock_min)/num_states; + len_ps = acpigen_write_package(num_states+1); // for Super LFM, this must be increases by another one + len_ps += acpigen_write_PSS_package(clock_max /*mhz*/, power_max /*mW*/, 0 /*lat1*/, 0 /*lat2*/, (busratio_max<<8)|(vid_max) /*control*/, (busratio_max<<8)|(vid_max) /*status*/); + int current_busratio=busratio_min+((num_states-1)*busratio_step); + int current_vid=vid_min+((num_states-1)*vid_step); + int current_power=power_min+((num_states-1)*power_step); + int current_clock=clock_min+((num_states-1)*clock_step); + int i; + for (i=0;i<num_states; i++) { + len_ps += acpigen_write_PSS_package(current_clock /*mhz*/, current_power /*mW*/, 0 /*lat1*/, 0 /*lat2*/, (current_busratio<<8)|(current_vid) /*control*/, (current_busratio<<8)|(current_vid) /*status*/); + current_busratio -= busratio_step; + current_vid -= vid_step; + current_power -= power_step; + current_clock -= clock_step; + } + len_ps--; + acpigen_patch_len(len_ps); + len_pr += acpigen_write_PPC(0); + len_pr += len_ps; + len_pr--; + acpigen_patch_len(len_pr); + len_sc += len_pr; + } + } + acpigen_patch_len(len_sc-1); +} + diff --git a/src/cpu/x86/smm/smmrelocate.S b/src/cpu/x86/smm/smmrelocate.S index 136f5630a1..3d1d9d2664 100644 --- a/src/cpu/x86/smm/smmrelocate.S +++ b/src/cpu/x86/smm/smmrelocate.S @@ -20,7 +20,13 @@ */ #include <arch/asm.h> -#include "../../../../src/northbridge/intel/i945/ich7.h" + +// Make sure no stage 2 code is included: +#define __ROMCC__ + +// FIXME: Is this piece of code southbridge specific, or +// can it be cleaned up so this include is not required? +#include "../../../southbridge/intel/i82801gx/i82801gx.h" #undef DEBUG_SMM_RELOCATION //#define DEBUG_SMM_RELOCATION |