diff options
| -rw-r--r-- | src/mainboard/google/trogdor/board.h | 5 | ||||
| -rw-r--r-- | src/mainboard/google/trogdor/mainboard.c | 63 | ||||
| -rw-r--r-- | src/soc/qualcomm/sc7180/Kconfig | 4 | ||||
| -rw-r--r-- | src/soc/qualcomm/sc7180/Makefile.inc | 1 | ||||
| -rw-r--r-- | src/soc/qualcomm/sc7180/display/mdss.c | 191 |
5 files changed, 262 insertions, 2 deletions
diff --git a/src/mainboard/google/trogdor/board.h b/src/mainboard/google/trogdor/board.h index bd7222fefa..39661b5f21 100644 --- a/src/mainboard/google/trogdor/board.h +++ b/src/mainboard/google/trogdor/board.h @@ -13,6 +13,11 @@ #define GPIO_SD_CD_L GPIO(69) #define GPIO_AMP_ENABLE GPIO(23) +/* Display specific GPIOS */ +#define GPIO_BACKLIGHT_ENABLE GPIO(12) +#define GPIO_EDP_BRIDGE_ENABLE (CONFIG(TROGDOR_REV0) ? GPIO(14) : GPIO(104)) +#define GPIO_EN_PP3300_DX_EDP (CONFIG(TROGDOR_REV0) ? GPIO(106) : GPIO(30)) + void setup_chromeos_gpios(void); #endif /* _COREBOOT_SRC_MAINBOARD_GOOGLE_TROGDOR_BOARD_H_ */ diff --git a/src/mainboard/google/trogdor/mainboard.c b/src/mainboard/google/trogdor/mainboard.c index 349c3064c3..57f3a3ba0f 100644 --- a/src/mainboard/google/trogdor/mainboard.c +++ b/src/mainboard/google/trogdor/mainboard.c @@ -1,9 +1,21 @@ /* SPDX-License-Identifier: GPL-2.0-only */ +#include <bootmode.h> +#include <delay.h> #include <device/device.h> +#include <device/i2c_simple.h> +#include <drivers/ti/sn65dsi86bridge/sn65dsi86bridge.h> +#include <soc/display/mipi_dsi.h> +#include <soc/display/mdssreg.h> #include <soc/qupv3_config.h> +#include <soc/qupv3_i2c.h> #include <soc/usb.h> +#include "board.h" + +#define BRIDGE_BUS 0x2 +#define BRIDGE_CHIP 0x2d + static struct usb_board_data usb0_board_data = { .pll_bias_control_2 = 0x22, .imp_ctrl1 = 0x08, @@ -20,7 +32,6 @@ static void setup_usb(void) static void qi2s_configure_gpios(void) { - gpio_configure(GPIO(49), GPIO49_FUNC_MI2S_1_SCK, GPIO_NO_PULL, GPIO_8MA, GPIO_OUTPUT); @@ -34,7 +45,6 @@ static void qi2s_configure_gpios(void) static void load_qup_fw(void) { qupv3_se_fw_load_and_init(QUPV3_0_SE1, SE_PROTOCOL_SPI, MIXED); /* ESIM SPI */ - qupv3_se_fw_load_and_init(QUPV3_0_SE2, SE_PROTOCOL_I2C, MIXED); /* EDP Bridge I2C */ qupv3_se_fw_load_and_init(QUPV3_0_SE3, SE_PROTOCOL_UART, FIFO); /* BT UART */ qupv3_se_fw_load_and_init(QUPV3_0_SE4, SE_PROTOCOL_I2C, MIXED); /* Pen Detect I2C */ qupv3_se_fw_load_and_init(QUPV3_0_SE5, SE_PROTOCOL_I2C, MIXED); /* SAR I2C */ @@ -51,11 +61,60 @@ static void load_qup_fw(void) qupv3_se_fw_load_and_init(QUPV3_1_SE5, SE_PROTOCOL_I2C, MIXED); /* Codec I2C */ } +static void configure_display(void) +{ + printk(BIOS_INFO, "%s: Bridge gpio init\n", __func__); + + /* Bridge Enable GPIO */ + gpio_output(GPIO_EDP_BRIDGE_ENABLE, 1); + + /* PP3300 EDP power supply */ + gpio_output(GPIO_EN_PP3300_DX_EDP, 1); +} + +static void display_init(struct edid *edid) +{ + uint32_t dsi_bpp = 24; + uint32_t lanes = 4; + + if (mdss_dsi_config(edid, lanes, dsi_bpp)) + return; + + sn65dsi86_bridge_configure(BRIDGE_BUS, BRIDGE_CHIP, edid, lanes, dsi_bpp); + mdp_dsi_video_config(edid); + mdss_dsi_video_mode_config(edid, dsi_bpp); + mdp_dsi_video_on(); +} + +static void display_startup(void) +{ + static struct edid ed; + enum dp_pll_clk_src ref_clk = SN65_SEL_19MHZ; + + i2c_init(QUPV3_0_SE2, I2C_SPEED_FAST); /* EDP Bridge I2C */ + if (display_init_required()) { + configure_display(); + mdelay(250); /* Delay for the panel to be up */ + sn65dsi86_bridge_init(BRIDGE_BUS, BRIDGE_CHIP, ref_clk); + if (sn65dsi86_bridge_read_edid(BRIDGE_BUS, BRIDGE_CHIP, &ed) < 0) + return; + + printk(BIOS_INFO, "display init!\n"); + + /* Configure backlight */ + gpio_output(GPIO_BACKLIGHT_ENABLE, 1); + display_init(&ed); + set_vbe_mode_info_valid(&ed, (uintptr_t)0); + } else + printk(BIOS_INFO, "Skipping display init.\n"); +} + static void mainboard_init(struct device *dev) { setup_usb(); qi2s_configure_gpios(); load_qup_fw(); + display_startup(); } static void mainboard_enable(struct device *dev) diff --git a/src/soc/qualcomm/sc7180/Kconfig b/src/soc/qualcomm/sc7180/Kconfig index 17df0d036f..d543ef5134 100644 --- a/src/soc/qualcomm/sc7180/Kconfig +++ b/src/soc/qualcomm/sc7180/Kconfig @@ -13,6 +13,10 @@ config SOC_QUALCOMM_SC7180 select ARM64_USE_ARCH_TIMER select SOC_QUALCOMM_COMMON select HAVE_UART_SPECIAL + select BOOTBLOCK_CONSOLE + select MAINBOARD_HAS_NATIVE_VGA_INIT + select MAINBOARD_FORCE_NATIVE_VGA_INIT + select HAVE_LINEAR_FRAMEBUFFER if SOC_QUALCOMM_SC7180 diff --git a/src/soc/qualcomm/sc7180/Makefile.inc b/src/soc/qualcomm/sc7180/Makefile.inc index ec6ab6c162..eea38d9766 100644 --- a/src/soc/qualcomm/sc7180/Makefile.inc +++ b/src/soc/qualcomm/sc7180/Makefile.inc @@ -62,6 +62,7 @@ ramstage-$(CONFIG_DRIVERS_UART) += qupv3_uart.c ramstage-$(CONFIG_MAINBOARD_DO_NATIVE_VGA_INIT) += display/dsi_phy_pll.c ramstage-$(CONFIG_MAINBOARD_DO_NATIVE_VGA_INIT) += display/dsi_phy.c ramstage-$(CONFIG_MAINBOARD_DO_NATIVE_VGA_INIT) += display/dsi.c +ramstage-$(CONFIG_MAINBOARD_DO_NATIVE_VGA_INIT) += display/mdss.c ################################################################################ diff --git a/src/soc/qualcomm/sc7180/display/mdss.c b/src/soc/qualcomm/sc7180/display/mdss.c new file mode 100644 index 0000000000..2d6bf6fcd3 --- /dev/null +++ b/src/soc/qualcomm/sc7180/display/mdss.c @@ -0,0 +1,191 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <device/mmio.h> +#include <console/console.h> +#include <delay.h> +#include <edid.h> +#include <soc/display/mdssreg.h> + +#define MDSS_MDP_MAX_PREFILL_FETCH 25 + +static void mdss_source_pipe_config(struct edid *edid) +{ + uint32_t img_size, out_size, stride; + uint32_t fb_off = 0; + uint32_t flip_bits = 0; + uint32_t src_xy = 0; + uint32_t dst_xy = 0; + + /* write active region size*/ + img_size = (edid->mode.va << 16) | edid->mode.ha; + out_size = img_size; + stride = (edid->mode.ha * edid->framebuffer_bits_per_pixel/8); + + if (!fb_off) { /* left */ + dst_xy = (edid->mode.vborder << 16) | edid->mode.hborder; + src_xy = dst_xy; + } else { /* right */ + dst_xy = (edid->mode.vborder << 16); + src_xy = (edid->mode.vborder << 16) | fb_off; + } + + printk(BIOS_INFO, "%s: src=%x fb_off=%x src_xy=%x dst_xy=%x\n", + __func__, out_size, fb_off, src_xy, dst_xy); + + write32(&mdp_sspp->sspp_src_ystride0, stride); + write32(&mdp_sspp->sspp_src_size, out_size); + write32(&mdp_sspp->sspp_out_size, out_size); + write32(&mdp_sspp->sspp_src_xy, src_xy); + write32(&mdp_sspp->sspp_out_xy, dst_xy); + + /* Tight Packing 4bpp Alpha 8-bit A R B G */ + write32(&mdp_sspp->sspp_src_format, 0x000236ff); + write32(&mdp_sspp->sspp_src_unpack_pattern, 0x03020001); + + flip_bits |= BIT(31); + write32(&mdp_sspp->sspp_sw_pic_ext_c0_req_pixels, out_size); + write32(&mdp_sspp->sspp_sw_pic_ext_c1c2_req_pixels, out_size); + write32(&mdp_sspp->sspp_sw_pic_ext_c3_req_pixels, out_size); + write32(&mdp_sspp->sspp_src_op_mode, flip_bits); +} + +static void mdss_vbif_setup(void) +{ + write32(&vbif_rt->vbif_out_axi_amemtype_conf0, 0x33333333); + write32(&vbif_rt->vbif_out_axi_amemtype_conf1, 0x00333333); +} + +static void mdss_intf_tg_setup(struct edid *edid) +{ + uint32_t hsync_period, vsync_period; + uint32_t hsync_start_x, hsync_end_x; + uint32_t display_hctl, hsync_ctl, display_vstart, display_vend; + + hsync_period = edid->mode.ha + edid->mode.hbl; + vsync_period = edid->mode.va + edid->mode.vbl; + hsync_start_x = edid->mode.hbl - edid->mode.hso; + hsync_end_x = hsync_period - edid->mode.hso - 1; + display_vstart = (edid->mode.vbl - edid->mode.vso) * hsync_period; + display_vend = ((vsync_period - edid->mode.vso) * hsync_period) - 1; + hsync_ctl = (hsync_period << 16) | edid->mode.hspw; + display_hctl = (hsync_end_x << 16) | hsync_start_x; + + write32(&mdp_intf->intf_hsync_ctl, hsync_ctl); + write32(&mdp_intf->intf_vysnc_period_f0, + vsync_period * hsync_period); + write32(&mdp_intf->intf_vysnc_pulse_width_f0, + edid->mode.vspw * hsync_period); + write32(&mdp_intf->intf_disp_hctl, display_hctl); + write32(&mdp_intf->intf_disp_v_start_f0, display_vstart); + write32(&mdp_intf->intf_disp_v_end_f0, display_vend); + write32(&mdp_intf->intf_underflow_color, 0x00); + write32(&mdp_intf->intf_panel_format, 0x2100); +} + +static void mdss_intf_fetch_start_config(struct edid *edid) +{ + uint32_t v_total, h_total, fetch_start, vfp_start; + uint32_t prefetch_avail, prefetch_needed; + uint32_t fetch_enable = BIT(31); + + /* + * MDP programmable fetch is for MDP with rev >= 1.05. + * Programmable fetch is not needed if vertical back porch + * plus vertical puls width is >= 25. + */ + if ((edid->mode.vbl - edid->mode.vso) >= MDSS_MDP_MAX_PREFILL_FETCH) + return; + + /* + * Fetch should always be outside the active lines. If the fetching + * is programmed within active region, hardware behavior is unknown. + */ + v_total = edid->mode.va + edid->mode.vbl; + h_total = edid->mode.ha + edid->mode.hbl; + vfp_start = edid->mode.va + edid->mode.vbl - edid->mode.vso; + prefetch_avail = v_total - vfp_start; + prefetch_needed = MDSS_MDP_MAX_PREFILL_FETCH - edid->mode.vbl + edid->mode.vso; + + /* + * In some cases, vertical front porch is too high. In such cases limit + * the mdp fetch lines as the last (25 - vbp - vpw) lines of + * vertical front porch. + */ + if (prefetch_avail > prefetch_needed) + prefetch_avail = prefetch_needed; + + fetch_start = (v_total - prefetch_avail) * h_total + h_total + 1; + write32(&mdp_intf->intf_prof_fetch_start, fetch_start); + write32(&mdp_intf->intf_config, fetch_enable); +} + +static void mdss_layer_mixer_setup(struct edid *edid) +{ + uint32_t mdp_rgb_size; + uint32_t left_staging_level; + + /* write active region size*/ + mdp_rgb_size = (edid->mode.va << 16) | edid->mode.ha; + + write32(&mdp_layer_mixer->layer_out_size, mdp_rgb_size); + write32(&mdp_layer_mixer->layer_op_mode, 0x0); + for (int i = 0; i < 6; i++) { + write32(&mdp_layer_mixer->layer_blend[i].layer_blend_op, 0x100); + write32(&mdp_layer_mixer->layer_blend[i].layer_blend_const_alpha, 0x00ff0000); + } + + /* Enable border fill */ + left_staging_level = BIT(24); + left_staging_level |= BIT(1); + + /* Base layer for layer mixer 0 */ + write32(&mdp_ctl->ctl_layer0, left_staging_level); +} + +static void mdss_vbif_qos_remapper_setup(void) +{ + /* + * VBIF remapper registers are used for translating internal display hardware + * priority level (from 0 to 7) into system fabric priority level. + * These remapper settings are defined for all the clients which corresponds + * to the xin clients connected to SSPP on VBIF. + */ + write32(&vbif_rt->qos_rp_remap[0].vbif_xinl_qos_rp_remap, 0x00000003); + write32(&vbif_rt->qos_rp_remap[1].vbif_xinl_qos_rp_remap, 0x11111113); + write32(&vbif_rt->qos_rp_remap[2].vbif_xinl_qos_rp_remap, 0x22222224); + write32(&vbif_rt->qos_rp_remap[3].vbif_xinl_qos_rp_remap, 0x33333334); + write32(&vbif_rt->qos_rp_remap[4].vbif_xinl_qos_rp_remap, 0x44444445); + write32(&vbif_rt->qos_rp_remap[7].vbif_xinl_qos_rp_remap, 0x77777776); + write32(&vbif_rt->qos_lvl_remap[0].vbif_xinl_qos_lvl_remap, 0x00000003); + write32(&vbif_rt->qos_lvl_remap[1].vbif_xinl_qos_lvl_remap, 0x11111113); + write32(&vbif_rt->qos_lvl_remap[2].vbif_xinl_qos_lvl_remap, 0x22222224); + write32(&vbif_rt->qos_lvl_remap[3].vbif_xinl_qos_lvl_remap, 0x33333334); + write32(&vbif_rt->qos_lvl_remap[4].vbif_xinl_qos_lvl_remap, 0x44444445); + write32(&vbif_rt->qos_lvl_remap[5].vbif_xinl_qos_lvl_remap, 0x77777776); +} + +void mdp_dsi_video_config(struct edid *edid) +{ + mdss_intf_tg_setup(edid); + mdss_intf_fetch_start_config(edid); + mdss_vbif_setup(); + mdss_vbif_qos_remapper_setup(); + mdss_source_pipe_config(edid); + mdss_layer_mixer_setup(edid); + + /* Select Video Mode Interface */ + write32(&mdp_ctl->ctl_top, 0x0); + + /* PPB0 to INTF1 */ + write32(&mdp_ctl->ctl_intf_active, BIT(1)); + write32(&mdp_intf->intf_mux, 0x0F0000); +} + +void mdp_dsi_video_on(void) +{ + uint32_t ctl0_reg_val; + + ctl0_reg_val = VIG_0 | LAYER_MIXER_0 | CTL | INTF; + write32(&mdp_ctl->ctl_intf_flush, 0x2); + write32(&mdp_ctl->ctl_flush, ctl0_reg_val); +} |