diff options
| -rw-r--r-- | src/arch/i386/lib/console.c | 1 | ||||
| -rw-r--r-- | src/cpu/Kconfig | 1 | ||||
| -rw-r--r-- | src/include/lib.h | 22 | ||||
| -rw-r--r-- | src/lib/generic_sdram.c | 9 | ||||
| -rw-r--r-- | src/lib/ramtest.c | 2 | ||||
| -rw-r--r-- | src/mainboard/tyan/s2892/romstage.c | 1 | ||||
| -rw-r--r-- | src/pc80/serial.c | 2 |
7 files changed, 29 insertions, 9 deletions
diff --git a/src/arch/i386/lib/console.c b/src/arch/i386/lib/console.c index 2f4500cef1..6d07e1670b 100644 --- a/src/arch/i386/lib/console.c +++ b/src/arch/i386/lib/console.c @@ -4,6 +4,7 @@ #if CONFIG_USE_PRINTK_IN_CAR == 0 #include "console_print.c" #else /* CONFIG_USE_PRINTK_IN_CAR == 1 */ +#include <console/console.h> #include "console_printk.c" #endif /* CONFIG_USE_PRINTK_IN_CAR */ diff --git a/src/cpu/Kconfig b/src/cpu/Kconfig index c0cf76887f..8d7c1a39c4 100644 --- a/src/cpu/Kconfig +++ b/src/cpu/Kconfig @@ -48,6 +48,7 @@ config SSE config SSE2 bool + default n help Select SSE2 in your socket or model Kconfig if your CPU has SSE2 streaming SIMD instructions. Some parts of coreboot can be built diff --git a/src/include/lib.h b/src/include/lib.h index d8e4eec2c3..41b286a6b6 100644 --- a/src/include/lib.h +++ b/src/include/lib.h @@ -19,8 +19,15 @@ /* This file is for "nuisance prototypes" that have no other home. */ +#ifndef __LIB_H__ +#define __LIB_H__ + +#ifndef __ROMCC__ /* romcc doesn't support prototypes. */ + +#ifndef __PRE_RAM__ /* Conflicts with romcc_io.h */ /* Defined in src/lib/clog2.c */ unsigned long log2(unsigned long x); +#endif /* Defined in src/lib/lzma.c */ unsigned long ulzma(unsigned char *src, unsigned char *dst); @@ -28,3 +35,18 @@ unsigned long ulzma(unsigned char *src, unsigned char *dst); /* Defined in src/arch/i386/boot/gdt.c */ void move_gdt(void); +/* Defined in src/lib/ramtest.c */ +void ram_check(unsigned long start, unsigned long stop); + +/* Defined in src/pc80/serial.c */ +void uart_init(void); + +/* Defined in romstage.c */ +#if defined(CONFIG_CPU_AMD_LX) && CONFIG_CPU_AMD_LX +void cache_as_ram_main(void); +#else +void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx); +#endif + +#endif /* __ROMCC__ */ +#endif /* __LIB_H__ */ diff --git a/src/lib/generic_sdram.c b/src/lib/generic_sdram.c index cdb06cd73f..7be0537484 100644 --- a/src/lib/generic_sdram.c +++ b/src/lib/generic_sdram.c @@ -1,3 +1,4 @@ +#include <lib.h> /* Prototypes */ #ifndef RAMINIT_SYSINFO #define RAMINIT_SYSINFO 0 @@ -12,14 +13,6 @@ static inline void print_debug_sdram_8(const char *strval, uint32_t val) #endif } -void sdram_no_memory(void) -{ - print_err("No memory!!\r\n"); - while(1) { - hlt(); - } -} - /* Setup SDRAM */ #if RAMINIT_SYSINFO == 1 void sdram_initialize(int controllers, const struct mem_controller *ctrl, void *sysinfo) diff --git a/src/lib/ramtest.c b/src/lib/ramtest.c index 6268aaa6cd..d707bf2385 100644 --- a/src/lib/ramtest.c +++ b/src/lib/ramtest.c @@ -1,3 +1,5 @@ +#include <lib.h> /* Prototypes */ + static void write_phys(unsigned long addr, unsigned long value) { // Assembler in lib/ is very ugly. But we properly guarded diff --git a/src/mainboard/tyan/s2892/romstage.c b/src/mainboard/tyan/s2892/romstage.c index 875a6c0f0f..5eadda78e5 100644 --- a/src/mainboard/tyan/s2892/romstage.c +++ b/src/mainboard/tyan/s2892/romstage.c @@ -17,7 +17,6 @@ #include "option_table.h" #include "pc80/mc146818rtc_early.c" -#define post_code(x) outb(x, 0x80) #include "pc80/serial.c" #include "arch/i386/lib/console.c" #include "lib/ramtest.c" diff --git a/src/pc80/serial.c b/src/pc80/serial.c index cddce333b3..837d112338 100644 --- a/src/pc80/serial.c +++ b/src/pc80/serial.c @@ -1,3 +1,5 @@ +#include <lib.h> /* Prototypes */ + /* Base Address */ #ifndef CONFIG_TTYS0_BASE #define CONFIG_TTYS0_BASE 0x3f8 |