diff options
| -rw-r--r-- | src/mainboard/intel/icelake_rvp/variants/icl_u/devicetree.cb | 5 | ||||
| -rw-r--r-- | src/mainboard/intel/icelake_rvp/variants/icl_y/devicetree.cb | 5 | ||||
| -rw-r--r-- | src/soc/intel/icelake/acpi/cnvi.asl | 32 | ||||
| -rw-r--r-- | src/soc/intel/icelake/acpi/southbridge.asl | 3 | ||||
| -rw-r--r-- | src/soc/intel/icelake/chip.h | 1 |
5 files changed, 9 insertions, 37 deletions
diff --git a/src/mainboard/intel/icelake_rvp/variants/icl_u/devicetree.cb b/src/mainboard/intel/icelake_rvp/variants/icl_u/devicetree.cb index 426436ed4b..fb39b60e8d 100644 --- a/src/mainboard/intel/icelake_rvp/variants/icl_u/devicetree.cb +++ b/src/mainboard/intel/icelake_rvp/variants/icl_u/devicetree.cb @@ -95,7 +95,10 @@ chip soc/intel/icelake device pci 12.6 off end # GSPI #2 device pci 14.0 on end # USB xHCI device pci 14.1 off end # USB xDCI (OTG) - device pci 14.3 on end # CNVi wifi + chip drivers/intel/wifi + register "wake" = "GPE0_PME_B0" + device pci 14.3 on end # CNVi wifi + end device pci 14.5 on end # SDCard device pci 15.0 on end # I2C #0 device pci 15.1 on end # I2C #1 diff --git a/src/mainboard/intel/icelake_rvp/variants/icl_y/devicetree.cb b/src/mainboard/intel/icelake_rvp/variants/icl_y/devicetree.cb index 55b5aa34f1..b3a78269c6 100644 --- a/src/mainboard/intel/icelake_rvp/variants/icl_y/devicetree.cb +++ b/src/mainboard/intel/icelake_rvp/variants/icl_y/devicetree.cb @@ -79,7 +79,10 @@ chip soc/intel/icelake device pci 12.6 off end # GSPI #2 device pci 14.0 on end # USB xHCI device pci 14.1 off end # USB xDCI (OTG) - device pci 14.3 on end # CNVi wifi + chip drivers/intel/wifi + register "wake" = "GPE0_PME_B0" + device pci 14.3 on end # CNVi wifi + end device pci 14.5 on end # SDCard device pci 15.0 on end # I2C 0 device pci 15.1 on end # I2C #1 diff --git a/src/soc/intel/icelake/acpi/cnvi.asl b/src/soc/intel/icelake/acpi/cnvi.asl deleted file mode 100644 index 634c6090ad..0000000000 --- a/src/soc/intel/icelake/acpi/cnvi.asl +++ /dev/null @@ -1,32 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2018 Intel Corp. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#include <soc/pm.h> - -/* CNVi Controller 0:14.3 */ -Device (CNVI) { - Name(_ADR, 0x00140003) - - Name (_S3D, 3) /* D3 supported in S3 */ - Name (_S0W, 3) /* D3 can wake device in S0 */ - Name (_S3W, 3) /* D3 can wake system from S3 */ - - Name (_PRW, Package() { PME_B0_EN_BIT, 3 }) - - Method (_STA, 0) - { - Return (0xF) - } -} diff --git a/src/soc/intel/icelake/acpi/southbridge.asl b/src/soc/intel/icelake/acpi/southbridge.asl index ff323c40a3..5cdc940523 100644 --- a/src/soc/intel/icelake/acpi/southbridge.asl +++ b/src/soc/intel/icelake/acpi/southbridge.asl @@ -56,8 +56,5 @@ /* PCI _OSC */ #include <soc/intel/common/acpi/pci_osc.asl> -/* CNVi */ -#include "cnvi.asl" - /* GBe 0:1f.6 */ #include "pch_glan.asl" diff --git a/src/soc/intel/icelake/chip.h b/src/soc/intel/icelake/chip.h index bd31946ba7..12daea50c6 100644 --- a/src/soc/intel/icelake/chip.h +++ b/src/soc/intel/icelake/chip.h @@ -20,6 +20,7 @@ #include <drivers/i2c/designware/dw_i2c.h> #include <intelblocks/gspi.h> #include <stdint.h> +#include <soc/gpe.h> #include <soc/gpio.h> #include <soc/pch.h> #include <soc/gpio_defs.h> |