diff options
| -rw-r--r-- | src/soc/intel/icelake/Kconfig | 8 | ||||
| -rw-r--r-- | src/soc/intel/icelake/chip.h | 63 | ||||
| -rw-r--r-- | src/soc/intel/icelake/include/soc/serialio.h | 28 |
3 files changed, 62 insertions, 37 deletions
diff --git a/src/soc/intel/icelake/Kconfig b/src/soc/intel/icelake/Kconfig index c4ee841802..727fccee0f 100644 --- a/src/soc/intel/icelake/Kconfig +++ b/src/soc/intel/icelake/Kconfig @@ -126,6 +126,10 @@ config PCR_BASE_ADDRESS help This option allows you to select MMIO Base Address of sideband bus. +config MMCONF_BASE_ADDRESS + hex + default 0xc0000000 + config CPU_BCLK_MHZ int default 100 @@ -146,6 +150,10 @@ config SOC_INTEL_I2C_DEV_MAX int default 6 +config SOC_INTEL_UART_DEV_MAX + int + default 3 + # Clock divider parameters for 115200 baud rate config SOC_INTEL_COMMON_LPSS_UART_CLK_M_VAL hex diff --git a/src/soc/intel/icelake/chip.h b/src/soc/intel/icelake/chip.h index cb06fcb06a..c8653b2f8e 100644 --- a/src/soc/intel/icelake/chip.h +++ b/src/soc/intel/icelake/chip.h @@ -152,11 +152,16 @@ struct soc_intel_icelake_config { /* eMMC and SD */ uint8_t ScsEmmcHs400Enabled; /* Need to update DLL setting to get Emmc running at HS400 speed */ - uint8_t EmmcHs400DllNeed; - /* 0-39: number of active delay for RX strobe, unit is 125 psec */ - uint8_t EmmcHs400RxStrobeDll1; - /* 0-78: number of active delay for TX data, unit is 125 psec */ - uint8_t EmmcHs400TxDataDll; + uint8_t EmmcUseCustomDlls; + uint32_t EmmcTxCmdDelayRegValue; + uint32_t EmmcTxDataDelay1RegValue; + uint32_t EmmcTxDataDelay2RegValue; + uint32_t EmmcRxCmdDataDelay1RegValue; + uint32_t EmmcRxCmdDataDelay2RegValue; + uint32_t EmmcRxStrobeDelayRegValue; + + /* Enable if SD Card Power Enable Signal is Active High */ + uint8_t SdCardPowerEnableActiveHigh; /* Integrated Sensor */ uint8_t PchIshEnable; @@ -219,28 +224,27 @@ struct soc_intel_icelake_config { } DebugConsent; /* * SerialIO device mode selection: - * - * Device index: - * PchSerialIoIndexI2C0 - * PchSerialIoIndexI2C1 - * PchSerialIoIndexI2C2 - * PchSerialIoIndexI2C3 - * PchSerialIoIndexI2C4 - * PchSerialIoIndexI2C5 - * PchSerialIoIndexSPI0 - * PchSerialIoIndexSPI1 - * PchSerialIoIndexSPI2 - * PchSerialIoIndexUART0 - * PchSerialIoIndexUART1 - * PchSerialIoIndexUART2 - * - * Mode select: - * PchSerialIoDisabled - * PchSerialIoPci - * PchSerialIoAcpi - * PchSerialIoHidden + * PchSerialIoDisabled, + * PchSerialIoPci, + * PchSerialIoHidden, + * PchSerialIoLegacyUart, + * PchSerialIoSkipInit + */ + uint8_t SerialIoI2cMode[CONFIG_SOC_INTEL_I2C_DEV_MAX]; + uint8_t SerialIoGSpiMode[CONFIG_SOC_INTEL_COMMON_BLOCK_GSPI_MAX]; + uint8_t SerialIoUartMode[CONFIG_SOC_INTEL_UART_DEV_MAX]; + /* + * GSPIn Default Chip Select Mode: + * 0:Hardware Mode, + * 1:Software Mode */ - uint8_t SerialIoDevMode[PchSerialIoIndexMAX]; + uint8_t SerialIoGSpiCsMode[CONFIG_SOC_INTEL_COMMON_BLOCK_GSPI_MAX]; + /* + * GSPIn Default Chip Select State: + * 0: Low, + * 1: High + */ + uint8_t SerialIoGSpiCsState[CONFIG_SOC_INTEL_COMMON_BLOCK_GSPI_MAX]; /* GPIO SD card detect pin */ unsigned int sdcard_cd_gpio; @@ -251,6 +255,13 @@ struct soc_intel_icelake_config { /* Intel VT configuration */ uint8_t VtdDisable; uint8_t VmxEnable; + + /* CNVi BT Audio Offload: Enable/Disable BT Audio Offload. */ + enum { + PLATFORM_POR, + FORCE_ENABLE, + FORCE_DISABLE, + } CnviBtAudioOffload; }; typedef struct soc_intel_icelake_config config_t; diff --git a/src/soc/intel/icelake/include/soc/serialio.h b/src/soc/intel/icelake/include/soc/serialio.h index 30a48a146f..cdf55157ff 100644 --- a/src/soc/intel/icelake/include/soc/serialio.h +++ b/src/soc/intel/icelake/include/soc/serialio.h @@ -16,27 +16,33 @@ #ifndef _SERIALIO_H_ #define _SERIALIO_H_ -typedef enum { +enum { PchSerialIoDisabled, PchSerialIoPci, - PchSerialIoAcpi, PchSerialIoHidden, -} PCH_SERIAL_IO_MODE; + PchSerialIoLegacyUart, + PchSerialIoSkipInit +}; -typedef enum { +enum { PchSerialIoIndexI2C0, PchSerialIoIndexI2C1, PchSerialIoIndexI2C2, PchSerialIoIndexI2C3, PchSerialIoIndexI2C4, - PchSerialIoIndexI2C5, - PchSerialIoIndexSPI0, - PchSerialIoIndexSPI1, - PchSerialIoIndexSPI2, + PchSerialIoIndexI2C5 +}; + +enum { + PchSerialIoIndexGSPI0, + PchSerialIoIndexGSPI1, + PchSerialIoIndexGSPI2 +}; + +enum { PchSerialIoIndexUART0, PchSerialIoIndexUART1, - PchSerialIoIndexUART2, - PchSerialIoIndexMAX -} PCH_SERIAL_IO_CONTROLLER; + PchSerialIoIndexUART2 +}; #endif |