diff options
| -rw-r--r-- | src/soc/intel/apollolake/Kconfig | 1 | ||||
| -rw-r--r-- | src/soc/intel/apollolake/i2c_early.c | 8 | ||||
| -rw-r--r-- | src/soc/intel/apollolake/include/soc/i2c.h | 5 | ||||
| -rw-r--r-- | src/soc/intel/apollolake/include/soc/uart.h | 10 | ||||
| -rw-r--r-- | src/soc/intel/apollolake/uart_early.c | 24 |
5 files changed, 12 insertions, 36 deletions
diff --git a/src/soc/intel/apollolake/Kconfig b/src/soc/intel/apollolake/Kconfig index b8af418289..7ec97bf11c 100644 --- a/src/soc/intel/apollolake/Kconfig +++ b/src/soc/intel/apollolake/Kconfig @@ -53,6 +53,7 @@ config CPU_SPECIFIC_OPTIONS select SOC_INTEL_COMMON_ACPI select SOC_INTEL_COMMON_ACPI_WAKE_SOURCE select SOC_INTEL_COMMON_BLOCK + select SOC_INTEL_COMMON_BLOCK_LPSS select SOC_INTEL_COMMON_BLOCK_PCR select SOC_INTEL_COMMON_BLOCK_SA select SOC_INTEL_COMMON_BLOCK_RTC diff --git a/src/soc/intel/apollolake/i2c_early.c b/src/soc/intel/apollolake/i2c_early.c index bb002748f0..4eb2b86042 100644 --- a/src/soc/intel/apollolake/i2c_early.c +++ b/src/soc/intel/apollolake/i2c_early.c @@ -19,6 +19,7 @@ #include <device/device.h> #include <device/i2c.h> #include <device/pci_def.h> +#include <intelblocks/lpss.h> #include <soc/intel/common/lpss_i2c.h> #include <soc/i2c.h> #include <soc/iomap.h> @@ -32,8 +33,6 @@ static int i2c_early_init_bus(unsigned int bus) pci_devfn_t dev; int devfn; uintptr_t base; - uint32_t value; - void *reg; /* Find the PCI device for this bus controller */ devfn = i2c_bus_to_devfn(bus); @@ -64,10 +63,7 @@ static int i2c_early_init_bus(unsigned int bus) PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER); /* Take device out of reset */ - reg = (void *)(base + I2C_LPSS_REG_RESET); - value = read32(reg); - value |= I2C_LPSS_RESET_RELEASE_HC; - write32(reg, value); + lpss_reset_release(base); /* Initialize the controller */ if (lpss_i2c_init(bus, &config->i2c[bus]) < 0) { diff --git a/src/soc/intel/apollolake/include/soc/i2c.h b/src/soc/intel/apollolake/include/soc/i2c.h index f7778e514c..8839f1460a 100644 --- a/src/soc/intel/apollolake/include/soc/i2c.h +++ b/src/soc/intel/apollolake/include/soc/i2c.h @@ -20,11 +20,6 @@ #include <device/pci_def.h> #include <soc/pci_devs.h> -/* I2C Controller Reset in MMIO private region */ -#define I2C_LPSS_REG_RESET 0x204 -#define I2C_LPSS_RESET_RELEASE_HC ((1 << 1) | (1 << 0)) -#define I2C_LPSS_RESET_RELEASE_IDMA (1 << 2) - /* Convert I2C bus number to PCI device and function */ static inline int i2c_bus_to_devfn(unsigned int bus) { diff --git a/src/soc/intel/apollolake/include/soc/uart.h b/src/soc/intel/apollolake/include/soc/uart.h index 3c6759c0ac..c7ba4a657a 100644 --- a/src/soc/intel/apollolake/include/soc/uart.h +++ b/src/soc/intel/apollolake/include/soc/uart.h @@ -18,16 +18,6 @@ #ifndef _SOC_APOLLOLAKE_UART_H_ #define _SOC_APOLLOLAKE_UART_H_ -/* Clock is 100MHz * (M / N).*/ -#define UART_CLK 0x200 -# define UART_CLK_UPDATE (1 << 31) -# define UART_CLK_DIV_N(n) (((n) & 0x7fff) << 16) -# define UART_CLK_DIV_M(m) (((m) & 0x7fff) << 1) -# define UART_CLK_EN (1 << 0) -#define UART_RESET 0x204 -# define UART_RESET_DMA_EN (1 << 2) -# define UART_RESET_UART_EN (3 << 0) - void lpss_console_uart_init(void); /* Initialize the console UART including the pads for the configured UART. */ diff --git a/src/soc/intel/apollolake/uart_early.c b/src/soc/intel/apollolake/uart_early.c index 51aeedfeb6..0a32b715b0 100644 --- a/src/soc/intel/apollolake/uart_early.c +++ b/src/soc/intel/apollolake/uart_early.c @@ -17,16 +17,11 @@ #include <console/uart.h> #include <device/pci.h> +#include <intelblocks/lpss.h> #include <soc/gpio.h> #include <soc/uart.h> #include <soc/pci_devs.h> -static void lpss_uart_write(uint16_t reg, uint32_t val) -{ - uintptr_t base = CONFIG_CONSOLE_UART_BASE_ADDRESS | reg; - write32((void *)base, val); -} - static inline int invalid_uart_for_console(void) { /* There are actually only 2 UARTS, and they are named UART1 and @@ -38,28 +33,27 @@ static inline int invalid_uart_for_console(void) void lpss_console_uart_init(void) { - uint32_t clk_sel; + uintptr_t base = CONFIG_CONSOLE_UART_BASE_ADDRESS; device_t uart = _PCH_DEV(UART, CONFIG_UART_FOR_CONSOLE & 3); if (invalid_uart_for_console()) return; /* Enable BAR0 for the UART -- this is where the 8250 registers hide */ - pci_write_config32(uart, PCI_BASE_ADDRESS_0, - CONFIG_CONSOLE_UART_BASE_ADDRESS); + pci_write_config32(uart, PCI_BASE_ADDRESS_0, base); /* Enable memory access and bus master */ pci_write_config32(uart, PCI_COMMAND, PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER); /* Take UART out of reset */ - lpss_uart_write(UART_RESET, UART_RESET_UART_EN); + lpss_reset_release(base); - /* These values get us a 1.836 MHz clock (ideally we want 1.843 MHz) */ - clk_sel = UART_CLK_DIV_N(0x7fff) | UART_CLK_DIV_M(0x025a); - /* Set M and N divisor inputs and enable clock */ - lpss_uart_write(UART_CLK, clk_sel | UART_CLK_UPDATE); - lpss_uart_write(UART_CLK, clk_sel | UART_CLK_EN); + /* + * Set M and N divisor inputs and enable clock. These values + * get us a 1.836 MHz clock (ideally we want 1.843 MHz) + */ + lpss_clk_update(base, 0x025a, 0x7fff); } |