diff options
| -rw-r--r-- | src/arch/x86/include/arch/intel-family.h | 86 | ||||
| -rw-r--r-- | src/soc/intel/common/block/timer/timer.c | 64 |
2 files changed, 147 insertions, 3 deletions
diff --git a/src/arch/x86/include/arch/intel-family.h b/src/arch/x86/include/arch/intel-family.h new file mode 100644 index 0000000000..43eb0e6b34 --- /dev/null +++ b/src/arch/x86/include/arch/intel-family.h @@ -0,0 +1,86 @@ +/* + * This file is part of the coreboot project. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#ifndef ARCH_INTEL_FAMILY_H +#define ARCH_INTEL_FAMILY_H + +#define CPU_MODEL_INTEL_CORE_YONAH 0x0E + +#define CPU_MODEL_INTEL_CORE2_MEROM 0x0F +#define CPU_MODEL_INTEL_CORE2_MEROM_L 0x16 +#define CPU_MODEL_INTEL_CORE2_PENRYN 0x17 +#define CPU_MODEL_INTEL_CORE2_DUNNINGTON 0x1D + +#define CPU_MODEL_INTEL_NEHALEM 0x1E +/* Auburndale / Havendale */ +#define CPU_MODEL_INTEL_NEHALEM_G 0x1F +#define CPU_MODEL_INTEL_NEHALEM_EP 0x1A +#define CPU_MODEL_INTEL_NEHALEM_EX 0x2E + +#define CPU_MODEL_INTEL_WESTMERE 0x25 +#define CPU_MODEL_INTEL_WESTMERE_EP 0x2C +#define CPU_MODEL_INTEL_WESTMERE_EX 0x2F + +#define CPU_MODEL_INTEL_SANDYBRIDGE 0x2A +#define CPU_MODEL_INTEL_SANDYBRIDGE_X 0x2D +#define CPU_MODEL_INTEL_IVYBRIDGE 0x3A +#define CPU_MODEL_INTEL_IVYBRIDGE_X 0x3E + +#define CPU_MODEL_INTEL_HASWELL_CORE 0x3C +#define CPU_MODEL_INTEL_HASWELL_X 0x3F +#define CPU_MODEL_INTEL_HASWELL_ULT 0x45 +#define CPU_MODEL_INTEL_HASWELL_GT3E 0x46 + +#define CPU_MODEL_INTEL_BROADWELL_CORE 0x3D +#define CPU_MODEL_INTEL_BROADWELL_GT3E 0x47 +#define CPU_MODEL_INTEL_BROADWELL_X 0x4F +#define CPU_MODEL_INTEL_BROADWELL_XEON_D 0x56 + +#define CPU_MODEL_INTEL_SKYLAKE_MOBILE 0x4E +#define CPU_MODEL_INTEL_SKYLAKE_DESKTOP 0x5E +#define CPU_MODEL_INTEL_SKYLAKE_X 0x55 +#define CPU_MODEL_INTEL_KABYLAKE_MOBILE 0x8E +#define CPU_MODEL_INTEL_KABYLAKE_DESKTOP 0x9E +#define CPU_MODEL_INTEL_CANNONLAKE_MOBILE 0x66 +#define CPU_MODEL_INTEL_ICELAKE_MOBILE 0x7E + +/* "Small Core" Processors (Atom) */ + +#define CPU_MODEL_INTEL_ATOM_PINEVIEW 0x1C +#define CPU_MODEL_INTEL_ATOM_LINCROFT 0x26 +#define CPU_MODEL_INTEL_ATOM_PENWELL 0x27 +#define CPU_MODEL_INTEL_ATOM_CLOVERVIEW 0x35 +#define CPU_MODEL_INTEL_ATOM_CEDARVIEW 0x36 +/* BayTrail/BYT / Valleyview */ +#define CPU_MODEL_INTEL_ATOM_SILVERMONT1 0x37 +/* Avaton/Rangely */ +#define CPU_MODEL_INTEL_ATOM_SILVERMONT2 0x4D +/* CherryTrail / Braswell */ +#define CPU_MODEL_INTEL_ATOM_AIRMONT 0x4C +/* Tangier */ +#define CPU_MODEL_INTEL_ATOM_MERRIFIELD 0x4A +/* Anniedale */ +#define CPU_MODEL_INTEL_ATOM_MOOREFIELD 0x5A +#define CPU_MODEL_INTEL_ATOM_GOLDMONT 0x5C +/* Goldmont Microserver */ +#define CPU_MODEL_INTEL_ATOM_DENVERTON 0x5F +#define CPU_MODEL_INTEL_ATOM_GEMINI_LAKE 0x7A + +/* Xeon Phi */ + +/* Knights Landing */ +#define CPU_MODEL_INTEL_XEON_PHI_KNL 0x57 +/* Knights Mill */ +#define CPU_MODEL_INTEL_XEON_PHI_KNM 0x85 + +#endif /* ARCH_INTEL_FAMILY_H */ diff --git a/src/soc/intel/common/block/timer/timer.c b/src/soc/intel/common/block/timer/timer.c index 12988856e4..e60ac4d26d 100644 --- a/src/soc/intel/common/block/timer/timer.c +++ b/src/soc/intel/common/block/timer/timer.c @@ -1,7 +1,7 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2017 Intel Corporation. + * Copyright (C) 2017-2019 Intel Corporation. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by @@ -13,12 +13,70 @@ * GNU General Public License for more details. */ +#include <arch/cpu.h> +#include <arch/intel-family.h> +#include <cpu/cpu.h> #include <cpu/x86/msr.h> #include <cpu/x86/tsc.h> #include <intelblocks/msr.h> +static int get_processor_model(void) +{ + struct cpuinfo_x86 c; + + get_fms(&c, cpuid_eax(1)); + + return c.x86_model; +} + +/* + * Nominal TSC frequency = "core crystal clock frequency" * EBX/EAX + * + * Time Stamp Counter + * CPUID Initial EAX value = 0x15 + * EAX Bit 31-0 : An unsigned integer which is the denominator of the + * TSC/"core crystal clock" ratio + * EBX Bit 31-0 : An unsigned integer which is the numerator of the + * TSC/"core crystal clock" ratio + * ECX Bit 31-0 : An unsigned integer which is the nominal frequency of the + * core crystal clock in Hz. + * EDX Bit 31-0 : Reserved = 0 + * + * Refer to Intel SDM Jan 2019 Vol 3B Section 18.7.3 + */ unsigned long tsc_freq_mhz(void) { - msr_t msr = rdmsr(MSR_PLATFORM_INFO); - return (CONFIG_CPU_BCLK_MHZ * ((msr.lo >> 8) & 0xff)); + unsigned int core_crystal_nominal_freq_khz; + struct cpuid_result cpuidr; + + /* CPUID 15H TSC/Crystal ratio, plus optionally Crystal Hz */ + cpuidr = cpuid(0x15); + + if (!cpuidr.ebx || !cpuidr.eax) + return 0; + + core_crystal_nominal_freq_khz = cpuidr.ecx / 1000; + + if (!core_crystal_nominal_freq_khz) { + switch (get_processor_model()) { + case CPU_MODEL_INTEL_SKYLAKE_MOBILE: + case CPU_MODEL_INTEL_SKYLAKE_DESKTOP: + case CPU_MODEL_INTEL_KABYLAKE_MOBILE: + case CPU_MODEL_INTEL_KABYLAKE_DESKTOP: + case CPU_MODEL_INTEL_CANNONLAKE_MOBILE: + case CPU_MODEL_INTEL_ICELAKE_MOBILE: + core_crystal_nominal_freq_khz = 24000; + break; + case CPU_MODEL_INTEL_ATOM_DENVERTON: + core_crystal_nominal_freq_khz = 25000; + break; + case CPU_MODEL_INTEL_ATOM_GOLDMONT: + case CPU_MODEL_INTEL_ATOM_GEMINI_LAKE: + core_crystal_nominal_freq_khz = 19200; + break; + } + } + + return (core_crystal_nominal_freq_khz * cpuidr.ebx / cpuidr.eax) / + 1000; } |