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-rw-r--r--src/vendorcode/amd/agesa/f10/AGESA.h4
-rw-r--r--src/vendorcode/amd/agesa/f14/AGESA.h4
-rw-r--r--src/vendorcode/amd/agesa/f14/Proc/GNB/GnbPage.h12
-rw-r--r--src/vendorcode/amd/agesa/f15/AGESA.h4
-rw-r--r--src/vendorcode/amd/agesa/f15/Include/GnbPage.h12
-rw-r--r--src/vendorcode/amd/agesa/f15tn/AGESA.h4
-rw-r--r--src/vendorcode/amd/agesa/f15tn/Include/GnbPage.h12
7 files changed, 26 insertions, 26 deletions
diff --git a/src/vendorcode/amd/agesa/f10/AGESA.h b/src/vendorcode/amd/agesa/f10/AGESA.h
index c50086deac..e6f5cfbce0 100644
--- a/src/vendorcode/amd/agesa/f10/AGESA.h
+++ b/src/vendorcode/amd/agesa/f10/AGESA.h
@@ -792,13 +792,13 @@ typedef struct {
* {
* 0, //Descriptor flags
* PCIE_ENGINE_DATA_INITIALIZER (PcieDdiEngine, 24, 27),
- * PCIE_DDI_DATA_INITIALIZER (ConnectorTypeDP, Aux1, Hdp1, 0)
+ * PCIE_DDI_DATA_INITIALIZER (ConnectorTypeDP, Aux1, Hdp1)
* },
* // Initialize Ddi descriptor (DDI interface Lanes 28:31, HDMI, ...)
* {
* DESCRIPTOR_TERMINATE_LIST, //Descriptor flags !!!IMPORTANT!!! Terminate last element of array
* PCIE_ENGINE_DATA_INITIALIZER (PcieDdiEngine, 28, 31),
- * PCIE_DDI_DATA_INITIALIZER (ConnectorTypeHDMI, Aux2, Hdp2, 0)
+ * PCIE_DDI_DATA_INITIALIZER (ConnectorTypeHDMI, Aux2, Hdp2)
* }
* };
* PCIe_COMPLEX_DESCRIPTOR PlatformTopology = {
diff --git a/src/vendorcode/amd/agesa/f14/AGESA.h b/src/vendorcode/amd/agesa/f14/AGESA.h
index 3333976c49..2a9bed1da1 100644
--- a/src/vendorcode/amd/agesa/f14/AGESA.h
+++ b/src/vendorcode/amd/agesa/f14/AGESA.h
@@ -905,13 +905,13 @@ typedef struct {
* {
* 0, //Descriptor flags
* PCIE_ENGINE_DATA_INITIALIZER (PcieDdiEngine, 24, 27),
- * PCIE_DDI_DATA_INITIALIZER (ConnectorTypeDP, Aux1, Hdp1, 0)
+ * PCIE_DDI_DATA_INITIALIZER (ConnectorTypeDP, Aux1, Hdp1)
* },
* // Initialize Ddi descriptor (DDI interface Lanes 28:31, HDMI, ...)
* {
* DESCRIPTOR_TERMINATE_LIST, //Descriptor flags !!!IMPORTANT!!! Terminate last element of array
* PCIE_ENGINE_DATA_INITIALIZER (PcieDdiEngine, 28, 31),
- * PCIE_DDI_DATA_INITIALIZER (ConnectorTypeHDMI, Aux2, Hdp2, 0)
+ * PCIE_DDI_DATA_INITIALIZER (ConnectorTypeHDMI, Aux2, Hdp2)
* }
* };
* PCIe_COMPLEX_DESCRIPTOR PlatformTopology = {
diff --git a/src/vendorcode/amd/agesa/f14/Proc/GNB/GnbPage.h b/src/vendorcode/amd/agesa/f14/Proc/GNB/GnbPage.h
index fec1603c8b..ecc9ca6a74 100644
--- a/src/vendorcode/amd/agesa/f14/Proc/GNB/GnbPage.h
+++ b/src/vendorcode/amd/agesa/f14/Proc/GNB/GnbPage.h
@@ -121,7 +121,7 @@
* {
* DESCRIPTOR_TERMINATE_LIST, //Descriptor flags
* PCIE_ENGINE_DATA_INITIALIZER (PcieDdiEngine, 24, 32),
- * PCIE_DDI_DATA_INITIALIZER (ConnectorTypeDualLinkDvi, Aux1, Hdp1, 0)
+ * PCIE_DDI_DATA_INITIALIZER (ConnectorTypeDualLinkDvi, Aux1, Hdp1)
* }
* }
* // Dual Link DVI on dedicated display lanes. DP0_TXP/N[0]..DP0_TXP/N[3] - master, DP1_TXP/N[0]..DP1_TXP/N[3] - slave.
@@ -129,7 +129,7 @@
* {
* DESCRIPTOR_TERMINATE_LIST, //Descriptor flags
* PCIE_ENGINE_DATA_INITIALIZER (PcieDdiEngine, 32, 24),
- * PCIE_DDI_DATA_INITIALIZER (ConnectorTypeDualLinkDvi, Aux1, Hdp1, 0)
+ * PCIE_DDI_DATA_INITIALIZER (ConnectorTypeDualLinkDvi, Aux1, Hdp1)
* }
* }
* // Dual Link DVI on PCIe lanes. P_GFX_TXP/N[0]..P_GFX_TXP/N[3] - master, P_GFX_TXP/N[4]..P_GFX_TXP/N[7] - slave.
@@ -137,7 +137,7 @@
* {
* DESCRIPTOR_TERMINATE_LIST, //Descriptor flags
* PCIE_ENGINE_DATA_INITIALIZER (PcieDdiEngine, 8, 15),
- * PCIE_DDI_DATA_INITIALIZER (ConnectorTypeDualLinkDvi, Aux1, Hdp1, 0)
+ * PCIE_DDI_DATA_INITIALIZER (ConnectorTypeDualLinkDvi, Aux1, Hdp1)
* }
* }
* // Dual Link DVI on PCIe lanes. P_GFX_TXP/N[7]..P_GFX_TXP/N[4] - master, P_GFX_TXP/N[0]..P_GFX_TXP/N[3] - slave.
@@ -145,7 +145,7 @@
* {
* DESCRIPTOR_TERMINATE_LIST, //Descriptor flags
* PCIE_ENGINE_DATA_INITIALIZER (PcieDdiEngine, 15, 8),
- * PCIE_DDI_DATA_INITIALIZER (ConnectorTypeDualLinkDvi, Aux1, Hdp1, 0)
+ * PCIE_DDI_DATA_INITIALIZER (ConnectorTypeDualLinkDvi, Aux1, Hdp1)
* }
* }
* // Dual Link DVI on PCIe lanes. P_GFX_TXP/N[8]..P_GFX_TXP/N[11] - master, P_GFX_TXP/N[12]..P_GFX_TXP/N[15] - slave.
@@ -153,7 +153,7 @@
* {
* DESCRIPTOR_TERMINATE_LIST, //Descriptor flags
* PCIE_ENGINE_DATA_INITIALIZER (PcieDdiEngine, 16, 23),
- * PCIE_DDI_DATA_INITIALIZER (ConnectorTypeDualLinkDvi, Aux1, Hdp1, 0)
+ * PCIE_DDI_DATA_INITIALIZER (ConnectorTypeDualLinkDvi, Aux1, Hdp1)
* }
* }
* // Dual Link DVI on PCIe lanes. P_GFX_TXP/N[12]..P_GFX_TXP/N[15] - master, P_GFX_TXP/N[8]..P_GFX_TXP/N[11] - slave.
@@ -161,7 +161,7 @@
* {
* DESCRIPTOR_TERMINATE_LIST, //Descriptor flags
* PCIE_ENGINE_DATA_INITIALIZER (PcieDdiEngine, 23, 16),
- * PCIE_DDI_DATA_INITIALIZER (ConnectorTypeDualLinkDvi, Aux1, Hdp1, 0)
+ * PCIE_DDI_DATA_INITIALIZER (ConnectorTypeDualLinkDvi, Aux1, Hdp1)
* }
* }
* @endcode
diff --git a/src/vendorcode/amd/agesa/f15/AGESA.h b/src/vendorcode/amd/agesa/f15/AGESA.h
index b18659e0ea..6b0171b269 100644
--- a/src/vendorcode/amd/agesa/f15/AGESA.h
+++ b/src/vendorcode/amd/agesa/f15/AGESA.h
@@ -1173,13 +1173,13 @@ typedef struct {
* {
* 0, //Descriptor flags
* PCIE_ENGINE_DATA_INITIALIZER (PcieDdiEngine, 24, 27),
- * PCIE_DDI_DATA_INITIALIZER (ConnectorTypeDP, Aux1, Hdp1, 0)
+ * PCIE_DDI_DATA_INITIALIZER (ConnectorTypeDP, Aux1, Hdp1)
* },
* // Initialize Ddi descriptor (DDI interface Lanes 28:31, HDMI, ...)
* {
* DESCRIPTOR_TERMINATE_LIST, //Descriptor flags !!!IMPORTANT!!! Terminate last element of array
* PCIE_ENGINE_DATA_INITIALIZER (PcieDdiEngine, 28, 31),
- * PCIE_DDI_DATA_INITIALIZER (ConnectorTypeHDMI, Aux2, Hdp2, 0)
+ * PCIE_DDI_DATA_INITIALIZER (ConnectorTypeHDMI, Aux2, Hdp2)
* }
* };
* PCIe_COMPLEX_DESCRIPTOR PlatformTopology = {
diff --git a/src/vendorcode/amd/agesa/f15/Include/GnbPage.h b/src/vendorcode/amd/agesa/f15/Include/GnbPage.h
index 2ccdfc593a..b571128a79 100644
--- a/src/vendorcode/amd/agesa/f15/Include/GnbPage.h
+++ b/src/vendorcode/amd/agesa/f15/Include/GnbPage.h
@@ -139,7 +139,7 @@
* {
* DESCRIPTOR_TERMINATE_LIST, //Descriptor flags
* PCIE_ENGINE_DATA_INITIALIZER (PcieDdiEngine, 24, 32),
- * PCIE_DDI_DATA_INITIALIZER (ConnectorTypeDualLinkDvi, Aux1, Hdp1, 0)
+ * PCIE_DDI_DATA_INITIALIZER (ConnectorTypeDualLinkDvi, Aux1, Hdp1)
* }
* }
* // Dual Link DVI on dedicated display lanes. DP0_TXP/N[0]..DP0_TXP/N[3] - master, DP1_TXP/N[0]..DP1_TXP/N[3] - slave.
@@ -147,7 +147,7 @@
* {
* DESCRIPTOR_TERMINATE_LIST, //Descriptor flags
* PCIE_ENGINE_DATA_INITIALIZER (PcieDdiEngine, 32, 24),
- * PCIE_DDI_DATA_INITIALIZER (ConnectorTypeDualLinkDvi, Aux1, Hdp1, 0)
+ * PCIE_DDI_DATA_INITIALIZER (ConnectorTypeDualLinkDvi, Aux1, Hdp1)
* }
* }
* // Dual Link DVI on PCIe lanes. P_GFX_TXP/N[0]..P_GFX_TXP/N[3] - master, P_GFX_TXP/N[4]..P_GFX_TXP/N[7] - slave.
@@ -155,7 +155,7 @@
* {
* DESCRIPTOR_TERMINATE_LIST, //Descriptor flags
* PCIE_ENGINE_DATA_INITIALIZER (PcieDdiEngine, 8, 15),
- * PCIE_DDI_DATA_INITIALIZER (ConnectorTypeDualLinkDvi, Aux1, Hdp1, 0)
+ * PCIE_DDI_DATA_INITIALIZER (ConnectorTypeDualLinkDvi, Aux1, Hdp1)
* }
* }
* // Dual Link DVI on PCIe lanes. P_GFX_TXP/N[7]..P_GFX_TXP/N[4] - master, P_GFX_TXP/N[0]..P_GFX_TXP/N[3] - slave.
@@ -163,7 +163,7 @@
* {
* DESCRIPTOR_TERMINATE_LIST, //Descriptor flags
* PCIE_ENGINE_DATA_INITIALIZER (PcieDdiEngine, 15, 8),
- * PCIE_DDI_DATA_INITIALIZER (ConnectorTypeDualLinkDvi, Aux1, Hdp1, 0)
+ * PCIE_DDI_DATA_INITIALIZER (ConnectorTypeDualLinkDvi, Aux1, Hdp1)
* }
* }
* // Dual Link DVI on PCIe lanes. P_GFX_TXP/N[8]..P_GFX_TXP/N[11] - master, P_GFX_TXP/N[12]..P_GFX_TXP/N[15] - slave.
@@ -171,7 +171,7 @@
* {
* DESCRIPTOR_TERMINATE_LIST, //Descriptor flags
* PCIE_ENGINE_DATA_INITIALIZER (PcieDdiEngine, 16, 23),
- * PCIE_DDI_DATA_INITIALIZER (ConnectorTypeDualLinkDvi, Aux1, Hdp1, 0)
+ * PCIE_DDI_DATA_INITIALIZER (ConnectorTypeDualLinkDvi, Aux1, Hdp1)
* }
* }
* // Dual Link DVI on PCIe lanes. P_GFX_TXP/N[12]..P_GFX_TXP/N[15] - master, P_GFX_TXP/N[8]..P_GFX_TXP/N[11] - slave.
@@ -179,7 +179,7 @@
* {
* DESCRIPTOR_TERMINATE_LIST, //Descriptor flags
* PCIE_ENGINE_DATA_INITIALIZER (PcieDdiEngine, 23, 16),
- * PCIE_DDI_DATA_INITIALIZER (ConnectorTypeDualLinkDvi, Aux1, Hdp1, 0)
+ * PCIE_DDI_DATA_INITIALIZER (ConnectorTypeDualLinkDvi, Aux1, Hdp1)
* }
* }
* @endcode
diff --git a/src/vendorcode/amd/agesa/f15tn/AGESA.h b/src/vendorcode/amd/agesa/f15tn/AGESA.h
index fdd02df1ef..9bd2e88369 100644
--- a/src/vendorcode/amd/agesa/f15tn/AGESA.h
+++ b/src/vendorcode/amd/agesa/f15tn/AGESA.h
@@ -1299,13 +1299,13 @@ typedef struct {
* {
* 0, //Descriptor flags
* PCIE_ENGINE_DATA_INITIALIZER (PcieDdiEngine, 24, 27),
- * PCIE_DDI_DATA_INITIALIZER (ConnectorTypeDP, Aux1, Hdp1, 0)
+ * PCIE_DDI_DATA_INITIALIZER (ConnectorTypeDP, Aux1, Hdp1)
* },
* // Initialize Ddi descriptor (DDI interface Lanes 28:31, HDMI, ...)
* {
* DESCRIPTOR_TERMINATE_LIST, //Descriptor flags !!!IMPORTANT!!! Terminate last element of array
* PCIE_ENGINE_DATA_INITIALIZER (PcieDdiEngine, 28, 31),
- * PCIE_DDI_DATA_INITIALIZER (ConnectorTypeHDMI, Aux2, Hdp2, 0)
+ * PCIE_DDI_DATA_INITIALIZER (ConnectorTypeHDMI, Aux2, Hdp2)
* }
* };
* PCIe_COMPLEX_DESCRIPTOR PlatformTopology = {
diff --git a/src/vendorcode/amd/agesa/f15tn/Include/GnbPage.h b/src/vendorcode/amd/agesa/f15tn/Include/GnbPage.h
index 9c051c5669..aae2e40d15 100644
--- a/src/vendorcode/amd/agesa/f15tn/Include/GnbPage.h
+++ b/src/vendorcode/amd/agesa/f15tn/Include/GnbPage.h
@@ -166,7 +166,7 @@
* {
* DESCRIPTOR_TERMINATE_LIST, //Descriptor flags
* PCIE_ENGINE_DATA_INITIALIZER (PcieDdiEngine, 24, 32),
- * PCIE_DDI_DATA_INITIALIZER (ConnectorTypeDualLinkDvi, Aux1, Hdp1, 0)
+ * PCIE_DDI_DATA_INITIALIZER (ConnectorTypeDualLinkDvi, Aux1, Hdp1)
* }
* }
* // Dual Link DVI on dedicated display lanes. DP0_TXP/N[0]..DP0_TXP/N[3] - master, DP1_TXP/N[0]..DP1_TXP/N[3] - slave.
@@ -174,7 +174,7 @@
* {
* DESCRIPTOR_TERMINATE_LIST, //Descriptor flags
* PCIE_ENGINE_DATA_INITIALIZER (PcieDdiEngine, 32, 24),
- * PCIE_DDI_DATA_INITIALIZER (ConnectorTypeDualLinkDvi, Aux1, Hdp1, 0)
+ * PCIE_DDI_DATA_INITIALIZER (ConnectorTypeDualLinkDvi, Aux1, Hdp1)
* }
* }
* // Dual Link DVI on PCIe lanes. P_GFX_TXP/N[0]..P_GFX_TXP/N[3] - master, P_GFX_TXP/N[4]..P_GFX_TXP/N[7] - slave.
@@ -182,7 +182,7 @@
* {
* DESCRIPTOR_TERMINATE_LIST, //Descriptor flags
* PCIE_ENGINE_DATA_INITIALIZER (PcieDdiEngine, 8, 15),
- * PCIE_DDI_DATA_INITIALIZER (ConnectorTypeDualLinkDvi, Aux1, Hdp1, 0)
+ * PCIE_DDI_DATA_INITIALIZER (ConnectorTypeDualLinkDvi, Aux1, Hdp1)
* }
* }
* // Dual Link DVI on PCIe lanes. P_GFX_TXP/N[7]..P_GFX_TXP/N[4] - master, P_GFX_TXP/N[0]..P_GFX_TXP/N[3] - slave.
@@ -190,7 +190,7 @@
* {
* DESCRIPTOR_TERMINATE_LIST, //Descriptor flags
* PCIE_ENGINE_DATA_INITIALIZER (PcieDdiEngine, 15, 8),
- * PCIE_DDI_DATA_INITIALIZER (ConnectorTypeDualLinkDvi, Aux1, Hdp1, 0)
+ * PCIE_DDI_DATA_INITIALIZER (ConnectorTypeDualLinkDvi, Aux1, Hdp1)
* }
* }
* // Dual Link DVI on PCIe lanes. P_GFX_TXP/N[8]..P_GFX_TXP/N[11] - master, P_GFX_TXP/N[12]..P_GFX_TXP/N[15] - slave.
@@ -198,7 +198,7 @@
* {
* DESCRIPTOR_TERMINATE_LIST, //Descriptor flags
* PCIE_ENGINE_DATA_INITIALIZER (PcieDdiEngine, 16, 23),
- * PCIE_DDI_DATA_INITIALIZER (ConnectorTypeDualLinkDvi, Aux1, Hdp1, 0)
+ * PCIE_DDI_DATA_INITIALIZER (ConnectorTypeDualLinkDvi, Aux1, Hdp1)
* }
* }
* // Dual Link DVI on PCIe lanes. P_GFX_TXP/N[12]..P_GFX_TXP/N[15] - master, P_GFX_TXP/N[8]..P_GFX_TXP/N[11] - slave.
@@ -206,7 +206,7 @@
* {
* DESCRIPTOR_TERMINATE_LIST, //Descriptor flags
* PCIE_ENGINE_DATA_INITIALIZER (PcieDdiEngine, 23, 16),
- * PCIE_DDI_DATA_INITIALIZER (ConnectorTypeDualLinkDvi, Aux1, Hdp1, 0)
+ * PCIE_DDI_DATA_INITIALIZER (ConnectorTypeDualLinkDvi, Aux1, Hdp1)
* }
* }
* @endcode
generated by cgit v1.2.3 (git 2.25.1) at 2024-10-30 00:56:17 +0000