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-rw-r--r--src/soc/intel/cannonlake/fsp_params.c21
-rw-r--r--src/soc/intel/icelake/fsp_params.c20
-rw-r--r--src/soc/intel/jasperlake/fsp_params.c14
-rw-r--r--src/soc/intel/skylake/chip.c13
-rw-r--r--src/soc/intel/tigerlake/fsp_params.c12
5 files changed, 50 insertions, 30 deletions
diff --git a/src/soc/intel/cannonlake/fsp_params.c b/src/soc/intel/cannonlake/fsp_params.c
index 615a94f32e..63a85c2db0 100644
--- a/src/soc/intel/cannonlake/fsp_params.c
+++ b/src/soc/intel/cannonlake/fsp_params.c
@@ -262,15 +262,6 @@ void platform_fsp_silicon_init_params_cb(FSPS_UPD *supd)
/* Load VBT before devicetree-specific config. */
params->GraphicsConfigPtr = (uintptr_t)vbt_get();
- /* Set USB OC pin to 0 first */
- for (i = 0; i < ARRAY_SIZE(params->Usb2OverCurrentPin); i++) {
- params->Usb2OverCurrentPin[i] = 0;
- }
-
- for (i = 0; i < ARRAY_SIZE(params->Usb3OverCurrentPin); i++) {
- params->Usb3OverCurrentPin[i] = 0;
- }
-
mainboard_silicon_init_params(params);
const struct soc_power_limits_config *soc_config;
@@ -379,12 +370,16 @@ void platform_fsp_silicon_init_params_cb(FSPS_UPD *supd)
/* USB */
for (i = 0; i < ARRAY_SIZE(config->usb2_ports); i++) {
params->PortUsb20Enable[i] = config->usb2_ports[i].enable;
- params->Usb2OverCurrentPin[i] = config->usb2_ports[i].ocpin;
params->Usb2AfePetxiset[i] = config->usb2_ports[i].pre_emp_bias;
params->Usb2AfeTxiset[i] = config->usb2_ports[i].tx_bias;
params->Usb2AfePredeemp[i] =
config->usb2_ports[i].tx_emp_enable;
params->Usb2AfePehalfbit[i] = config->usb2_ports[i].pre_emp_bit;
+
+ if (config->usb2_ports[i].enable)
+ params->Usb2OverCurrentPin[i] = config->usb2_ports[i].ocpin;
+ else
+ params->Usb2OverCurrentPin[i] = 0xff;
}
if (config->PchUsb2PhySusPgDisable)
@@ -392,7 +387,11 @@ void platform_fsp_silicon_init_params_cb(FSPS_UPD *supd)
for (i = 0; i < ARRAY_SIZE(config->usb3_ports); i++) {
params->PortUsb30Enable[i] = config->usb3_ports[i].enable;
- params->Usb3OverCurrentPin[i] = config->usb3_ports[i].ocpin;
+ if (config->usb3_ports[i].enable) {
+ params->Usb3OverCurrentPin[i] = config->usb3_ports[i].ocpin;
+ } else {
+ params->Usb3OverCurrentPin[i] = 0xff;
+ }
if (config->usb3_ports[i].tx_de_emp) {
params->Usb3HsioTxDeEmphEnable[i] = 1;
params->Usb3HsioTxDeEmph[i] =
diff --git a/src/soc/intel/icelake/fsp_params.c b/src/soc/intel/icelake/fsp_params.c
index 0130d2c3a3..8e33174345 100644
--- a/src/soc/intel/icelake/fsp_params.c
+++ b/src/soc/intel/icelake/fsp_params.c
@@ -64,13 +64,6 @@ void platform_fsp_silicon_init_params_cb(FSPS_UPD *supd)
/* Load VBT before devicetree-specific config. */
params->GraphicsConfigPtr = (uintptr_t)vbt_get();
- /* Set USB OC pin to 0 first */
- for (i = 0; i < ARRAY_SIZE(params->Usb2OverCurrentPin); i++)
- params->Usb2OverCurrentPin[i] = 0;
-
- for (i = 0; i < ARRAY_SIZE(params->Usb3OverCurrentPin); i++)
- params->Usb3OverCurrentPin[i] = 0;
-
/* Use coreboot MP PPI services if Kconfig is enabled */
if (CONFIG(USE_INTEL_FSP_TO_CALL_COREBOOT_PUBLISH_MP_PPI))
params->CpuMpPpi = (uintptr_t) mp_fill_ppi_services_data();
@@ -135,8 +128,6 @@ void platform_fsp_silicon_init_params_cb(FSPS_UPD *supd)
for (i = 0; i < ARRAY_SIZE(config->usb2_ports); i++) {
params->PortUsb20Enable[i] =
config->usb2_ports[i].enable;
- params->Usb2OverCurrentPin[i] =
- config->usb2_ports[i].ocpin;
params->Usb2PhyPetxiset[i] =
config->usb2_ports[i].pre_emp_bias;
params->Usb2PhyTxiset[i] =
@@ -145,11 +136,20 @@ void platform_fsp_silicon_init_params_cb(FSPS_UPD *supd)
config->usb2_ports[i].tx_emp_enable;
params->Usb2PhyPehalfbit[i] =
config->usb2_ports[i].pre_emp_bit;
+
+ if (config->usb2_ports[i].enable)
+ params->Usb2OverCurrentPin[i] = config->usb2_ports[i].ocpin;
+ else
+ params->Usb2OverCurrentPin[i] = 0xff;
}
for (i = 0; i < ARRAY_SIZE(config->usb3_ports); i++) {
params->PortUsb30Enable[i] = config->usb3_ports[i].enable;
- params->Usb3OverCurrentPin[i] = config->usb3_ports[i].ocpin;
+ if (config->usb3_ports[i].enable) {
+ params->Usb3OverCurrentPin[i] = config->usb3_ports[i].ocpin;
+ } else {
+ params->Usb3OverCurrentPin[i] = 0xff;
+ }
if (config->usb3_ports[i].tx_de_emp) {
params->Usb3HsioTxDeEmphEnable[i] = 1;
params->Usb3HsioTxDeEmph[i] =
diff --git a/src/soc/intel/jasperlake/fsp_params.c b/src/soc/intel/jasperlake/fsp_params.c
index 40be0d45bf..b787192f6f 100644
--- a/src/soc/intel/jasperlake/fsp_params.c
+++ b/src/soc/intel/jasperlake/fsp_params.c
@@ -253,19 +253,25 @@ void platform_fsp_silicon_init_params_cb(FSPS_UPD *supd)
/* USB configuration */
for (i = 0; i < ARRAY_SIZE(config->usb2_ports); i++) {
-
params->PortUsb20Enable[i] = config->usb2_ports[i].enable;
- params->Usb2OverCurrentPin[i] = config->usb2_ports[i].ocpin;
params->Usb2PhyPetxiset[i] = config->usb2_ports[i].pre_emp_bias;
params->Usb2PhyTxiset[i] = config->usb2_ports[i].tx_bias;
params->Usb2PhyPredeemp[i] = config->usb2_ports[i].tx_emp_enable;
params->Usb2PhyPehalfbit[i] = config->usb2_ports[i].pre_emp_bit;
+
+ if (config->usb2_ports[i].enable)
+ params->Usb2OverCurrentPin[i] = config->usb2_ports[i].ocpin;
+ else
+ params->Usb2OverCurrentPin[i] = 0xff;
}
for (i = 0; i < ARRAY_SIZE(config->usb3_ports); i++) {
-
params->PortUsb30Enable[i] = config->usb3_ports[i].enable;
- params->Usb3OverCurrentPin[i] = config->usb3_ports[i].ocpin;
+ if (config->usb3_ports[i].enable) {
+ params->Usb3OverCurrentPin[i] = config->usb3_ports[i].ocpin;
+ } else {
+ params->Usb3OverCurrentPin[i] = 0xff;
+ }
if (config->usb3_ports[i].tx_de_emp) {
params->Usb3HsioTxDeEmphEnable[i] = 1;
params->Usb3HsioTxDeEmph[i] = config->usb3_ports[i].tx_de_emp;
diff --git a/src/soc/intel/skylake/chip.c b/src/soc/intel/skylake/chip.c
index e96d624ad2..a0bcac7bad 100644
--- a/src/soc/intel/skylake/chip.c
+++ b/src/soc/intel/skylake/chip.c
@@ -139,8 +139,6 @@ void platform_fsp_silicon_init_params_cb(FSPS_UPD *supd)
for (i = 0; i < ARRAY_SIZE(config->usb2_ports); i++) {
params->PortUsb20Enable[i] =
config->usb2_ports[i].enable;
- params->Usb2OverCurrentPin[i] =
- config->usb2_ports[i].ocpin;
params->Usb2AfePetxiset[i] =
config->usb2_ports[i].pre_emp_bias;
params->Usb2AfeTxiset[i] =
@@ -149,11 +147,20 @@ void platform_fsp_silicon_init_params_cb(FSPS_UPD *supd)
config->usb2_ports[i].tx_emp_enable;
params->Usb2AfePehalfbit[i] =
config->usb2_ports[i].pre_emp_bit;
+
+ if (config->usb2_ports[i].enable)
+ params->Usb2OverCurrentPin[i] = config->usb2_ports[i].ocpin;
+ else
+ params->Usb2OverCurrentPin[i] = 0xff;
}
for (i = 0; i < ARRAY_SIZE(config->usb3_ports); i++) {
params->PortUsb30Enable[i] = config->usb3_ports[i].enable;
- params->Usb3OverCurrentPin[i] = config->usb3_ports[i].ocpin;
+ if (config->usb3_ports[i].enable) {
+ params->Usb3OverCurrentPin[i] = config->usb3_ports[i].ocpin;
+ } else {
+ params->Usb3OverCurrentPin[i] = 0xff;
+ }
if (config->usb3_ports[i].tx_de_emp) {
params->Usb3HsioTxDeEmphEnable[i] = 1;
params->Usb3HsioTxDeEmph[i] =
diff --git a/src/soc/intel/tigerlake/fsp_params.c b/src/soc/intel/tigerlake/fsp_params.c
index 1601c2c58d..73a620d465 100644
--- a/src/soc/intel/tigerlake/fsp_params.c
+++ b/src/soc/intel/tigerlake/fsp_params.c
@@ -148,16 +148,24 @@ void platform_fsp_silicon_init_params_cb(FSPS_UPD *supd)
/* USB */
for (i = 0; i < ARRAY_SIZE(config->usb2_ports); i++) {
params->PortUsb20Enable[i] = config->usb2_ports[i].enable;
- params->Usb2OverCurrentPin[i] = config->usb2_ports[i].ocpin;
params->Usb2PhyPetxiset[i] = config->usb2_ports[i].pre_emp_bias;
params->Usb2PhyTxiset[i] = config->usb2_ports[i].tx_bias;
params->Usb2PhyPredeemp[i] = config->usb2_ports[i].tx_emp_enable;
params->Usb2PhyPehalfbit[i] = config->usb2_ports[i].pre_emp_bit;
+
+ if (config->usb2_ports[i].enable)
+ params->Usb2OverCurrentPin[i] = config->usb2_ports[i].ocpin;
+ else
+ params->Usb2OverCurrentPin[i] = 0xff;
}
for (i = 0; i < ARRAY_SIZE(config->usb3_ports); i++) {
params->PortUsb30Enable[i] = config->usb3_ports[i].enable;
- params->Usb3OverCurrentPin[i] = config->usb3_ports[i].ocpin;
+ if (config->usb3_ports[i].enable) {
+ params->Usb3OverCurrentPin[i] = config->usb3_ports[i].ocpin;
+ } else {
+ params->Usb3OverCurrentPin[i] = 0xff;
+ }
if (config->usb3_ports[i].tx_de_emp) {
params->Usb3HsioTxDeEmphEnable[i] = 1;
params->Usb3HsioTxDeEmph[i] = config->usb3_ports[i].tx_de_emp;
generated by cgit v1.2.3 (git 2.39.1) at 2024-07-05 23:36:32 +0000