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-rw-r--r--src/northbridge/intel/haswell/Kconfig8
-rw-r--r--src/northbridge/intel/haswell/gma.c19
2 files changed, 26 insertions, 1 deletions
diff --git a/src/northbridge/intel/haswell/Kconfig b/src/northbridge/intel/haswell/Kconfig
index f68978040f..12f865a2e3 100644
--- a/src/northbridge/intel/haswell/Kconfig
+++ b/src/northbridge/intel/haswell/Kconfig
@@ -82,6 +82,14 @@ config DCACHE_RAM_ROMSTAGE_STACK_SIZE
The amount of anticipated stack usage from the data cache
during pre-ram rom stage execution.
+config MARK_GRAPHICS_MEM_WRCOMB
+ bool "Mark graphics memory as write-combining."
+ default n
+ help
+ The graphics performance may increase if the graphics
+ memory is set as write-combining cache type. This option
+ enables marking the graphics memory as write-combining.
+
config HAVE_MRC
bool "Add a System Agent binary"
help
diff --git a/src/northbridge/intel/haswell/gma.c b/src/northbridge/intel/haswell/gma.c
index d0850667ac..0a67b6a851 100644
--- a/src/northbridge/intel/haswell/gma.c
+++ b/src/northbridge/intel/haswell/gma.c
@@ -217,12 +217,29 @@ static void gma_set_subsystem(device_t dev, unsigned vendor, unsigned device)
}
}
+static void gma_read_resources(struct device *dev)
+{
+ pci_dev_read_resources(dev);
+
+#if CONFIG_MARK_GRAPHICS_MEM_WRCOMB
+ struct resource *res;
+
+ /* Set the graphics memory to write combining. */
+ res = find_resource(dev, PCI_BASE_ADDRESS_2);
+ if (res == NULL) {
+ printk(BIOS_DEBUG, "gma: memory resource not found.\n");
+ return;
+ }
+ res->flags |= IORESOURCE_WRCOMB;
+#endif
+}
+
static struct pci_operations gma_pci_ops = {
.set_subsystem = gma_set_subsystem,
};
static struct device_operations gma_func0_ops = {
- .read_resources = pci_dev_read_resources,
+ .read_resources = gma_read_resources,
.set_resources = pci_dev_set_resources,
.enable_resources = pci_dev_enable_resources,
.init = gma_func0_init,