diff options
| -rw-r--r-- | src/soc/intel/apollolake/Makefile.inc | 4 | ||||
| -rw-r--r-- | src/soc/intel/apollolake/heci.c | 36 | ||||
| -rw-r--r-- | src/soc/intel/apollolake/include/soc/heci.h | 43 | ||||
| -rw-r--r-- | src/soc/intel/apollolake/include/soc/pci_devs.h | 3 |
4 files changed, 86 insertions, 0 deletions
diff --git a/src/soc/intel/apollolake/Makefile.inc b/src/soc/intel/apollolake/Makefile.inc index c44fc464d5..fda3523454 100644 --- a/src/soc/intel/apollolake/Makefile.inc +++ b/src/soc/intel/apollolake/Makefile.inc @@ -13,6 +13,7 @@ bootblock-y += bootblock/cache_as_ram.S bootblock-y += bootblock/bootblock.c bootblock-y += car.c bootblock-y += gpio.c +bootblock-y += heci.c bootblock-y += itss.c bootblock-y += lpc_lib.c bootblock-y += mmap_boot.c @@ -24,6 +25,7 @@ bootblock-$(CONFIG_SOC_UART_DEBUG) += uart_early.c romstage-y += car.c romstage-$(CONFIG_PLATFORM_USES_FSP2_0) += romstage.c romstage-y += gpio.c +romstage-y += heci.c romstage-y += i2c_early.c romstage-y += itss.c romstage-$(CONFIG_SOC_UART_DEBUG) += uart_early.c @@ -49,6 +51,7 @@ ramstage-y += chip.c ramstage-y += dsp.c ramstage-y += gpio.c ramstage-y += graphics.c +ramstage-y += heci.c ramstage-y += i2c.c ramstage-y += itss.c ramstage-$(CONFIG_SOC_UART_DEBUG) += uart_early.c @@ -77,6 +80,7 @@ postcar-y += tsc_freq.c verstage-y += car.c verstage-y += i2c_early.c +verstage-y += heci.c verstage-y += memmap.c verstage-y += mmap_boot.c verstage-$(CONFIG_SOC_UART_DEBUG) += uart_early.c diff --git a/src/soc/intel/apollolake/heci.c b/src/soc/intel/apollolake/heci.c new file mode 100644 index 0000000000..468589531c --- /dev/null +++ b/src/soc/intel/apollolake/heci.c @@ -0,0 +1,36 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2016 Intel Corp. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <device/device.h> +#include <device/pci_def.h> +#include <device/pci_ops.h> +#include <soc/heci.h> +#include <soc/pci_devs.h> + +uint32_t heci_fw_sts(void) +{ + return pci_read_config32(CSE_DEV, REG_SEC_FW_STS0); +} + +bool heci_cse_normal(void) +{ + return ((heci_fw_sts() & MASK_SEC_STATUS) == SEC_STATE_NORMAL); +} + +bool heci_cse_done(void) +{ + return (!!(heci_fw_sts() & MASK_SEC_FIRMWARE_COMPLETE)); +} diff --git a/src/soc/intel/apollolake/include/soc/heci.h b/src/soc/intel/apollolake/include/soc/heci.h new file mode 100644 index 0000000000..1151321445 --- /dev/null +++ b/src/soc/intel/apollolake/include/soc/heci.h @@ -0,0 +1,43 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2016 Intel Corp. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#ifndef _SOC_APOLLOLAKE_HECI_H_ +#define _SOC_APOLLOLAKE_HECI_H_ + +enum sec_status { + SEC_STATE_RESET = 0, + SEC_STATE_INIT, + SEC_STATE_RECOVERY, + SEC_STATE_UNKNOWN0, + SEC_STATE_UNKNOWN1, + SEC_STATE_NORMAL, + SEC_STATE_DISABLE_WAIT, + SEC_STATE_TRANSITION, + SEC_STATE_INVALID_CPU +}; + +#define REG_SEC_FW_STS0 0x40 +#define MASK_SEC_FIRMWARE_COMPLETE (1 << 9) +#define MASK_SEC_STATUS 0xf + +/* Read Firmware Status register */ +uint32_t heci_fw_sts(void); +/* Returns true if CSE is in normal status */ +bool heci_cse_normal(void); +/* Returns true if CSE is done with whatever it was doing */ +bool heci_cse_done(void); + +#endif diff --git a/src/soc/intel/apollolake/include/soc/pci_devs.h b/src/soc/intel/apollolake/include/soc/pci_devs.h index f29784d974..b7519ed799 100644 --- a/src/soc/intel/apollolake/include/soc/pci_devs.h +++ b/src/soc/intel/apollolake/include/soc/pci_devs.h @@ -46,6 +46,9 @@ #define HDA_DEV _PCI_DEV(0xe, 0) #define HDA_DEVFN _PCI_DEVFN(0xe, 0) +#define CSE_DEV _PCI_DEV(0xf, 0) +#define CSE_DEVFN _PCI_DEVFN(0xf, 0) + #define ISH_DEV _PCI_DEV(0x11, 0) #define ISH_DEVFN _PCI_DEVFN(0x11, 0) |