diff options
| -rw-r--r-- | src/soc/intel/broadwell/igd.c | 21 | ||||
| -rw-r--r-- | src/soc/intel/broadwell/include/soc/igd.h | 20 | ||||
| -rw-r--r-- | src/soc/intel/broadwell/minihd.c | 5 |
3 files changed, 46 insertions, 0 deletions
diff --git a/src/soc/intel/broadwell/igd.c b/src/soc/intel/broadwell/igd.c index ccb1e93604..c1cfdd81d7 100644 --- a/src/soc/intel/broadwell/igd.c +++ b/src/soc/intel/broadwell/igd.c @@ -31,6 +31,7 @@ #include <soc/systemagent.h> #include <soc/intel/broadwell/chip.h> #include <vboot/vbnv.h> +#include <soc/igd.h> #define GT_RETRY 1000 #define GT_CDCLK_337 0 @@ -38,6 +39,12 @@ #define GT_CDCLK_540 2 #define GT_CDCLK_675 3 +static u32 reg_em4; +static u32 reg_em5; + +u32 igd_get_reg_em4(void) { return reg_em4; } +u32 igd_get_reg_em5(void) { return reg_em5; } + struct reg_script haswell_early_init_script[] = { /* Enable Force Wake */ REG_RES_WRITE32(PCI_BASE_ADDRESS_0, 0xa180, 0x00000020), @@ -364,14 +371,20 @@ static void igd_cdclk_init_haswell(struct device *dev) case GT_CDCLK_337: dpdiv = 169; lpcll = (1 << 26); + reg_em4 = 16; + reg_em5 = 225; break; case GT_CDCLK_450: dpdiv = 225; lpcll = 0; + reg_em4 = 4; + reg_em5 = 75; break; case GT_CDCLK_540: dpdiv = 270; lpcll = (1 << 26); + reg_em4 = 4; + reg_em5 = 90; break; default: return; @@ -432,24 +445,32 @@ static void igd_cdclk_init_broadwell(struct device *dev) lpcll = (1 << 27); pwctl = 2; dpdiv = 169; + reg_em4 = 16; + reg_em5 = 225; break; case GT_CDCLK_450: cdset = 449; lpcll = 0; pwctl = 0; dpdiv = 225; + reg_em4 = 4; + reg_em5 = 75; break; case GT_CDCLK_540: cdset = 539; lpcll = (1 << 26); pwctl = 1; dpdiv = 270; + reg_em4 = 4; + reg_em5 = 90; break; case GT_CDCLK_675: cdset = 674; lpcll = (1 << 26) | (1 << 27); pwctl = 3; dpdiv = 338; + reg_em4 = 8; + reg_em5 = 225; default: return; } diff --git a/src/soc/intel/broadwell/include/soc/igd.h b/src/soc/intel/broadwell/include/soc/igd.h new file mode 100644 index 0000000000..e7d3777045 --- /dev/null +++ b/src/soc/intel/broadwell/include/soc/igd.h @@ -0,0 +1,20 @@ +/* + * This file is part of the coreboot project. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#ifndef SOC_INTEL_BROADWELL_GMA_H +#define SOC_INTEL_BROADWELL_GMA_H + +u32 igd_get_reg_em4(void); +u32 igd_get_reg_em5(void); + +#endif /* SOC_INTEL_BROADWELL_GMA_H */
\ No newline at end of file diff --git a/src/soc/intel/broadwell/minihd.c b/src/soc/intel/broadwell/minihd.c index 5014b08e7b..a9fc3d688b 100644 --- a/src/soc/intel/broadwell/minihd.c +++ b/src/soc/intel/broadwell/minihd.c @@ -25,6 +25,7 @@ #include <stdlib.h> #include <soc/intel/common/hda_verb.h> #include <soc/ramstage.h> +#include <soc/igd.h> static const u32 minihd_verb_table[] = { /* coreboot specific header */ @@ -101,6 +102,10 @@ static void minihd_init(struct device *dev) minihd_verb_table); } } + + /* Set EM4/EM5 registers */ + write32(base + 0x0100c, igd_get_reg_em4()); + write32(base + 0x01010, igd_get_reg_em5()); } static struct device_operations minihd_ops = { |