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-rw-r--r--src/soc/intel/alderlake/Kconfig10
-rw-r--r--src/vendorcode/intel/fsp/fsp2_0/alderlake/FirmwareVersionInfoHob.h68
-rw-r--r--src/vendorcode/intel/fsp/fsp2_0/alderlake/FspUpd.h48
-rw-r--r--src/vendorcode/intel/fsp/fsp2_0/alderlake/FspmUpd.h947
-rw-r--r--src/vendorcode/intel/fsp/fsp2_0/alderlake/FspsUpd.h902
-rw-r--r--src/vendorcode/intel/fsp/fsp2_0/alderlake/MemInfoHob.h293
6 files changed, 2268 insertions, 0 deletions
diff --git a/src/soc/intel/alderlake/Kconfig b/src/soc/intel/alderlake/Kconfig
index ee1e871ebb..b873a03de8 100644
--- a/src/soc/intel/alderlake/Kconfig
+++ b/src/soc/intel/alderlake/Kconfig
@@ -14,6 +14,7 @@ config CPU_SPECIFIC_OPTIONS
select IDT_IN_EVERY_STAGE
select INTEL_CAR_NEM #TODO - Enable INTEL_CAR_NEM_ENHANCED
select MICROCODE_BLOB_UNDISCLOSED
+ select PLATFORM_USES_FSP2_2
select SOC_INTEL_COMMON
select SOC_INTEL_COMMON_BLOCK
select SOC_INTEL_COMMON_BLOCK_CPU
@@ -26,6 +27,7 @@ config CPU_SPECIFIC_OPTIONS
select SUPPORT_CPU_UCODE_IN_CBFS
select TSC_MONOTONIC_TIMER
select UDELAY_TSC
+ select UDK_202005_BINDING
config DCACHE_RAM_BASE
default 0xfef00000
@@ -129,4 +131,12 @@ config CBFS_SIZE
config PRERAM_CBMEM_CONSOLE_SIZE
hex
default 0x1400
+config FSP_HEADER_PATH
+ string "Location of FSP headers"
+ default "src/vendorcode/intel/fsp/fsp2_0/alderlake/"
+
+config FSP_FD_PATH
+ string
+ depends on FSP_USE_REPO
+ default "3rdparty/fsp/AlderLakeFspBinPkg/Fsp.fd"
endif
diff --git a/src/vendorcode/intel/fsp/fsp2_0/alderlake/FirmwareVersionInfoHob.h b/src/vendorcode/intel/fsp/fsp2_0/alderlake/FirmwareVersionInfoHob.h
new file mode 100644
index 0000000000..a7e029c802
--- /dev/null
+++ b/src/vendorcode/intel/fsp/fsp2_0/alderlake/FirmwareVersionInfoHob.h
@@ -0,0 +1,68 @@
+/** @file
+ Header file for Firmware Version Information
+
+ @copyright
+ Copyright (c) 2015 - 2020, Intel Corporation. All rights reserved.<BR>
+
+ This program and the accompanying materials are licensed and made available under
+ the terms and conditions of the BSD License which accompanies this distribution.
+ The full text of the license may be found at
+ http://opensource.org/licenses/bsd-license.php
+
+ THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+ WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+
+**/
+
+#ifndef _FIRMWARE_VERSION_INFO_HOB_H_
+#define _FIRMWARE_VERSION_INFO_HOB_H_
+
+#include <Uefi/UefiMultiPhase.h>
+#include <Pi/PiBootMode.h>
+#include <Pi/PiHob.h>
+
+#pragma pack(1)
+///
+/// Firmware Version Structure
+///
+typedef struct {
+ UINT8 MajorVersion;
+ UINT8 MinorVersion;
+ UINT8 Revision;
+ UINT16 BuildNumber;
+} FIRMWARE_VERSION;
+
+///
+/// Firmware Version Information Structure
+///
+typedef struct {
+ UINT8 ComponentNameIndex; ///< Offset 0 Index of Component Name
+ UINT8 VersionStringIndex; ///< Offset 1 Index of Version String
+ FIRMWARE_VERSION Version; ///< Offset 2-6 Firmware version
+} FIRMWARE_VERSION_INFO;
+
+#ifndef __SMBIOS_STANDARD_H__
+///
+/// The Smbios structure header.
+///
+typedef struct {
+ UINT8 Type;
+ UINT8 Length;
+ UINT16 Handle;
+} SMBIOS_STRUCTURE;
+#endif
+
+///
+/// Firmware Version Information HOB Structure
+///
+typedef struct {
+ EFI_HOB_GUID_TYPE Header; ///< Offset 0-23 The header of FVI HOB
+ SMBIOS_STRUCTURE SmbiosData; ///< Offset 24-27 The SMBIOS header of FVI HOB
+ UINT8 Count; ///< Offset 28 Number of FVI elements included.
+///
+/// FIRMWARE_VERSION_INFO structures followed by the null terminated string buffer
+///
+} FIRMWARE_VERSION_INFO_HOB;
+#pragma pack()
+
+#endif // _FIRMWARE_VERSION_INFO_HOB_H_ \ No newline at end of file
diff --git a/src/vendorcode/intel/fsp/fsp2_0/alderlake/FspUpd.h b/src/vendorcode/intel/fsp/fsp2_0/alderlake/FspUpd.h
new file mode 100644
index 0000000000..b6ac3deaad
--- /dev/null
+++ b/src/vendorcode/intel/fsp/fsp2_0/alderlake/FspUpd.h
@@ -0,0 +1,48 @@
+/** @file
+
+Copyright (c) 2020, Intel Corporation. All rights reserved.<BR>
+
+Redistribution and use in source and binary forms, with or without modification,
+are permitted provided that the following conditions are met:
+
+* Redistributions of source code must retain the above copyright notice, this
+ list of conditions and the following disclaimer.
+* Redistributions in binary form must reproduce the above copyright notice, this
+ list of conditions and the following disclaimer in the documentation and/or
+ other materials provided with the distribution.
+* Neither the name of Intel Corporation nor the names of its contributors may
+ be used to endorse or promote products derived from this software without
+ specific prior written permission.
+
+ THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
+ LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
+ THE POSSIBILITY OF SUCH DAMAGE.
+
+ This file is automatically generated. Please do NOT modify !!!
+
+**/
+
+#ifndef __FSPUPD_H__
+#define __FSPUPD_H__
+
+#include <FspEas.h>
+
+#pragma pack(1)
+
+#define FSPT_UPD_SIGNATURE 0x545F4450554C4441 /* 'ADLUPD_T' */
+
+#define FSPM_UPD_SIGNATURE 0x4D5F4450554C4441 /* 'ADLUPD_M' */
+
+#define FSPS_UPD_SIGNATURE 0x535F4450554C4441 /* 'ADLUPD_S' */
+
+#pragma pack()
+
+#endif
diff --git a/src/vendorcode/intel/fsp/fsp2_0/alderlake/FspmUpd.h b/src/vendorcode/intel/fsp/fsp2_0/alderlake/FspmUpd.h
new file mode 100644
index 0000000000..a42f01474f
--- /dev/null
+++ b/src/vendorcode/intel/fsp/fsp2_0/alderlake/FspmUpd.h
@@ -0,0 +1,947 @@
+/** @file
+
+Copyright (c) 2020, Intel Corporation. All rights reserved.<BR>
+
+Redistribution and use in source and binary forms, with or without modification,
+are permitted provided that the following conditions are met:
+
+* Redistributions of source code must retain the above copyright notice, this
+ list of conditions and the following disclaimer.
+* Redistributions in binary form must reproduce the above copyright notice, this
+ list of conditions and the following disclaimer in the documentation and/or
+ other materials provided with the distribution.
+* Neither the name of Intel Corporation nor the names of its contributors may
+ be used to endorse or promote products derived from this software without
+ specific prior written permission.
+
+ THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
+ LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
+ THE POSSIBILITY OF SUCH DAMAGE.
+
+ This file is automatically generated. Please do NOT modify !!!
+
+**/
+
+#ifndef __FSPMUPD_H__
+#define __FSPMUPD_H__
+
+#include <FspUpd.h>
+
+#pragma pack(1)
+
+
+#include <MemInfoHob.h>
+
+///
+/// The ChipsetInit Info structure provides the information of ME ChipsetInit CRC and BIOS ChipsetInit CRC.
+///
+typedef struct {
+ UINT8 Revision; ///< Chipset Init Info Revision
+ UINT8 Rsvd[3]; ///< Reserved
+ UINT16 MeChipInitCrc; ///< 16 bit CRC value of MeChipInit Table
+ UINT16 BiosChipInitCrc; ///< 16 bit CRC value of PchChipInit Table
+} CHIPSET_INIT_INFO;
+
+
+/** Fsp M Configuration
+**/
+typedef struct {
+
+/** Offset 0x0040 - Platform Reserved Memory Size
+ The minimum platform memory size required to pass control into DXE
+**/
+ UINT64 PlatformMemorySize;
+
+/** Offset 0x0048 - SPD Data Length
+ Length of SPD Data
+ 0x100:256 Bytes, 0x200:512 Bytes, 0x400:1024 Bytes
+**/
+ UINT16 MemorySpdDataLen;
+
+/** Offset 0x004A - Reserved
+**/
+ UINT8 Reserved0[2];
+
+/** Offset 0x004C - MemorySpdPtr00
+**/
+ UINT32 MemorySpdPtr00;
+
+/** Offset 0x0050 - MemorySpdPtr01
+**/
+ UINT32 MemorySpdPtr01;
+
+/** Offset 0x0054 - MemorySpdPtr02
+**/
+ UINT32 MemorySpdPtr02;
+
+/** Offset 0x0058 - MemorySpdPtr03
+**/
+ UINT32 MemorySpdPtr03;
+
+/** Offset 0x005C - MemorySpdPtr04
+**/
+ UINT32 MemorySpdPtr04;
+
+/** Offset 0x0060 - MemorySpdPtr05
+**/
+ UINT32 MemorySpdPtr05;
+
+/** Offset 0x0064 - MemorySpdPtr06
+**/
+ UINT32 MemorySpdPtr06;
+
+/** Offset 0x0068 - MemorySpdPtr07
+**/
+ UINT32 MemorySpdPtr07;
+
+/** Offset 0x006C - MemorySpdPtr08
+**/
+ UINT32 MemorySpdPtr08;
+
+/** Offset 0x0070 - MemorySpdPtr09
+**/
+ UINT32 MemorySpdPtr09;
+
+/** Offset 0x0074 - MemorySpdPtr10
+**/
+ UINT32 MemorySpdPtr10;
+
+/** Offset 0x0078 - MemorySpdPtr11
+**/
+ UINT32 MemorySpdPtr11;
+
+/** Offset 0x007C - MemorySpdPtr12
+**/
+ UINT32 MemorySpdPtr12;
+
+/** Offset 0x0080 - MemorySpdPtr13
+**/
+ UINT32 MemorySpdPtr13;
+
+/** Offset 0x0084 - MemorySpdPtr14
+**/
+ UINT32 MemorySpdPtr14;
+
+/** Offset 0x0088 - MemorySpdPtr15
+**/
+ UINT32 MemorySpdPtr15;
+
+/** Offset 0x008C - RcompResistor settings
+ Indicates RcompResistor settings: Board-dependent
+**/
+ UINT16 RcompResistor;
+
+/** Offset 0x008E - RcompTarget settings
+ RcompTarget settings: board-dependent
+**/
+ UINT16 RcompTarget[5];
+
+/** Offset 0x0098 - DqsMapCpu2DramCh0
+**/
+ UINT8 DqsMapCpu2DramCh0[2];
+
+/** Offset 0x009A - DqsMapCpu2DramCh1
+**/
+ UINT8 DqsMapCpu2DramCh1[2];
+
+/** Offset 0x009C - DqsMapCpu2DramCh2
+**/
+ UINT8 DqsMapCpu2DramCh2[2];
+
+/** Offset 0x009E - DqsMapCpu2DramCh3
+**/
+ UINT8 DqsMapCpu2DramCh3[2];
+
+/** Offset 0x00A0 - DqsMapCpu2DramCh4
+**/
+ UINT8 DqsMapCpu2DramCh4[2];
+
+/** Offset 0x00A2 - DqsMapCpu2DramCh5
+**/
+ UINT8 DqsMapCpu2DramCh5[2];
+
+/** Offset 0x00A4 - DqsMapCpu2DramCh6
+**/
+ UINT8 DqsMapCpu2DramCh6[2];
+
+/** Offset 0x00A6 - DqsMapCpu2DramCh7
+**/
+ UINT8 DqsMapCpu2DramCh7[2];
+
+/** Offset 0x00A8 - DqMapCpu2DramCh0
+**/
+ UINT8 DqMapCpu2DramCh0[16];
+
+/** Offset 0x00B8 - DqMapCpu2DramCh1
+**/
+ UINT8 DqMapCpu2DramCh1[16];
+
+/** Offset 0x00C8 - DqMapCpu2DramCh2
+**/
+ UINT8 DqMapCpu2DramCh2[16];
+
+/** Offset 0x00D8 - DqMapCpu2DramCh3
+**/
+ UINT8 DqMapCpu2DramCh3[16];
+
+/** Offset 0x00E8 - DqMapCpu2DramCh4
+**/
+ UINT8 DqMapCpu2DramCh4[16];
+
+/** Offset 0x00F8 - DqMapCpu2DramCh5
+**/
+ UINT8 DqMapCpu2DramCh5[16];
+
+/** Offset 0x0108 - DqMapCpu2DramCh6
+**/
+ UINT8 DqMapCpu2DramCh6[16];
+
+/** Offset 0x0118 - DqMapCpu2DramCh7
+**/
+ UINT8 DqMapCpu2DramCh7[16];
+
+/** Offset 0x0128 - Dqs Pins Interleaved Setting
+ Indicates DqPinsInterleaved setting: board-dependent
+ $EN_DIS
+**/
+ UINT8 DqPinsInterleaved;
+
+/** Offset 0x0129 - Reserved
+**/
+ UINT8 Reserved1[7];
+
+/** Offset 0x0130 - Tseg Size
+ Size of SMRAM memory reserved. 0x400000 for Release build and 0x1000000 for Debug build
+ 0x0400000:4MB, 0x01000000:16MB
+**/
+ UINT32 TsegSize;
+
+/** Offset 0x0134 - Reserved
+**/
+ UINT8 Reserved2[3];
+
+/** Offset 0x0137 - Enable SMBus
+ Enable/disable SMBus controller.
+ $EN_DIS
+**/
+ UINT8 SmbusEnable;
+
+/** Offset 0x0138 - Spd Address Tabl
+ Specify SPD Address table for CH0D0/CH0D1/CH1D0&CH1D1. MemorySpdPtr will be used
+ if SPD Address is 00
+**/
+ UINT8 SpdAddressTable[16];
+
+/** Offset 0x0148 - Platform Debug Consent
+ To 'opt-in' for debug, please select 'Enabled' with the desired debug probe type.
+ Enabling this BIOS option may alter the default value of other debug-related BIOS
+ options.\Manual: Do not use Platform Debug Consent to override other debug-relevant
+ policies, but the user must set each debug option manually, aimed at advanced users.\n
+ Note: DCI OOB (aka BSSB) uses CCA probe;[DCI OOB+DbC] and [USB2 DbC] have the same setting.
+ 0:Disabled, 1:Enabled (DCI OOB+[DbC]), 2:Enabled (DCI OOB), 3:Enabled (USB3 DbC),
+ 4:Enabled (XDP/MIPI60), 5:Enabled (USB2 DbC), 6:Enable (2-wire DCI OOB), 7:Manual
+**/
+ UINT8 PlatformDebugConsent;
+
+/** Offset 0x0149 - Reserved
+**/
+ UINT8 Reserved3[14];
+
+/** Offset 0x0157 - State of X2APIC_OPT_OUT bit in the DMAR table
+ 0=Disable/Clear, 1=Enable/Set
+ $EN_DIS
+**/
+ UINT8 X2ApicOptOut;
+
+/** Offset 0x0158 - Reserved
+**/
+ UINT8 Reserved4[40];
+
+/** Offset 0x0180 - Disable VT-d
+ 0=Enable/FALSE(VT-d enabled), 1=Disable/TRUE (VT-d disabled)
+ $EN_DIS
+**/
+ UINT8 VtdDisable;
+
+/** Offset 0x0181 - Reserved
+**/
+ UINT8 Reserved5[4];
+
+/** Offset 0x0185 - Internal Graphics Pre-allocated Memory
+ Size of memory preallocated for internal graphics.
+ 0x00:0MB, 0x01:32MB, 0x02:64MB, 0x03:96MB, 0x04:128MB, 0x05:160MB, 0xF0:4MB, 0xF1:8MB,
+ 0xF2:12MB, 0xF3:16MB, 0xF4:20MB, 0xF5:24MB, 0xF6:28MB, 0xF7:32MB, 0xF8:36MB, 0xF9:40MB,
+ 0xFA:44MB, 0xFB:48MB, 0xFC:52MB, 0xFD:56MB, 0xFE:60MB
+**/
+ UINT8 IgdDvmt50PreAlloc;
+
+/** Offset 0x0186 - Internal Graphics
+ Enable/disable internal graphics.
+ $EN_DIS
+**/
+ UINT8 InternalGfx;
+
+/** Offset 0x0187 - Reserved
+**/
+ UINT8 Reserved6;
+
+/** Offset 0x0188 - Board Type
+ MrcBoardType, Options are 0=Mobile/Mobile Halo, 1=Desktop/DT Halo, 5=ULT/ULX/Mobile
+ Halo, 7=UP Server
+ 0:Mobile/Mobile Halo, 1:Desktop/DT Halo, 5:ULT/ULX/Mobile Halo, 7:UP Server
+**/
+ UINT8 UserBd;
+
+/** Offset 0x0189 - Reserved
+**/
+ UINT8 Reserved7[3];
+
+/** Offset 0x018C - SA GV
+ System Agent dynamic frequency support and when enabled memory will be training
+ at three different frequencies.
+ 0:Disabled, 1:FixedPoint0, 2:FixedPoint1, 3:FixedPoint2, 4:FixedPoint3, 5:Enabled
+**/
+ UINT8 SaGv;
+
+/** Offset 0x018D - Reserved
+**/
+ UINT8 Reserved8[2];
+
+/** Offset 0x018F - Rank Margin Tool
+ Enable/disable Rank Margin Tool.
+ $EN_DIS
+**/
+ UINT8 RMT;
+
+/** Offset 0x0190 - Controller 0 Channel 0 DIMM Control
+ Controller 1 Channel 0 DIMM Control Support - Enable or Disable Dimms on Channel A.
+ 0:Enable both DIMMs, 1:Disable DIMM0, 2:Disable DIMM1, 3:Disable both DIMMs
+**/
+ UINT8 DisableDimmMc0Ch0;
+
+/** Offset 0x0191 - Controller 0 Channel 1 DIMM Control
+ Controller 1 Channel 1 DIMM Control Support - Enable or Disable Dimms on Channel B.
+ 0:Enable both DIMMs, 1:Disable DIMM0, 2:Disable DIMM1, 3:Disable both DIMMs
+**/
+ UINT8 DisableDimmMc0Ch1;
+
+/** Offset 0x0192 - Controller 0 Channel 2 DIMM Control
+ Controller 0 Channel 2 DIMM Control Support - Enable or Disable Dimms on Channel A.
+ 0:Enable both DIMMs, 1:Disable DIMM0, 2:Disable DIMM1, 3:Disable both DIMMs
+**/
+ UINT8 DisableDimmMc0Ch2;
+
+/** Offset 0x0193 - Controller 0 Channel 3 DIMM Control
+ Controller 0 Channel 3 DIMM Control Support - Enable or Disable Dimms on Channel B.
+ 0:Enable both DIMMs, 1:Disable DIMM0, 2:Disable DIMM1, 3:Disable both DIMMs
+**/
+ UINT8 DisableDimmMc0Ch3;
+
+/** Offset 0x0194 - Controller 1 Channel 0 DIMM Control
+ Controller 1 Channel 0 DIMM Control Support - Enable or Disable Dimms on Channel A.
+ 0:Enable both DIMMs, 1:Disable DIMM0, 2:Disable DIMM1, 3:Disable both DIMMs
+**/
+ UINT8 DisableDimmMc1Ch0;
+
+/** Offset 0x0195 - Controller 1 Channel 1 DIMM Control
+ Controller 1 Channel 1 DIMM Control Support - Enable or Disable Dimms on Channel B.
+ 0:Enable both DIMMs, 1:Disable DIMM0, 2:Disable DIMM1, 3:Disable both DIMMs
+**/
+ UINT8 DisableDimmMc1Ch1;
+
+/** Offset 0x0196 - Controller 1 Channel 2 DIMM Control
+ Controller 1 Channel 2 DIMM Control Support - Enable or Disable Dimms on Channel A.
+ 0:Enable both DIMMs, 1:Disable DIMM0, 2:Disable DIMM1, 3:Disable both DIMMs
+**/
+ UINT8 DisableDimmMc1Ch2;
+
+/** Offset 0x0197 - Controller 1 Channel 3 DIMM Control
+ Controller 1 Channel 3 DIMM Control Support - Enable or Disable Dimms on Channel B.
+ 0:Enable both DIMMs, 1:Disable DIMM0, 2:Disable DIMM1, 3:Disable both DIMMs
+**/
+ UINT8 DisableDimmMc1Ch3;
+
+/** Offset 0x0198 - Reserved
+**/
+ UINT8 Reserved9[2];
+
+/** Offset 0x019A - Memory Reference Clock
+ 100MHz, 133MHz.
+ 0:133MHz, 1:100MHz
+**/
+ UINT8 RefClk;
+
+/** Offset 0x019B - Reserved
+**/
+ UINT8 Reserved10[22];
+
+/** Offset 0x01B1 - Enable Intel HD Audio (Azalia)
+ 0: Disable, 1: Enable (Default) Azalia controller
+ $EN_DIS
+**/
+ UINT8 PchHdaEnable;
+
+/** Offset 0x01B2 - Enable PCH ISH Controller
+ 0: Disable, 1: Enable (Default) ISH Controller
+ $EN_DIS
+**/
+ UINT8 PchIshEnable;
+
+/** Offset 0x01B3 - Reserved
+**/
+ UINT8 Reserved11[107];
+
+/** Offset 0x021E - IMGU CLKOUT Configuration
+ The configuration of IMGU CLKOUT, 0: Disable;<b>1: Enable</b>.
+ $EN_DIS
+**/
+ UINT8 ImguClkOutEn[6];
+
+/** Offset 0x0224 - Enable PCIE RP Mask
+ Enable/disable PCIE Root Ports. 0: disable, 1: enable. One bit for each port, bit0
+ for port1, bit1 for port2, and so on.
+**/
+ UINT32 CpuPcieRpEnableMask;
+
+/** Offset 0x0228 - Reserved
+**/
+ UINT8 Reserved12;
+
+/** Offset 0x0229 - RpClockReqMsgEnable
+**/
+ UINT8 RpClockReqMsgEnable[3];
+
+/** Offset 0x022C - RpPcieThresholdBytes
+**/
+ UINT8 RpPcieThresholdBytes[4];
+
+/** Offset 0x0230 - Reserved
+**/
+ UINT8 Reserved13[2];
+
+/** Offset 0x0232 - Program GPIOs for LFP on DDI port-A device
+ 0=Disabled,1(Default)=eDP, 2=MIPI DSI
+ 0:Disabled, 1:eDP, 2:MIPI DSI
+**/
+ UINT8 DdiPortAConfig;
+
+/** Offset 0x0233 - Program GPIOs for LFP on DDI port-B device
+ 0(Default)=Disabled,1=eDP, 2=MIPI DSI
+ 0:Disabled, 1:eDP, 2:MIPI DSI
+**/
+ UINT8 DdiPortBConfig;
+
+/** Offset 0x0234 - Enable or disable HPD of DDI port A
+ 0(Default)=Disable, 1=Enable
+ $EN_DIS
+**/
+ UINT8 DdiPortAHpd;
+
+/** Offset 0x0235 - Enable or disable HPD of DDI port B
+ 0=Disable, 1(Default)=Enable
+ $EN_DIS
+**/
+ UINT8 DdiPortBHpd;
+
+/** Offset 0x0236 - Enable or disable HPD of DDI port C
+ 0(Default)=Disable, 1=Enable
+ $EN_DIS
+**/
+ UINT8 DdiPortCHpd;
+
+/** Offset 0x0237 - Enable or disable HPD of DDI port 1
+ 0=Disable, 1(Default)=Enable
+ $EN_DIS
+**/
+ UINT8 DdiPort1Hpd;
+
+/** Offset 0x0238 - Enable or disable HPD of DDI port 2
+ 0(Default)=Disable, 1=Enable
+ $EN_DIS
+**/
+ UINT8 DdiPort2Hpd;
+
+/** Offset 0x0239 - Enable or disable HPD of DDI port 3
+ 0(Default)=Disable, 1=Enable
+ $EN_DIS
+**/
+ UINT8 DdiPort3Hpd;
+
+/** Offset 0x023A - Enable or disable HPD of DDI port 4
+ 0(Default)=Disable, 1=Enable
+ $EN_DIS
+**/
+ UINT8 DdiPort4Hpd;
+
+/** Offset 0x023B - Enable or disable DDC of DDI port A
+ 0(Default)=Disable, 1=Enable
+ $EN_DIS
+**/
+ UINT8 DdiPortADdc;
+
+/** Offset 0x023C - Enable or disable DDC of DDI port B
+ 0=Disable, 1(Default)=Enable
+ $EN_DIS
+**/
+ UINT8 DdiPortBDdc;
+
+/** Offset 0x023D - Enable or disable DDC of DDI port C
+ 0(Default)=Disable, 1=Enable
+ $EN_DIS
+**/
+ UINT8 DdiPortCDdc;
+
+/** Offset 0x023E - Enable DDC setting of DDI Port 1
+ 0(Default)=Disable, 1=Enable
+ $EN_DIS
+**/
+ UINT8 DdiPort1Ddc;
+
+/** Offset 0x023F - Enable DDC setting of DDI Port 2
+ 0(Default)=Disable, 1=Enable
+ $EN_DIS
+**/
+ UINT8 DdiPort2Ddc;
+
+/** Offset 0x0240 - Enable DDC setting of DDI Port 3
+ 0(Default)=Disable, 1=Enable
+ $EN_DIS
+**/
+ UINT8 DdiPort3Ddc;
+
+/** Offset 0x0241 - Enable DDC setting of DDI Port 4
+ 0(Default)=Disable, 1=Enable
+ $EN_DIS
+**/
+ UINT8 DdiPort4Ddc;
+
+/** Offset 0x0242 - Reserved
+**/
+ UINT8 Reserved14[142];
+
+/** Offset 0x02D0 - DMI Gen3 Root port preset values per lane
+ Used for programming DMI Gen3 preset values per lane. Range: 0-9, 8 is default for each lane
+**/
+ UINT8 DmiGen3RootPortPreset[8];
+
+/** Offset 0x02D8 - Reserved
+**/
+ UINT8 Reserved15[150];
+
+/** Offset 0x036E - C6DRAM power gating feature
+ This policy indicates whether or not BIOS should allocate PRMRR memory for C6DRAM
+ power gating feature.- 0: Don't allocate any PRMRR memory for C6DRAM power gating
+ feature.- <b>1: Allocate PRMRR memory for C6DRAM power gating feature</b>.
+ $EN_DIS
+**/
+ UINT8 EnableC6Dram;
+
+/** Offset 0x036F - Reserved
+**/
+ UINT8 Reserved16[5];
+
+/** Offset 0x0374 - Hyper Threading Enable/Disable
+ Enable or Disable Hyper Threading; 0: Disable; <b>1: Enable</b>
+ $EN_DIS
+**/
+ UINT8 HyperThreading;
+
+/** Offset 0x0375 - Reserved
+**/
+ UINT8 Reserved17;
+
+/** Offset 0x0376 - CPU ratio value
+ CPU ratio value. Valid Range 0 to 63
+**/
+ UINT8 CpuRatio;
+
+/** Offset 0x0377 - Reserved
+**/
+ UINT8 Reserved18[2];
+
+/** Offset 0x0379 - Processor Early Power On Configuration FCLK setting
+ <b>0: 800 MHz (ULT/ULX)</b>. <b>1: 1 GHz (DT/Halo)</b>. Not supported on ULT/ULX.-
+ 2: 400 MHz. - 3: Reserved
+ 0:800 MHz, 1: 1 GHz, 2: 400 MHz, 3: Reserved
+**/
+ UINT8 FClkFrequency;
+
+/** Offset 0x037A - Reserved
+**/
+ UINT8 Reserved19;
+
+/** Offset 0x037B - Enable or Disable VMX
+ Enable or Disable VMX; 0: Disable; <b>1: Enable</b>.
+ $EN_DIS
+**/
+ UINT8 VmxEnable;
+
+/** Offset 0x037C - Reserved
+**/
+ UINT8 Reserved20[34];
+
+/** Offset 0x039E - BiosGuard
+ Enable/Disable. 0: Disable, Enable/Disable BIOS Guard feature, 1: enable
+ $EN_DIS
+**/
+ UINT8 BiosGuard;
+
+/** Offset 0x039F
+**/
+ UINT8 BiosGuardToolsInterface;
+
+/** Offset 0x03A0 - Reserved
+**/
+ UINT8 Reserved21[4];
+
+/** Offset 0x03A4 - PrmrrSize
+ Enable/Disable. 0: Disable, define default value of PrmrrSize , 1: enable
+**/
+ UINT32 PrmrrSize;
+
+/** Offset 0x03A8 - SinitMemorySize
+ Enable/Disable. 0: Disable, define default value of SinitMemorySize , 1: enable
+**/
+ UINT32 SinitMemorySize;
+
+/** Offset 0x03AC - Reserved
+**/
+ UINT8 Reserved22[12];
+
+/** Offset 0x03B8 - TxtHeapMemorySize
+ Enable/Disable. 0: Disable, define default value of TxtHeapMemorySize , 1: enable
+**/
+ UINT32 TxtHeapMemorySize;
+
+/** Offset 0x03BC - TxtDprMemorySize
+ Enable/Disable. 0: Disable, define default value of TxtDprMemorySize , 1: enable
+**/
+ UINT32 TxtDprMemorySize;
+
+/** Offset 0x03C0 - Reserved
+**/
+ UINT8 Reserved23[614];
+
+/** Offset 0x0626 - Number of RsvdSmbusAddressTable.
+ The number of elements in the RsvdSmbusAddressTable.
+**/
+ UINT8 PchNumRsvdSmbusAddresses;
+
+/** Offset 0x0627 - Reserved
+**/
+ UINT8 Reserved24[4];
+
+/** Offset 0x062B - Usage type for ClkSrc
+ 0-23: PCH rootport, 0x40-0x43: PEG port, 0x70:LAN, 0x80: unspecified but in use
+ (free running), 0xFF: not used
+**/
+ UINT8 PcieClkSrcUsage[18];
+
+/** Offset 0x063D - Reserved
+**/
+ UINT8 Reserved25[14];
+
+/** Offset 0x064B - ClkReq-to-ClkSrc mapping
+ Number of ClkReq signal assigned to ClkSrc
+**/
+ UINT8 PcieClkSrcClkReq[18];
+
+/** Offset 0x065D - Reserved
+**/
+ UINT8 Reserved26[19];
+
+/** Offset 0x0670 - Enable PCIE RP Mask
+ Enable/disable PCIE Root Ports. 0: disable, 1: enable. One bit for each port, bit0
+ for port1, bit1 for port2, and so on.
+**/
+ UINT32 PcieRpEnableMask;
+
+/** Offset 0x0674 - Reserved
+**/
+ UINT8 Reserved27[2];
+
+/** Offset 0x0676 - Enable HD Audio Link
+ Enable/disable HD Audio Link. Muxed with SSP0/SSP1/SNDW1.
+ $EN_DIS
+**/
+ UINT8 PchHdaAudioLinkHdaEnable;
+
+/** Offset 0x0677 - Reserved
+**/
+ UINT8 Reserved28[3];
+
+/** Offset 0x067A - Enable HD Audio DMIC_N Link
+ Enable/disable HD Audio DMIC1 link. Muxed with SNDW3.
+**/
+ UINT8 PchHdaAudioLinkDmicEnable[2];
+
+/** Offset 0x067C - DMIC<N> ClkA Pin Muxing (N - DMIC number)
+ Determines DMIC<N> ClkA Pin muxing. See GPIO_*_MUXING_DMIC<N>_CLKA_*
+**/
+ UINT32 PchHdaAudioLinkDmicClkAPinMux[2];
+
+/** Offset 0x0684 - DMIC<N> ClkB Pin Muxing
+ Determines DMIC<N> ClkA Pin muxing. See GPIO_*_MUXING_DMIC<N>_CLKB_*
+**/
+ UINT32 PchHdaAudioLinkDmicClkBPinMux[2];
+
+/** Offset 0x068C - Enable HD Audio DSP
+ Enable/disable HD Audio DSP feature.
+ $EN_DIS
+**/
+ UINT8 PchHdaDspEnable;
+
+/** Offset 0x068D - Reserved
+**/
+ UINT8 Reserved29[3];
+
+/** Offset 0x0690 - DMIC<N> Data Pin Muxing
+ Determines DMIC<N> Data Pin muxing. See GPIO_*_MUXING_DMIC<N>_DATA_*
+**/
+ UINT32 PchHdaAudioLinkDmicDataPinMux[2];
+
+/** Offset 0x0698 - Enable HD Audio SSP0 Link
+ Enable/disable HD Audio SSP_N/I2S link. Muxed with HDA. N-number 0-5
+**/
+ UINT8 PchHdaAudioLinkSspEnable[6];
+
+/** Offset 0x069E - Enable HD Audio SoundWire#N Link
+ Enable/disable HD Audio SNDW#N link. Muxed with HDA.
+**/
+ UINT8 PchHdaAudioLinkSndwEnable[4];
+
+/** Offset 0x06A2 - iDisp-Link Frequency
+ iDisp-Link Freq (PCH_HDAUDIO_LINK_FREQUENCY enum): 4: 96MHz, 3: 48MHz.
+ 4: 96MHz, 3: 48MHz
+**/
+ UINT8 PchHdaIDispLinkFrequency;
+
+/** Offset 0x06A3 - iDisp-Link T-mode
+ iDisp-Link T-Mode (PCH_HDAUDIO_IDISP_TMODE enum): 0: 2T, 2: 4T, 3: 8T, 4: 16T
+ 0: 2T, 2: 4T, 3: 8T, 4: 16T
+**/
+ UINT8 PchHdaIDispLinkTmode;
+
+/** Offset 0x06A4 - iDisplay Audio Codec disconnection
+ 0: Not disconnected, enumerable, 1: Disconnected SDI, not enumerable.
+ $EN_DIS
+**/
+ UINT8 PchHdaIDispCodecDisconnect;
+
+/** Offset 0x06A5 - Debug Interfaces
+ Debug Interfaces. BIT0-RAM, BIT1-UART, BIT3-USB3, BIT4-Serial IO, BIT5-TraceHub,
+ BIT2 - Not used.
+**/
+ UINT8 PcdDebugInterfaceFlags;
+
+/** Offset 0x06A6 - Serial Io Uart Debug Controller Number
+ Select SerialIo Uart Controller for debug. Note: If UART0 is selected as CNVi BT
+ Core interface, it cannot be used for debug purpose.
+ 0:SerialIoUart0, 1:SerialIoUart1, 2:SerialIoUart2
+**/
+ UINT8 SerialIoUartDebugControllerNumber;
+
+/** Offset 0x06A7 - Reserved
+**/
+ UINT8 Reserved30[13];
+
+/** Offset 0x06B4 - ISA Serial Base selection
+ Select ISA Serial Base address. Default is 0x3F8.
+ 0:0x3F8, 1:0x2F8
+**/
+ UINT8 PcdIsaSerialUartBase;
+
+/** Offset 0x06B5 - Reserved
+**/
+ UINT8 Reserved31[4];
+
+/** Offset 0x06B9 - MRC Safe Config
+ Enables/Disable MRC Safe Config
+ $EN_DIS
+**/
+ UINT8 MrcSafeConfig;
+
+/** Offset 0x06BA - TCSS Thunderbolt PCIE Root Port 0 Enable
+ Set TCSS Thunderbolt PCIE Root Port 0. 0:Disabled 1:Enabled
+ $EN_DIS
+**/
+ UINT8 TcssItbtPcie0En;
+
+/** Offset 0x06BB - TCSS Thunderbolt PCIE Root Port 1 Enable
+ Set TCSS Thunderbolt PCIE Root Port 1. 0:Disabled 1:Enabled
+ $EN_DIS
+**/
+ UINT8 TcssItbtPcie1En;
+
+/** Offset 0x06BC - TCSS Thunderbolt PCIE Root Port 2 Enable
+ Set TCSS Thunderbolt PCIE Root Port 2. 0:Disabled 1:Enabled
+ $EN_DIS
+**/
+ UINT8 TcssItbtPcie2En;
+
+/** Offset 0x06BD - TCSS Thunderbolt PCIE Root Port 3 Enable
+ Set TCSS Thunderbolt PCIE Root Port 3. 0:Disabled 1:Enabled
+ $EN_DIS
+**/
+ UINT8 TcssItbtPcie3En;
+
+/** Offset 0x06BE - TCSS USB HOST (xHCI) Enable
+ Set TCSS XHCI. 0:Disabled 1:Enabled - Must be enabled if xDCI is enabled below
+ $EN_DIS
+**/
+ UINT8 TcssXhciEn;
+
+/** Offset 0x06BF - TCSS USB DEVICE (xDCI) Enable
+ Set TCSS XDCI. 0:Disabled 1:Enabled - xHCI must be enabled if xDCI is enabled
+ $EN_DIS
+**/
+ UINT8 TcssXdciEn;
+
+/** Offset 0x06C0 - TCSS DMA0 Enable
+ Set TCSS DMA0. 0:Disabled 1:Enabled
+ $EN_DIS
+**/
+ UINT8 TcssDma0En;
+
+/** Offset 0x06C1 - TCSS DMA1 Enable
+ Set TCSS DMA1. 0:Disabled 1:Enabled
+ $EN_DIS
+**/
+ UINT8 TcssDma1En;
+
+/** Offset 0x06C2 - Reserved
+**/
+ UINT8 Reserved32[2];
+
+/** Offset 0x06C4 - Early Command Training
+ Enables/Disable Early Command Training
+ $EN_DIS
+**/
+ UINT8 ECT;
+
+/** Offset 0x06C5 - Reserved
+**/
+ UINT8 Reserved33[65];
+
+/** Offset 0x0706 - Ch Hash Mask
+ Set the BIT(s) to be included in the XOR function. NOTE BIT mask corresponds to
+ BITS [19:6] Default is 0x30CC
+**/
+ UINT16 ChHashMask;
+
+/** Offset 0x0708 - Reserved
+**/
+ UINT8 Reserved34[64];
+
+/** Offset 0x0748 - PcdSerialDebugLevel
+ Serial Debug Message Level. 0:Disable, 1:Error Only, 2:Error & Warnings, 3:Load,
+ Error, Warnings & Info, 4:Load, Error, Warnings, Info & Event, 5:Load, Error, Warnings,
+ Info & Verbose.
+ 0:Disable, 1:Error Only, 2:Error and Warnings, 3:Load Error Warnings and Info, 4:Load
+ Error Warnings and Info & Event, 5:Load Error Warnings Info and Verbose
+**/
+ UINT8 PcdSerialDebugLevel;
+
+/** Offset 0x0749 - Reserved
+**/
+ UINT8 Reserved35[2];
+
+/** Offset 0x074B - Safe Mode Support
+ This option configures the varous items in the IO and MC to be more conservative.(def=Disable)
+ $EN_DIS
+**/
+ UINT8 SafeMode;
+
+/** Offset 0x074C - Reserved
+**/
+ UINT8 Reserved36[2];
+
+/** Offset 0x074E - TCSS USB Port Enable
+ Bitmap for per port enabling
+**/
+ UINT8 UsbTcPortEnPreMem;
+
+/** Offset 0x074F - Reserved
+**/
+ UINT8 Reserved37[50];
+
+/** Offset 0x0781 - Skip external display device scanning
+ Enable: Do not scan for external display device, Disable (Default): Scan external
+ display devices
+ $EN_DIS
+**/
+ UINT8 SkipExtGfxScan;
+
+/** Offset 0x0782 - Reserved
+**/
+ UINT8 Reserved38;
+
+/** Offset 0x0783 - Lock PCU Thermal Management registers
+ Lock PCU Thermal Management registers. Enable(Default)=1, Disable=0
+ $EN_DIS
+**/
+ UINT8 LockPTMregs;
+
+/** Offset 0x0784 - Reserved
+**/
+ UINT8 Reserved39[129];
+
+/** Offset 0x0805 - Skip CPU replacement check
+ Test, 0: disable, 1: enable, Setting this option to skip CPU replacement check
+ $EN_DIS
+**/
+ UINT8 SkipCpuReplacementCheck;
+
+/** Offset 0x0806 - Reserved
+**/
+ UINT8 Reserved40[292];
+
+/** Offset 0x092A - Serial Io Uart Debug Mode
+ Select SerialIo Uart Controller mode
+ 0:SerialIoUartDisabled, 1:SerialIoUartPci, 2:SerialIoUartHidden, 3:SerialIoUartCom,
+ 4:SerialIoUartSkipInit
+**/
+ UINT8 SerialIoUartDebugMode;
+
+/** Offset 0x092B - Reserved
+**/
+ UINT8 Reserved41[517];
+} FSP_M_CONFIG;
+
+/** Fsp M UPD Configuration
+**/
+typedef struct {
+
+/** Offset 0x0000
+**/
+ FSP_UPD_HEADER FspUpdHeader;
+
+/** Offset 0x0020
+**/
+ FSPM_ARCH_UPD FspmArchUpd;
+
+/** Offset 0x0040
+**/
+ FSP_M_CONFIG FspmConfig;
+
+
+/** Offset 0x0B30
+**/
+ UINT8 UnusedUpdSpace32[6];
+
+/** Offset 0x0B36
+**/
+ UINT16 UpdTerminator;
+} FSPM_UPD;
+
+#pragma pack()
+
+#endif
diff --git a/src/vendorcode/intel/fsp/fsp2_0/alderlake/FspsUpd.h b/src/vendorcode/intel/fsp/fsp2_0/alderlake/FspsUpd.h
new file mode 100644
index 0000000000..39c360ddd6
--- /dev/null
+++ b/src/vendorcode/intel/fsp/fsp2_0/alderlake/FspsUpd.h
@@ -0,0 +1,902 @@
+/** @file
+
+Copyright (c) 2020, Intel Corporation. All rights reserved.<BR>
+
+Redistribution and use in source and binary forms, with or without modification,
+are permitted provided that the following conditions are met:
+
+* Redistributions of source code must retain the above copyright notice, this
+ list of conditions and the following disclaimer.
+* Redistributions in binary form must reproduce the above copyright notice, this
+ list of conditions and the following disclaimer in the documentation and/or
+ other materials provided with the distribution.
+* Neither the name of Intel Corporation nor the names of its contributors may
+ be used to endorse or promote products derived from this software without
+ specific prior written permission.
+
+ THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
+ LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
+ THE POSSIBILITY OF SUCH DAMAGE.
+
+ This file is automatically generated. Please do NOT modify !!!
+
+**/
+
+#ifndef __FSPSUPD_H__
+#define __FSPSUPD_H__
+
+#include <FspUpd.h>
+
+#pragma pack(1)
+
+
+///
+/// Azalia Header structure
+///
+typedef struct {
+ UINT16 VendorId; ///< Codec Vendor ID
+ UINT16 DeviceId; ///< Codec Device ID
+ UINT8 RevisionId; ///< Revision ID of the codec. 0xFF matches any revision.
+ UINT8 SdiNum; ///< SDI number, 0xFF matches any SDI.
+ UINT16 DataDwords; ///< Number of data DWORDs pointed by the codec data buffer.
+ UINT32 Reserved; ///< Reserved for future use. Must be set to 0.
+} AZALIA_HEADER;
+
+///
+/// Audio Azalia Verb Table structure
+///
+typedef struct {
+ AZALIA_HEADER Header; ///< AZALIA PCH header
+ UINT32 *Data; ///< Pointer to the data buffer. Its length is specified in the header
+} AUDIO_AZALIA_VERB_TABLE;
+
+///
+/// Refer to the definition of PCH_INT_PIN
+///
+typedef enum {
+ SiPchNoInt, ///< No Interrupt Pin
+ SiPchIntA,
+ SiPchIntB,
+ SiPchIntC,
+ SiPchIntD
+} SI_PCH_INT_PIN;
+///
+/// The PCH_DEVICE_INTERRUPT_CONFIG block describes interrupt pin, IRQ and interrupt mode for PCH device.
+///
+typedef struct {
+ UINT8 Device; ///< Device number
+ UINT8 Function; ///< Device function
+ UINT8 IntX; ///< Interrupt pin: INTA-INTD (see SI_PCH_INT_PIN)
+ UINT8 Irq; ///< IRQ to be set for device.
+} SI_PCH_DEVICE_INTERRUPT_CONFIG;
+
+#define SI_PCH_MAX_DEVICE_INTERRUPT_CONFIG 64 ///< Number of all PCH devices
+
+
+/** FSPS_ARCH_UPD
+**/
+typedef struct {
+
+/** Offset 0x0020 - Reserved
+**/
+ UINT8 Revision;
+
+/** Offset 0x0021 - Reserved
+**/
+ UINT8 Reserved[3];
+
+/** Offset 0x0024 - Reserved
+**/
+ UINT32 Length;
+
+/** Offset 0x0028 - Reserved
+**/
+ UINT32 FspEventHandler;
+
+/** Offset 0x002C - Reserved
+**/
+ UINT8 EnableMultiPhaseSiliconInit;
+
+/** Offset 0x002D - Reserved
+**/
+ UINT8 Reserved1[19];
+} FSPS_ARCH_UPD;
+
+/** Fsp S Configuration
+**/
+typedef struct {
+
+/** Offset 0x0040 - Reserved
+**/
+ UINT8 Reserved0[16];
+
+/** Offset 0x0050 - Graphics Configuration Ptr
+ Points to VBT
+**/
+ UINT32 GraphicsConfigPtr;
+
+/** Offset 0x0054 - Enable Device 4
+ Enable/disable Device 4
+ $EN_DIS
+**/
+ UINT8 Device4Enable;
+
+/** Offset 0x0055 - Reserved
+**/
+ UINT8 Reserved1[12];
+
+/** Offset 0x0061 - Enable SATA SALP Support
+ Enable/disable SATA Aggressive Link Power Management.
+ $EN_DIS
+**/
+ UINT8 SataSalpSupport;
+
+/** Offset 0x0062 - Enable SATA ports
+ Enable/disable SATA ports. One byte for each port, byte0 for port0, byte1 for port1,
+ and so on.
+**/
+ UINT8 SataPortsEnable[8];
+
+/** Offset 0x006A - Enable SATA DEVSLP Feature
+ Enable/disable SATA DEVSLP per port. 0 is disable, 1 is enable. One byte for each
+ port, byte0 for port0, byte1 for port1, and so on.
+**/
+ UINT8 SataPortsDevSlp[8];
+
+/** Offset 0x0072 - Enable USB2 ports
+ Enable/disable per USB2 ports. One byte for each port, byte0 for port0, byte1 for
+ port1, and so on.
+**/
+ UINT8 PortUsb20Enable[16];
+
+/** Offset 0x0082 - Enable USB3 ports
+ Enable/disable per USB3 ports. One byte for each port, byte0 for port0, byte1 for
+ port1, and so on.
+**/
+ UINT8 PortUsb30Enable[10];
+
+/** Offset 0x008C - Enable xDCI controller
+ Enable/disable to xDCI controller.
+ $EN_DIS
+**/
+ UINT8 XdciEnable;
+
+/** Offset 0x008D - Reserved
+**/
+ UINT8 Reserved2[28];
+
+/** Offset 0x00A9 - Enable SATA
+ Enable/disable SATA controller.
+ $EN_DIS
+**/
+ UINT8 SataEnable;
+
+/** Offset 0x00AA - SATA Mode
+ Select SATA controller working mode.
+ 0:AHCI, 1:RAID
+**/
+ UINT8 SataMode;
+
+/** Offset 0x00AB - SPIn Device Mode
+ Selects SPI operation mode. N represents controller index: SPI0, SPI1, ... Available
+ modes: 0:SerialIoSpiDisabled, 1:SerialIoSpiPci, 2:SerialIoSpiHidden
+**/
+ UINT8 SerialIoSpiMode[7];
+
+/** Offset 0x00B2 - Reserved
+**/
+ UINT8 Reserved3[35];
+
+/** Offset 0x00D5 - SPIn Default Chip Select Mode HW/SW
+ Sets Default CS Mode Hardware or Software. N represents controller index: SPI0,
+ SPI1, ... Available options: 0:HW, 1:SW
+**/
+ UINT8 SerialIoSpiCsMode[7];
+
+/** Offset 0x00DC - SPIn Default Chip Select State Low/High
+ Sets Default CS State Low or High. N represents controller index: SPI0, SPI1, ...
+ Available options: 0:Low, 1:High
+**/
+ UINT8 SerialIoSpiCsState[7];
+
+/** Offset 0x00E3 - UARTn Device Mode
+ Selects Uart operation mode. N represents controller index: Uart0, Uart1, ... Available
+ modes: 0:SerialIoUartDisabled, 1:SerialIoUartPci, 2:SerialIoUartHidden, 3:SerialIoUartCom,
+ 4:SerialIoUartSkipInit
+**/
+ UINT8 SerialIoUartMode[7];
+
+/** Offset 0x00EA - Reserved
+**/
+ UINT8 Reserved4[65];
+
+/** Offset 0x012B - Enables UART hardware flow control, CTS and RTS lines
+ Enables UART hardware flow control, CTS and RTS lines.
+**/
+ UINT8 SerialIoUartAutoFlow[7];
+
+/** Offset 0x0132 - Reserved
+**/
+ UINT8 Reserved5[2];
+
+/** Offset 0x0134 - SerialIoUartRtsPinMuxPolicy
+ Select SerialIo Uart Rts pin muxing. Refer to GPIO_*_MUXING_SERIALIO_UARTx_RTS*
+ for possible values.
+**/
+ UINT32 SerialIoUartRtsPinMuxPolicy[7];
+
+/** Offset 0x0150 - SerialIoUartCtsPinMuxPolicy
+ Select SerialIo Uart Cts pin muxing. Refer to GPIO_*_MUXING_SERIALIO_UARTx_CTS*
+ for possible values.
+**/
+ UINT32 SerialIoUartCtsPinMuxPolicy[7];
+
+/** Offset 0x016C - SerialIoUartRxPinMuxPolicy
+ Select SerialIo Uart Rx pin muxing. Refer to GPIO_*_MUXING_SERIALIO_UARTx_RX* for
+ possible values.
+**/
+ UINT32 SerialIoUartRxPinMuxPolicy[7];
+
+/** Offset 0x0188 - SerialIoUartTxPinMuxPolicy
+ Select SerialIo Uart Tx pin muxing. Refer to GPIO_*_MUXING_SERIALIO_UARTx_TX* for
+ possible values.
+**/
+ UINT32 SerialIoUartTxPinMuxPolicy[7];
+
+/** Offset 0x01A4 - UART Number For Debug Purpose
+ UART number for debug purpose. 0:UART0, 1:UART1, 2:UART2, 3:UART3, 4:UART4, 5:UART5,
+ 6:UART6. Note: If UART0 is selected as CNVi BT Core interface, it cannot be used
+ for debug purpose.
+ 0:UART0, 1:UART1, 2:UART2, 3:UART3, 4:UART4, 5:UART5, 6:UART6
+**/
+ UINT8 SerialIoDebugUartNumber;
+
+/** Offset 0x01A5 - Reserved
+**/
+ UINT8 Reserved6[7];
+
+/** Offset 0x01AC - I2Cn Device Mode
+ Selects I2c operation mode. N represents controller index: I2c0, I2c1, ... Available
+ modes: 0:SerialIoI2cDisabled, 1:SerialIoI2cPci, 2:SerialIoI2cHidden
+**/
+ UINT8 SerialIoI2cMode[8];
+
+/** Offset 0x01B4 - Serial IO I2C SDA Pin Muxing
+ Select SerialIo I2c Sda pin muxing. Refer to GPIO_*_MUXING_SERIALIO_I2Cx_SDA* for
+ possible values.
+**/
+ UINT32 PchSerialIoI2cSdaPinMux[8];
+
+/** Offset 0x01D4 - Serial IO I2C SCL Pin Muxing
+ Select SerialIo I2c Scl pin muxing. Refer to GPIO_*_MUXING_SERIALIO_I2Cx_SCL* for
+ possible values.
+**/
+ UINT32 PchSerialIoI2cSclPinMux[8];
+
+/** Offset 0x01F4 - Reserved
+**/
+ UINT8 Reserved7[192];
+
+/** Offset 0x02B4 - USB Per Port HS Preemphasis Bias
+ USB Per Port HS Preemphasis Bias. 000b-0mV, 001b-11.25mV, 010b-16.9mV, 011b-28.15mV,
+ 100b-28.15mV, 101b-39.35mV, 110b-45mV, 111b-56.3mV. One byte for each port.
+**/
+ UINT8 Usb2PhyPetxiset[16];
+
+/** Offset 0x02C4 - USB Per Port HS Transmitter Bias
+ USB Per Port HS Transmitter Bias. 000b-0mV, 001b-11.25mV, 010b-16.9mV, 011b-28.15mV,
+ 100b-28.15mV, 101b-39.35mV, 110b-45mV, 111b-56.3mV, One byte for each port.
+**/
+ UINT8 Usb2PhyTxiset[16];
+
+/** Offset 0x02D4 - USB Per Port HS Transmitter Emphasis
+ USB Per Port HS Transmitter Emphasis. 00b - Emphasis OFF, 01b - De-emphasis ON,
+ 10b - Pre-emphasis ON, 11b - Pre-emphasis & De-emphasis ON. One byte for each port.
+**/
+ UINT8 Usb2PhyPredeemp[16];
+
+/** Offset 0x02E4 - USB Per Port Half Bit Pre-emphasis
+ USB Per Port Half Bit Pre-emphasis. 1b - half-bit pre-emphasis, 0b - full-bit pre-emphasis.
+ One byte for each port.
+**/
+ UINT8 Usb2PhyPehalfbit[16];
+
+/** Offset 0x02F4 - Enable the write to USB 3.0 TX Output -3.5dB De-Emphasis Adjustment
+ Enable the write to USB 3.0 TX Output -3.5dB De-Emphasis Adjustment. Each value
+ in arrary can be between 0-1. One byte for each port.
+**/
+ UINT8 Usb3HsioTxDeEmphEnable[10];
+
+/** Offset 0x02FE - USB 3.0 TX Output -3.5dB De-Emphasis Adjustment Setting
+ USB 3.0 TX Output -3.5dB De-Emphasis Adjustment Setting, HSIO_TX_DWORD5[21:16],
+ <b>Default = 29h</b> (approximately -3.5dB De-Emphasis). One byte for each port.
+**/
+ UINT8 Usb3HsioTxDeEmph[10];
+
+/** Offset 0x0308 - Enable the write to USB 3.0 TX Output Downscale Amplitude Adjustment
+ Enable the write to USB 3.0 TX Output Downscale Amplitude Adjustment, Each value
+ in arrary can be between 0-1. One byte for each port.
+**/
+ UINT8 Usb3HsioTxDownscaleAmpEnable[10];
+
+/** Offset 0x0312 - USB 3.0 TX Output Downscale Amplitude Adjustment
+ USB 3.0 TX Output Downscale Amplitude Adjustment, HSIO_TX_DWORD8[21:16], <b>Default
+ = 00h</b>. One byte for each port.
+**/
+ UINT8 Usb3HsioTxDownscaleAmp[10];
+
+/** Offset 0x031C - Reserved
+**/
+ UINT8 Reserved8[80];
+
+/** Offset 0x036C - Enable LAN
+ Enable/disable LAN controller.
+ $EN_DIS
+**/
+ UINT8 PchLanEnable;
+
+/** Offset 0x036D - Reserved
+**/
+ UINT8 Reserved9[11];
+
+/** Offset 0x0378 - PCIe PTM enable/disable
+ Enable/disable Precision Time Measurement for PCIE Root Ports.
+**/
+ UINT8 PciePtm[28];
+
+/** Offset 0x0394 - Reserved
+**/
+ UINT8 Reserved10[81];
+
+/** Offset 0x03E5 - Transition time in microseconds from Low Current Mode Voltage to High Current Mode Voltage
+ This field has 1us resolution. When value is 0 PCH will not transition VCCIN_AUX
+ to low current mode voltage.
+**/
+ UINT8 PchFivrVccinAuxLowToHighCurModeVolTranTime;
+
+/** Offset 0x03E6 - Transition time in microseconds from Retention Mode Voltage to High Current Mode Voltage
+ This field has 1us resolution. When value is 0 PCH will not transition VCCIN_AUX
+ to retention mode voltage.
+**/
+ UINT8 PchFivrVccinAuxRetToHighCurModeVolTranTime;
+
+/** Offset 0x03E7 - Reserved
+**/
+ UINT8 Reserved11;
+
+/** Offset 0x03E8 - Transition time in microseconds from Off (0V) to High Current Mode Voltage
+ This field has 1us resolution. When value is 0 Transition to 0V is disabled.
+**/
+ UINT16 PchFivrVccinAuxOffToHighCurModeVolTranTime;
+
+/** Offset 0x03EA - Reserved
+**/
+ UINT8 Reserved12[50];
+
+/** Offset 0x041C - CNVi Configuration
+ This option allows for automatic detection of Connectivity Solution. [Auto Detection]
+ assumes that CNVi will be enabled when available, [Disable] allows for disabling CNVi.
+ 0:Disable, 1:Auto
+**/
+ UINT8 CnviMode;
+
+/** Offset 0x041D - CNVi BT Core
+ Enable/Disable CNVi BT Core, Default is ENABLE. 0: DISABLE, 1: ENABLE
+ $EN_DIS
+**/
+ UINT8 CnviBtCore;
+
+/** Offset 0x041E - CNVi BT Audio Offload
+ Enable/Disable BT Audio Offload, Default is DISABLE. 0: DISABLE, 1: ENABLE
+ $EN_DIS
+**/
+ UINT8 CnviBtAudioOffload;
+
+/** Offset 0x041F - Reserved
+**/
+ UINT8 Reserved13;
+
+/** Offset 0x0420 - CNVi RF_RESET pin muxing
+ Select CNVi RF_RESET# pin depending on board routing. TGP-LP: GPP_A8 = 0x2942E408(default)
+ or GPP_F4 = 0x194CE404. TGP-H: 0. Refer to GPIO_*_MUXING_CNVI_RF_RESET_* in GpioPins*.h.
+**/
+ UINT32 CnviRfResetPinMux;
+
+/** Offset 0x0424 - CNVi CLKREQ pin muxing
+ Select CNVi CLKREQ pin depending on board routing. TGP-LP: GPP_A9 = 0x3942E609(default)
+ or GPP_F5 = 0x394CE605. TGP-H: 0. Refer to GPIO_*_MUXING_CNVI_MODEM_CLKREQ_* in
+ GpioPins*.h.
+**/
+ UINT32 CnviClkreqPinMux;
+
+/** Offset 0x0428 - Reserved
+**/
+ UINT8 Reserved14[166];
+
+/** Offset 0x04CE - CdClock Frequency selection
+ 0 (Default) Auto (Max based on reference clock frequency), 0: 192, 1: 307.2, 2:
+ 312 Mhz, 3: 324Mhz, 4: 326.4 Mhz, 5: 552 Mhz, 6: 556.8 Mhz, 7: 648 Mhz, 8: 652.8 Mhz
+ 0xFF: Auto (Max based on reference clock frequency), 0: 192, 1: 307.2, 2: 312 Mhz,
+ 3: 324Mhz, 4: 326.4 Mhz, 5: 552 Mhz, 6: 556.8 Mhz, 7: 648 Mhz, 8: 652.8 Mhz
+**/
+ UINT8 CdClock;
+
+/** Offset 0x04CF - Enable/Disable PeiGraphicsPeimInit
+ <b>Enable(Default):</b> FSP will initialize the framebuffer and provide it via EFI_PEI_GRAPHICS_INFO_HOB.
+ Disable: FSP will NOT initialize the framebuffer.
+ $EN_DIS
+**/
+ UINT8 PeiGraphicsPeimInit;
+
+/** Offset 0x04D0 - Enable D3 Hot in TCSS
+ This policy will enable/disable D3 hot support in IOM
+ $EN_DIS
+**/
+ UINT8 D3HotEnable;
+
+/** Offset 0x04D1 - Reserved
+**/
+ UINT8 Reserved15[3];
+
+/** Offset 0x04D4 - TypeC port GPIO setting
+ GPIO Ping number for Type C Aux Oritation setting, use the GpioPad that is defined
+ in GpioPinsXXXH.h and GpioPinsXXXLp.h as argument.(XXX is platform name, Ex: Adl
+ = AlderLake)
+**/
+ UINT32 IomTypeCPortPadCfg[8];
+
+/** Offset 0x04F4 - Reserved
+**/
+ UINT8 Reserved16[8];
+
+/** Offset 0x04FC - Enable D3 Cold in TCSS
+ This policy will enable/disable D3 cold support in IOM
+ $EN_DIS
+**/
+ UINT8 D3ColdEnable;
+
+/** Offset 0x04FD - Reserved
+**/
+ UINT8 Reserved17[8];
+
+/** Offset 0x0505 - Enable VMD controller
+ Enable/disable to VMD controller.0: Disable(Default); 1: Enable
+ $EN_DIS
+**/
+ UINT8 VmdEnable;
+
+/** Offset 0x0506 - Reserved
+**/
+ UINT8 Reserved18[108];
+
+/** Offset 0x0572 - TCSS Aux Orientation Override Enable
+ Bits 0, 2, ... 10 control override enables, bits 1, 3, ... 11 control overrides
+**/
+ UINT16 TcssAuxOri;
+
+/** Offset 0x0574 - TCSS HSL Orientation Override Enable
+ Bits 0, 2, ... 10 control override enables, bits 1, 3, ... 11 control overrides
+**/
+ UINT16 TcssHslOri;
+
+/** Offset 0x0576 - Reserved
+**/
+ UINT8 Reserved19[2];
+
+/** Offset 0x0578 - ITBT Root Port Enable
+ ITBT Root Port Enable, 0:Disable, 1:Enable
+ 0:Disable, 1:Enable
+**/
+ UINT8 ITbtPcieRootPortEn[4];
+
+/** Offset 0x057C - Reserved
+**/
+ UINT8 Reserved20[2];
+
+/** Offset 0x057E - ITbtConnectTopology Timeout value
+ ITbtConnectTopologyTimeout value. Specified increment values in miliseconds. Range
+ is 0-10000. 100 = 100 ms.
+**/
+ UINT16 ITbtConnectTopologyTimeoutInMs;
+
+/** Offset 0x0580 - Reserved
+**/
+ UINT8 Reserved21[7];
+
+/** Offset 0x0587 - Enable/Disable PTM
+ This policy will enable/disable Precision Time Measurement for TCSS PCIe Root Ports
+ $EN_DIS
+**/
+ UINT8 PtmEnabled[4];
+
+/** Offset 0x058B - Reserved
+**/
+ UINT8 Reserved22[201];
+
+/** Offset 0x0654 - Skip Multi-Processor Initialization
+ When this is skipped, boot loader must initialize processors before SilicionInit
+ API. </b>0: Initialize; <b>1: Skip
+ $EN_DIS
+**/
+ UINT8 SkipMpInit;
+
+/** Offset 0x0655 - Reserved
+**/
+ UINT8 Reserved23[11];
+
+/** Offset 0x0660 - CpuMpPpi
+ <b>Optional</b> pointer to the boot loader's implementation of EFI_PEI_MP_SERVICES_PPI.
+ If not NULL, FSP will use the boot loader's implementation of multiprocessing.
+ See section 5.1.4 of the FSP Integration Guide for more details.
+**/
+ UINT32 CpuMpPpi;
+
+/** Offset 0x0664 - Reserved
+**/
+ UINT8 Reserved24[68];
+
+/** Offset 0x06A8 - Enable Power Optimizer
+ Enable DMI Power Optimizer on PCH side.
+ $EN_DIS
+**/
+ UINT8 PchPwrOptEnable;
+
+/** Offset 0x06A9 - Reserved
+**/
+ UINT8 Reserved25[33];
+
+/** Offset 0x06CA - Enable PCH ISH SPI Cs0 pins assigned
+ Set if ISH SPI Cs0 pins are to be enabled by BIOS. 0: Disable; 1: Enable.
+**/
+ UINT8 PchIshSpiCs0Enable[1];
+
+/** Offset 0x06CB - Reserved
+**/
+ UINT8 Reserved26[2];
+
+/** Offset 0x06CD - Enable PCH ISH SPI pins assigned
+ Set if ISH SPI native pins are to be enabled by BIOS. 0: Disable; 1: Enable.
+**/
+ UINT8 PchIshSpiEnable[1];
+
+/** Offset 0x06CE - Enable PCH ISH UART pins assigned
+ Set if ISH UART native pins are to be enabled by BIOS. 0: Disable; 1: Enable.
+**/
+ UINT8 PchIshUartEnable[2];
+
+/** Offset 0x06D0 - Enable PCH ISH I2C pins assigned
+ Set if ISH I2C native pins are to be enabled by BIOS. 0: Disable; 1: Enable.
+**/
+ UINT8 PchIshI2cEnable[3];
+
+/** Offset 0x06D3 - Enable PCH ISH GP pins assigned
+ Set if ISH GP native pins are to be enabled by BIOS. 0: Disable; 1: Enable.
+**/
+ UINT8 PchIshGpEnable[8];
+
+/** Offset 0x06DB - Reserved
+**/
+ UINT8 Reserved27[2];
+
+/** Offset 0x06DD - Enable LOCKDOWN BIOS LOCK
+ Enable the BIOS Lock feature and set EISS bit (D31:F5:RegDCh[5]) for the BIOS region
+ protection.
+ $EN_DIS
+**/
+ UINT8 PchLockDownBiosLock;
+
+/** Offset 0x06DE - Reserved
+**/
+ UINT8 Reserved28[2];
+
+/** Offset 0x06E0 - RTC Cmos Memory Lock
+ Enable RTC lower and upper 128 byte Lock bits to lock Bytes 38h-3Fh in the upper
+ and and lower 128-byte bank of RTC RAM.
+ $EN_DIS
+**/
+ UINT8 RtcMemoryLock;
+
+/** Offset 0x06E1 - Enable PCIE RP HotPlug
+ Indicate whether the root port is hot plug available.
+**/
+ UINT8 PcieRpHotPlug[28];
+
+/** Offset 0x06FD - Reserved
+**/
+ UINT8 Reserved29[56];
+
+/** Offset 0x0735 - Enable PCIE RP Clk Req Detect
+ Probe CLKREQ# signal before enabling CLKREQ# based power management.
+**/
+ UINT8 PcieRpClkReqDetect[28];
+
+/** Offset 0x0751 - PCIE RP Advanced Error Report
+ Indicate whether the Advanced Error Reporting is enabled.
+**/
+ UINT8 PcieRpAdvancedErrorReporting[28];
+
+/** Offset 0x076D - Reserved
+**/
+ UINT8 Reserved30[196];
+
+/** Offset 0x0831 - PCIE RP Max Payload
+ Max Payload Size supported, Default 128B, see enum PCH_PCIE_MAX_PAYLOAD.
+**/
+ UINT8 PcieRpMaxPayload[28];
+
+/** Offset 0x084D - Touch Host Controller Port 0 Assignment
+ Assign THC Port 0
+ 0x0:ThcAssignmentNone, 0x1:ThcAssignmentThc0
+**/
+ UINT8 ThcPort0Assignment;
+
+/** Offset 0x084E - Reserved
+**/
+ UINT8 Reserved31[6];
+
+/** Offset 0x0854 - Touch Host Controller Port 1 Assignment
+ Assign THC Port 1
+ 0x0:ThcAssignmentNone, 0x1:ThcPort1AssignmentThc0, 0x2:ThcAssignmentThc1
+**/
+ UINT8 ThcPort1Assignment;
+
+/** Offset 0x0855 - Reserved
+**/
+ UINT8 Reserved32[91];
+
+/** Offset 0x08B0 - PCIE RP Aspm
+ The ASPM configuration of the root port (see: PCH_PCIE_ASPM_CONTROL). Default is
+ PchPcieAspmAutoConfig.
+**/
+ UINT8 PcieRpAspm[28];
+
+/** Offset 0x08CC - PCIE RP L1 Substates
+ The L1 Substates configuration of the root port (see: PCH_PCIE_L1SUBSTATES_CONTROL).
+ Default is PchPcieL1SubstatesL1_1_2.
+**/
+ UINT8 PcieRpL1Substates[28];
+
+/** Offset 0x08E8 - PCIE RP Ltr Enable
+ Latency Tolerance Reporting Mechanism.
+**/
+ UINT8 PcieRpLtrEnable[28];
+
+/** Offset 0x0904 - Reserved
+**/
+ UINT8 Reserved33[102];
+
+/** Offset 0x096A - PCH Sata Pwr Opt Enable
+ SATA Power Optimizer on PCH side.
+ $EN_DIS
+**/
+ UINT8 SataPwrOptEnable;
+
+/** Offset 0x096B - Reserved
+**/
+ UINT8 Reserved34[50];
+
+/** Offset 0x099D - Enable SATA Port DmVal
+ DITO multiplier. Default is 15.
+**/
+ UINT8 SataPortsDmVal[8];
+
+/** Offset 0x09A5 - Reserved
+**/
+ UINT8 Reserved35;
+
+/** Offset 0x09A6 - Enable SATA Port DmVal
+ DEVSLP Idle Timeout (DITO), Default is 625.
+**/
+ UINT16 SataPortsDitoVal[8];
+
+/** Offset 0x09B6 - Reserved
+**/
+ UINT8 Reserved36[62];
+
+/** Offset 0x09F4 - USB2 Port Over Current Pin
+ Describe the specific over current pin number of USB 2.0 Port N.
+**/
+ UINT8 Usb2OverCurrentPin[16];
+
+/** Offset 0x0A04 - USB3 Port Over Current Pin
+ Describe the specific over current pin number of USB 3.0 Port N.
+**/
+ UINT8 Usb3OverCurrentPin[10];
+
+/** Offset 0x0A0E - Reserved
+**/
+ UINT8 Reserved37[14];
+
+/** Offset 0x0A1C - Enable 8254 Static Clock Gating
+ Set 8254CGE=1 is required for SLP_S0 support. However, set 8254CGE=1 in POST time
+ might fail to boot legacy OS using 8254 timer. Make sure it is disabled to support
+ legacy OS using 8254 timer. Also enable this while S0ix is enabled.
+ $EN_DIS
+**/
+ UINT8 Enable8254ClockGating;
+
+/** Offset 0x0A1D - Enable 8254 Static Clock Gating On S3
+ This is only applicable when Enable8254ClockGating is disabled. FSP will do the
+ 8254 CGE programming on S3 resume when Enable8254ClockGatingOnS3 is enabled. This
+ avoids the SMI requirement for the programming.
+ $EN_DIS
+**/
+ UINT8 Enable8254ClockGatingOnS3;
+
+/** Offset 0x0A1E - Reserved
+**/
+ UINT8 Reserved38;
+
+/** Offset 0x0A1F - Hybrid Storage Detection and Configuration Mode
+ Enables support for Hybrid storage devices. 0: Disabled; 1: Dynamic Configuration.
+ Default is 0: Disabled
+ 0: Disabled, 1: Dynamic Configuration
+**/
+ UINT8 HybridStorageMode;
+
+/** Offset 0x0A20 - Reserved
+**/
+ UINT8 Reserved39[113];
+
+/** Offset 0x0A91 - Enable PS_ON.
+ PS_ON is a new C10 state from the CPU on desktop SKUs that enables a lower power
+ target that will be required by the California Energy Commission (CEC). When FALSE,
+ PS_ON is to be disabled.
+ $EN_DIS
+**/
+ UINT8 PsOnEnable;
+
+/** Offset 0x0A92 - Reserved
+**/
+ UINT8 Reserved40[310];
+
+/** Offset 0x0BC8 - RpPtmBytes
+**/
+ UINT8 RpPtmBytes[4];
+
+/** Offset 0x0BCC - Reserved
+**/
+ UINT8 Reserved41[99];
+
+/** Offset 0x0C2F - Enable/Disable IGFX PmSupport
+ Enable(Default): Enable IGFX PmSupport, Disable: Disable IGFX PmSupport
+ $EN_DIS
+**/
+ UINT8 PmSupport;
+
+/** Offset 0x0C30 - Reserved
+**/
+ UINT8 Reserved42;
+
+/** Offset 0x0C31 - GT Frequency Limit
+ 0xFF: Auto(Default), 2: 100 Mhz, 3: 150 Mhz, 4: 200 Mhz, 5: 250 Mhz, 6: 300 Mhz,
+ 7: 350 Mhz, 8: 400 Mhz, 9: 450 Mhz, 0xA: 500 Mhz, 0xB: 550 Mhz, 0xC: 600 Mhz, 0xD:
+ 650 Mhz, 0xE: 700 Mhz, 0xF: 750 Mhz, 0x10: 800 Mhz, 0x11: 850 Mhz, 0x12:900 Mhz,
+ 0x13: 950 Mhz, 0x14: 1000 Mhz, 0x15: 1050 Mhz, 0x16: 1100 Mhz, 0x17: 1150 Mhz,
+ 0x18: 1200 Mhz
+ 0xFF: Auto(Default), 2: 100 Mhz, 3: 150 Mhz, 4: 200 Mhz, 5: 250 Mhz, 6: 300 Mhz,
+ 7: 350 Mhz, 8: 400 Mhz, 9: 450 Mhz, 0xA: 500 Mhz, 0xB: 550 Mhz, 0xC: 600 Mhz, 0xD:
+ 650 Mhz, 0xE: 700 Mhz, 0xF: 750 Mhz, 0x10: 800 Mhz, 0x11: 850 Mhz, 0x12:900 Mhz,
+ 0x13: 950 Mhz, 0x14: 1000 Mhz, 0x15: 1050 Mhz, 0x16: 1100 Mhz, 0x17: 1150 Mhz,
+ 0x18: 1200 Mhz
+**/
+ UINT8 GtFreqMax;
+
+/** Offset 0x0C32 - Reserved
+**/
+ UINT8 Reserved43[24];
+
+/** Offset 0x0C4A - Enable or Disable HWP
+ Enable or Disable HWP(Hardware P states) Support. 0: Disable; <b>1: Enable;</b>
+ 2-3:Reserved
+ $EN_DIS
+**/
+ UINT8 Hwp;
+
+/** Offset 0x0C4B - Reserved
+**/
+ UINT8 Reserved44[8];
+
+/** Offset 0x0C53 - TCC Activation Offset
+ TCC Activation Offset. Offset from factory set TCC activation temperature at which
+ the Thermal Control Circuit must be activated. TCC will be activated at TCC Activation
+ Temperature, in volts.For SKL Y SKU, the recommended default for this policy is
+ <b>10</b>, For all other SKUs the recommended default are <b>0</b>
+**/
+ UINT8 TccActivationOffset;
+
+/** Offset 0x0C54 - Reserved
+**/
+ UINT8 Reserved45[34];
+
+/** Offset 0x0C76 - Enable or Disable CPU power states (C-states)
+ Enable or Disable CPU power states (C-states). 0: Disable; <b>1: Enable</b>
+ $EN_DIS
+**/
+ UINT8 Cx;
+
+/** Offset 0x0C77 - Reserved
+**/
+ UINT8 Reserved46[197];
+
+/** Offset 0x0D3C - Enable LOCKDOWN SMI
+ Enable SMI_LOCK bit to prevent writes to the Global SMI Enable bit.
+ $EN_DIS
+**/
+ UINT8 PchLockDownGlobalSmi;
+
+/** Offset 0x0D3D - Enable LOCKDOWN BIOS Interface
+ Enable BIOS Interface Lock Down bit to prevent writes to the Backup Control Register.
+ $EN_DIS
+**/
+ UINT8 PchLockDownBiosInterface;
+
+/** Offset 0x0D3E - Unlock all GPIO pads
+ Force all GPIO pads to be unlocked for debug purpose.
+ $EN_DIS
+**/
+ UINT8 PchUnlockGpioPads;
+
+/** Offset 0x0D3F - Reserved
+**/
+ UINT8 Reserved47;
+
+/** Offset 0x0D40 - PCIE RP Ltr Max Snoop Latency
+ Latency Tolerance Reporting, Max Snoop Latency.
+**/
+ UINT16 PcieRpLtrMaxSnoopLatency[24];
+
+/** Offset 0x0D70 - PCIE RP Ltr Max No Snoop Latency
+ Latency Tolerance Reporting, Max Non-Snoop Latency.
+**/
+ UINT16 PcieRpLtrMaxNoSnoopLatency[24];
+
+/** Offset 0x0DA0 - Reserved
+**/
+ UINT8 Reserved48[289];
+
+/** Offset 0x0EC1 - LpmStateEnableMask
+**/
+ UINT8 LpmStateEnableMask;
+
+/** Offset 0x0EC2 - Reserved
+**/
+ UINT8 Reserved49[766];
+} FSP_S_CONFIG;
+
+/** Fsp S UPD Configuration
+**/
+typedef struct {
+
+/** Offset 0x0000
+**/
+ FSP_UPD_HEADER FspUpdHeader;
+
+/** Offset 0x0020
+**/
+ FSPS_ARCH_UPD FspsArchUpd;
+
+/** Offset 0x0040
+**/
+ FSP_S_CONFIG FspsConfig;
+
+/** Offset 0x11C0
+**/
+ UINT8 UnusedUpdSpace49[6];
+
+/** Offset 0x11C6
+**/
+ UINT16 UpdTerminator;
+} FSPS_UPD;
+
+#pragma pack()
+
+#endif
diff --git a/src/vendorcode/intel/fsp/fsp2_0/alderlake/MemInfoHob.h b/src/vendorcode/intel/fsp/fsp2_0/alderlake/MemInfoHob.h
new file mode 100644
index 0000000000..816ce06f8c
--- /dev/null
+++ b/src/vendorcode/intel/fsp/fsp2_0/alderlake/MemInfoHob.h
@@ -0,0 +1,293 @@
+/** @file
+ This file contains definitions required for creation of
+ Memory S3 Save data, Memory Info data and Memory Platform
+ data hobs.
+
+ @copyright
+ Copyright (c) 1999 - 2020, Intel Corporation. All rights reserved.<BR>
+ This program and the accompanying materials are licensed and made available under
+ the terms and conditions of the BSD License that accompanies this distribution.
+ The full text of the license may be found at
+ http://opensource.org/licenses/bsd-license.php.
+ THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+
+ WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+
+@par Specification Reference:
+**/
+#ifndef _MEM_INFO_HOB_H_
+#define _MEM_INFO_HOB_H_
+
+#pragma pack (push, 1)
+
+extern EFI_GUID gSiMemoryS3DataGuid;
+extern EFI_GUID gSiMemoryInfoDataGuid;
+extern EFI_GUID gSiMemoryPlatformDataGuid;
+
+#define MAX_TRACE_CACHE_TYPE 3
+
+#define MAX_NODE 1
+#define MAX_CH 2
+#define MAX_DIMM 2
+
+///
+/// Host reset states from MRC.
+///
+#define WARM_BOOT 2
+
+#define R_MC_CHNL_RANK_PRESENT 0x7C
+#define B_RANK0_PRS BIT0
+#define B_RANK1_PRS BIT1
+#define B_RANK2_PRS BIT4
+#define B_RANK3_PRS BIT5
+
+// @todo remove and use the MdePkg\Include\Pi\PiHob.h
+#if !defined(_PEI_HOB_H_) && !defined(__PI_HOB_H__)
+#ifndef __HOB__H__
+typedef struct _EFI_HOB_GENERIC_HEADER {
+ UINT16 HobType;
+ UINT16 HobLength;
+ UINT32 Reserved;
+} EFI_HOB_GENERIC_HEADER;
+
+typedef struct _EFI_HOB_GUID_TYPE {
+ EFI_HOB_GENERIC_HEADER Header;
+ EFI_GUID Name;
+ ///
+ /// Guid specific data goes here
+ ///
+} EFI_HOB_GUID_TYPE;
+#endif
+#endif
+
+///
+/// Defines taken from MRC so avoid having to include MrcInterface.h
+///
+
+//
+// Matches MAX_SPD_SAVE define in MRC
+//
+#ifndef MAX_SPD_SAVE
+#define MAX_SPD_SAVE 29
+#endif
+
+//
+// MRC version description.
+//
+typedef struct {
+ UINT8 Major; ///< Major version number
+ UINT8 Minor; ///< Minor version number
+ UINT8 Rev; ///< Revision number
+ UINT8 Build; ///< Build number
+} SiMrcVersion;
+
+//
+// Matches MrcChannelSts enum in MRC
+//
+#ifndef CHANNEL_NOT_PRESENT
+#define CHANNEL_NOT_PRESENT 0 // There is no channel present on the controller.
+#endif
+#ifndef CHANNEL_DISABLED
+#define CHANNEL_DISABLED 1 // There is a channel present but it is disabled.
+#endif
+#ifndef CHANNEL_PRESENT
+#define CHANNEL_PRESENT 2 // There is a channel present and it is enabled.
+#endif
+
+//
+// Matches MrcDimmSts enum in MRC
+//
+#ifndef DIMM_ENABLED
+#define DIMM_ENABLED 0 // DIMM/rank Pair is enabled, presence will be detected.
+#endif
+#ifndef DIMM_DISABLED
+#define DIMM_DISABLED 1 // DIMM/rank Pair is disabled, regardless of presence.
+#endif
+#ifndef DIMM_PRESENT
+#define DIMM_PRESENT 2 // There is a DIMM present in the slot/rank pair and it will be used.
+#endif
+#ifndef DIMM_NOT_PRESENT
+#define DIMM_NOT_PRESENT 3 // There is no DIMM present in the slot/rank pair.
+#endif
+
+//
+// Matches MrcBootMode enum in MRC
+//
+#ifndef __MRC_BOOT_MODE__
+#define __MRC_BOOT_MODE__ //The below values are originated from MrcCommonTypes.h
+ #ifndef INT32_MAX
+ #define INT32_MAX (0x7FFFFFFF)
+ #endif //INT32_MAX
+typedef enum {
+ bmCold, ///< Cold boot
+ bmWarm, ///< Warm boot
+ bmS3, ///< S3 resume
+ bmFast, ///< Fast boot
+ MrcBootModeMax, ///< MRC_BOOT_MODE enumeration maximum value.
+ MrcBootModeDelim = INT32_MAX ///< This value ensures the enum size is consistent on both sides of the PPI.
+} MRC_BOOT_MODE;
+#endif //__MRC_BOOT_MODE__
+
+//
+// Matches MrcDdrType enum in MRC
+//
+#ifndef MRC_DDR_TYPE_DDR4
+#define MRC_DDR_TYPE_DDR4 0
+#endif
+#ifndef MRC_DDR_TYPE_DDR3
+#define MRC_DDR_TYPE_DDR3 1
+#endif
+#ifndef MRC_DDR_TYPE_LPDDR3
+#define MRC_DDR_TYPE_LPDDR3 2
+#endif
+#ifndef MRC_DDR_TYPE_LPDDR4
+#define MRC_DDR_TYPE_LPDDR4 3
+#endif
+#ifndef MRC_DDR_TYPE_WIO2
+#define MRC_DDR_TYPE_WIO2 4
+#endif
+#ifndef MRC_DDR_TYPE_UNKNOWN
+#define MRC_DDR_TYPE_UNKNOWN 5
+#endif
+
+#define MAX_PROFILE_NUM 4 // number of memory profiles supported
+#define MAX_XMP_PROFILE_NUM 2 // number of XMP profiles supported
+
+//
+// DIMM timings
+//
+typedef struct {
+ UINT32 tCK; ///< Memory cycle time, in femtoseconds.
+ UINT16 NMode; ///< Number of tCK cycles for the channel DIMM's command rate mode.
+ UINT16 tCL; ///< Number of tCK cycles for the channel DIMM's CAS latency.
+ UINT16 tCWL; ///< Number of tCK cycles for the channel DIMM's minimum CAS write latency time.
+ UINT16 tFAW; ///< Number of tCK cycles for the channel DIMM's minimum four activate window delay time.
+ UINT16 tRAS; ///< Number of tCK cycles for the channel DIMM's minimum active to precharge delay time.
+ UINT16 tRCDtRP; ///< Number of tCK cycles for the channel DIMM's minimum RAS# to CAS# delay time and Row Precharge delay time.
+ UINT16 tREFI; ///< Number of tCK cycles for the channel DIMM's minimum Average Periodic Refresh Interval.
+ UINT16 tRFC; ///< Number of tCK cycles for the channel DIMM's minimum refresh recovery delay time.
+ UINT16 tRFCpb; ///< Number of tCK cycles for the channel DIMM's minimum per bank refresh recovery delay time.
+ UINT16 tRFC2; ///< Number of tCK cycles for the channel DIMM's minimum refresh recovery delay time.
+ UINT16 tRFC4; ///< Number of tCK cycles for the channel DIMM's minimum refresh recovery delay time.
+ UINT16 tRPab; ///< Number of tCK cycles for the channel DIMM's minimum row precharge delay time for all banks.
+ UINT16 tRRD; ///< Number of tCK cycles for the channel DIMM's minimum row active to row active delay time.
+ UINT16 tRRD_L; ///< Number of tCK cycles for the channel DIMM's minimum row active to row active delay time for same bank groups.
+ UINT16 tRRD_S; ///< Number of tCK cycles for the channel DIMM's minimum row active to row active delay time for different bank groups.
+ UINT16 tRTP; ///< Number of tCK cycles for the channel DIMM's minimum internal read to precharge command delay time.
+ UINT16 tWR; ///< Number of tCK cycles for the channel DIMM's minimum write recovery time.
+ UINT16 tWTR; ///< Number of tCK cycles for the channel DIMM's minimum internal write to read command delay time.
+ UINT16 tWTR_L; ///< Number of tCK cycles for the channel DIMM's minimum internal write to read command delay time for same bank groups.
+ UINT16 tWTR_S; ///< Number of tCK cycles for the channel DIMM's minimum internal write to read command delay time for different bank groups.
+ UINT16 tCCD_L; ///< Number of tCK cycles for the channel DIMM's minimum CAS-to-CAS delay for same bank group.
+} MRC_CH_TIMING;
+
+///
+/// Memory SMBIOS & OC Memory Data Hob
+///
+typedef struct {
+ UINT8 Status; ///< See MrcDimmStatus for the definition of this field.
+ UINT8 DimmId;
+ UINT32 DimmCapacity; ///< DIMM size in MBytes.
+ UINT16 MfgId;
+ UINT8 ModulePartNum[20]; ///< Module part number for DDR3 is 18 bytes however for DRR4 20 bytes as per JEDEC Spec, so reserving 20 bytes
+ UINT8 RankInDimm; ///< The number of ranks in this DIMM.
+ UINT8 SpdDramDeviceType; ///< Save SPD DramDeviceType information needed for SMBIOS structure creation.
+ UINT8 SpdModuleType; ///< Save SPD ModuleType information needed for SMBIOS structure creation.
+ UINT8 SpdModuleMemoryBusWidth; ///< Save SPD ModuleMemoryBusWidth information needed for SMBIOS structure creation.
+ UINT8 SpdSave[MAX_SPD_SAVE]; ///< Save SPD Manufacturing information needed for SMBIOS structure creation.
+ UINT16 Speed; ///< The maximum capable speed of the device, in MHz
+ UINT8 MdSocket; ///< MdSocket: 0 = Memory Down, 1 = Socketed. Needed for SMBIOS structure creation.
+} DIMM_INFO;
+
+typedef struct {
+ UINT8 Status; ///< Indicates whether this channel should be used.
+ UINT8 ChannelId;
+ UINT8 DimmCount; ///< Number of valid DIMMs that exist in the channel.
+ MRC_CH_TIMING Timing[MAX_PROFILE_NUM]; ///< The channel timing values.
+ DIMM_INFO DimmInfo[MAX_DIMM]; ///< Save the DIMM output characteristics.
+} CHANNEL_INFO;
+
+typedef struct {
+ UINT8 Status; ///< Indicates whether this controller should be used.
+ UINT16 DeviceId; ///< The PCI device id of this memory controller.
+ UINT8 RevisionId; ///< The PCI revision id of this memory controller.
+ UINT8 ChannelCount; ///< Number of valid channels that exist on the controller.
+ CHANNEL_INFO ChannelInfo[MAX_CH]; ///< The following are channel level definitions.
+} CONTROLLER_INFO;
+
+typedef struct {
+ UINT64 BaseAddress; ///< Trace Base Address
+ UINT64 TotalSize; ///< Total Trace Region of Same Cache type
+ UINT8 CacheType; ///< Trace Cache Type
+ UINT8 ErrorCode; ///< Trace Region Allocation Fail Error code
+ UINT8 Rsvd[2];
+} PSMI_MEM_INFO;
+
+typedef struct {
+ UINT8 Revision;
+ UINT16 DataWidth; ///< Data width, in bits, of this memory device
+ /** As defined in SMBIOS 3.0 spec
+ Section 7.18.2 and Table 75
+ **/
+ UINT8 MemoryType; ///< DDR type: DDR3, DDR4, or LPDDR3
+ UINT16 MaximumMemoryClockSpeed;///< The maximum capable speed of the device, in megahertz (MHz)
+ UINT16 ConfiguredMemoryClockSpeed; ///< The configured clock speed to the memory device, in megahertz (MHz)
+ /** As defined in SMBIOS 3.0 spec
+ Section 7.17.3 and Table 72
+ **/
+ UINT8 ErrorCorrectionType;
+
+ SiMrcVersion Version;
+ BOOLEAN EccSupport;
+ UINT8 MemoryProfile;
+ UINT32 TotalPhysicalMemorySize;
+ UINT32 DefaultXmptCK[MAX_XMP_PROFILE_NUM];///< Stores the tCK value read from SPD XMP profiles if they exist.
+ UINT8 XmpProfileEnable; ///< If XMP capable DIMMs are detected, this will indicate which XMP Profiles are common among all DIMMs.
+ UINT8 Ratio;
+ UINT8 RefClk;
+ UINT32 VddVoltage[MAX_PROFILE_NUM];
+ CONTROLLER_INFO Controller[MAX_NODE];
+} MEMORY_INFO_DATA_HOB;
+
+/**
+ Memory Platform Data Hob
+
+ <b>Revision 1:</b>
+ - Initial version.
+ <b>Revision 2:</b>
+ - Added TsegBase, PrmrrSize, PrmrrBase, Gttbase, MmioSize, PciEBaseAddress fields
+**/
+typedef struct {
+ UINT8 Revision;
+ UINT8 Reserved[3];
+ UINT32 BootMode;
+ UINT32 TsegSize;
+ UINT32 TsegBase;
+ UINT32 PrmrrSize;
+ UINT64 PrmrrBase;
+ UINT32 PramSize;
+ UINT64 PramBase;
+ UINT64 DismLimit;
+ UINT64 DismBase;
+ UINT32 GttBase;
+ UINT32 MmioSize;
+ UINT32 PciEBaseAddress;
+//
+// CPU:RestrictedBegin
+//
+ UINT32 SharedMailboxBase;
+//
+// CPU:RestrictedEnd
+//
+ PSMI_MEM_INFO PsmiInfo[MAX_TRACE_CACHE_TYPE];
+} MEMORY_PLATFORM_DATA;
+
+typedef struct {
+ EFI_HOB_GUID_TYPE EfiHobGuidType;
+ MEMORY_PLATFORM_DATA Data;
+ UINT8 *Buffer;
+} MEMORY_PLATFORM_DATA_HOB;
+
+#pragma pack (pop)
+
+#endif // _MEM_INFO_HOB_H_
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