diff options
| -rw-r--r-- | src/soc/intel/cannonlake/bootblock/pch.c | 4 | ||||
| -rw-r--r-- | src/soc/intel/icelake/bootblock/pch.c | 4 | ||||
| -rw-r--r-- | src/soc/intel/skylake/bootblock/pch.c | 6 | ||||
| -rw-r--r-- | src/soc/intel/tigerlake/bootblock/pch.c | 4 |
4 files changed, 9 insertions, 9 deletions
diff --git a/src/soc/intel/cannonlake/bootblock/pch.c b/src/soc/intel/cannonlake/bootblock/pch.c index e7b79a0a68..eca28b33dd 100644 --- a/src/soc/intel/cannonlake/bootblock/pch.c +++ b/src/soc/intel/cannonlake/bootblock/pch.c @@ -168,8 +168,8 @@ void pch_early_iorange_init(void) if (pch_check_decode_enable() == 0) { io_enables = lpc_enable_fixed_io_ranges(io_enables); /* - * Set up LPC IO Enables PCR[DMI] + 2774h [15:0] to the same - * value program in LPC PCI offset 82h. + * Set LPC IO Enables PCR[DMI] + 2774h [15:0] to the same + * value programmed in LPC PCI offset 82h. */ pcr_write16(PID_DMI, PCR_DMI_LPCIOE, io_enables); /* diff --git a/src/soc/intel/icelake/bootblock/pch.c b/src/soc/intel/icelake/bootblock/pch.c index b1309a45b0..f51ecab4af 100644 --- a/src/soc/intel/icelake/bootblock/pch.c +++ b/src/soc/intel/icelake/bootblock/pch.c @@ -140,8 +140,8 @@ void pch_early_iorange_init(void) if (pch_check_decode_enable() == 0) { io_enables = lpc_enable_fixed_io_ranges(io_enables); /* - * Set up ESPI IO Enables PCR[DMI] + 2774h [15:0] to the same - * value program in ESPI PCI offset 82h. + * Set ESPI IO Enables PCR[DMI] + 2774h [15:0] to the same + * value programmed in ESPI PCI offset 82h. */ pcr_write16(PID_DMI, PCR_DMI_LPCIOE, io_enables); /* diff --git a/src/soc/intel/skylake/bootblock/pch.c b/src/soc/intel/skylake/bootblock/pch.c index 7763cf0033..d5d3aedc3d 100644 --- a/src/soc/intel/skylake/bootblock/pch.c +++ b/src/soc/intel/skylake/bootblock/pch.c @@ -135,9 +135,9 @@ void pch_early_iorange_init(void) if (pch_check_decode_enable() == 0) { io_enables = lpc_enable_fixed_io_ranges(io_enables); /* - * As per PCH BWG 2.5.16. - * Set up LPC IO Enables PCR[DMI] + 2774h [15:0] to the same - * value program in LPC PCI offset 82h. + * As per PCH BWG 2.5.1.6. + * Set LPC IO Enables PCR[DMI] + 2774h [15:0] to the same + * value programmed in LPC PCI offset 82h. */ pcr_write16(PID_DMI, PCR_DMI_LPCIOE, io_enables); /* diff --git a/src/soc/intel/tigerlake/bootblock/pch.c b/src/soc/intel/tigerlake/bootblock/pch.c index 33637e9e01..090f88f910 100644 --- a/src/soc/intel/tigerlake/bootblock/pch.c +++ b/src/soc/intel/tigerlake/bootblock/pch.c @@ -165,8 +165,8 @@ void pch_early_iorange_init(void) if (pch_check_decode_enable() == 0) { io_enables = lpc_enable_fixed_io_ranges(io_enables); /* - * Set up ESPI IO Enables PCR[DMI] + 2774h [15:0] to the same - * value program in ESPI PCI offset 82h. + * Set ESPI IO Enables PCR[DMI] + 2774h [15:0] to the same + * value programmed in ESPI PCI offset 82h. */ pcr_write16(PID_DMI, PCR_DMI_LPCIOE, io_enables); /* |