diff options
40 files changed, 96 insertions, 60 deletions
diff --git a/src/arch/x86/include/arch/io.h b/src/arch/x86/include/arch/io.h index d35e9647ab..37b2e957fe 100644 --- a/src/arch/x86/include/arch/io.h +++ b/src/arch/x86/include/arch/io.h @@ -427,63 +427,4 @@ void pnp_set_drq(pnp_devfn_t dev, unsigned int index, unsigned int drq) } #endif /* __SIMPLE_DEVICE__ */ - -#ifndef __SIMPLE_DEVICE__ -#include <device/pci_ops.h> -#endif - -static inline __attribute__((always_inline)) -void pci_or_config8(device_t dev, unsigned int where, u8 ormask) -{ - u8 value = pci_read_config8(dev, where); - pci_write_config8(dev, where, value | ormask); -} - -static inline __attribute__((always_inline)) -void pci_or_config16(device_t dev, unsigned int where, u16 ormask) -{ - u16 value = pci_read_config16(dev, where); - pci_write_config16(dev, where, value | ormask); -} - -static inline __attribute__((always_inline)) -void pci_or_config32(device_t dev, unsigned int where, u32 ormask) -{ - u32 value = pci_read_config32(dev, where); - pci_write_config32(dev, where, value | ormask); -} - -static inline __attribute__((always_inline)) -void pci_update_config8(device_t dev, int reg, u8 mask, u8 or) -{ - u8 reg8; - - reg8 = pci_read_config8(dev, reg); - reg8 &= mask; - reg8 |= or; - pci_write_config8(dev, reg, reg8); -} - -static inline __attribute__((always_inline)) -void pci_update_config16(device_t dev, int reg, u16 mask, u16 or) -{ - u16 reg16; - - reg16 = pci_read_config16(dev, reg); - reg16 &= mask; - reg16 |= or; - pci_write_config16(dev, reg, reg16); -} - -static inline __attribute__((always_inline)) -void pci_update_config32(device_t dev, int reg, u32 mask, u32 or) -{ - u32 reg32; - - reg32 = pci_read_config32(dev, reg); - reg32 &= mask; - reg32 |= or; - pci_write_config32(dev, reg, reg32); -} - #endif diff --git a/src/cpu/intel/haswell/smmrelocate.c b/src/cpu/intel/haswell/smmrelocate.c index 8d9a4dcc67..d2683affbf 100644 --- a/src/cpu/intel/haswell/smmrelocate.c +++ b/src/cpu/intel/haswell/smmrelocate.c @@ -17,6 +17,7 @@ #include <string.h> #include <device/device.h> #include <device/pci.h> +#include <device/pci_ops.h> #include <cpu/cpu.h> #include <cpu/x86/cache.h> #include <cpu/x86/lapic.h> diff --git a/src/device/pciexp_device.c b/src/device/pciexp_device.c index c020159b0e..b15d9c2a2b 100644 --- a/src/device/pciexp_device.c +++ b/src/device/pciexp_device.c @@ -19,6 +19,7 @@ #include <device/device.h> #include <device/pci.h> #include <device/pci_ids.h> +#include <device/pci_ops.h> #include <device/pciexp.h> unsigned int pciexp_find_extended_cap(device_t dev, unsigned int cap) diff --git a/src/include/device/device.h b/src/include/device/device.h index 15e477afd6..02a933ecb8 100644 --- a/src/include/device/device.h +++ b/src/include/device/device.h @@ -19,6 +19,7 @@ struct device; #ifndef __SIMPLE_DEVICE__ typedef struct device *device_t; #endif +#include <arch/io.h> struct pci_operations; struct pci_bus_operations; diff --git a/src/include/device/pci_ops.h b/src/include/device/pci_ops.h index 3310e10bf4..358f92ddeb 100644 --- a/src/include/device/pci_ops.h +++ b/src/include/device/pci_ops.h @@ -15,4 +15,62 @@ void pci_write_config32(struct device *dev, unsigned int where, u32 val); #endif +/* + * Use device_t here as the functions are to be used with either + * __SIMPLE_DEVICE__ defined or undefined. + */ +static inline __attribute__((always_inline)) +void pci_or_config8(device_t dev, unsigned int where, u8 ormask) +{ + u8 value = pci_read_config8(dev, where); + pci_write_config8(dev, where, value | ormask); +} + +static inline __attribute__((always_inline)) +void pci_or_config16(device_t dev, unsigned int where, u16 ormask) +{ + u16 value = pci_read_config16(dev, where); + pci_write_config16(dev, where, value | ormask); +} + +static inline __attribute__((always_inline)) +void pci_or_config32(device_t dev, unsigned int where, u32 ormask) +{ + u32 value = pci_read_config32(dev, where); + pci_write_config32(dev, where, value | ormask); +} + +static inline __attribute__((always_inline)) +void pci_update_config8(device_t dev, int reg, u8 mask, u8 or) +{ + u8 reg8; + + reg8 = pci_read_config8(dev, reg); + reg8 &= mask; + reg8 |= or; + pci_write_config8(dev, reg, reg8); +} + +static inline __attribute__((always_inline)) +void pci_update_config16(device_t dev, int reg, u16 mask, u16 or) +{ + u16 reg16; + + reg16 = pci_read_config16(dev, reg); + reg16 &= mask; + reg16 |= or; + pci_write_config16(dev, reg, reg16); +} + +static inline __attribute__((always_inline)) +void pci_update_config32(device_t dev, int reg, u32 mask, u32 or) +{ + u32 reg32; + + reg32 = pci_read_config32(dev, reg); + reg32 &= mask; + reg32 |= or; + pci_write_config32(dev, reg, reg32); +} + #endif /* PCI_OPS_H */ diff --git a/src/mainboard/asus/maximus_iv_gene-z/romstage.c b/src/mainboard/asus/maximus_iv_gene-z/romstage.c index 75f99727b1..d32b6f9735 100644 --- a/src/mainboard/asus/maximus_iv_gene-z/romstage.c +++ b/src/mainboard/asus/maximus_iv_gene-z/romstage.c @@ -15,6 +15,7 @@ */ #include <arch/io.h> +#include <device/pci_ops.h> #include <device/dram/ddr3.h> #include <northbridge/intel/sandybridge/raminit_native.h> #include <northbridge/intel/sandybridge/sandybridge.h> diff --git a/src/mainboard/gizmosphere/gizmo/mainboard.c b/src/mainboard/gizmosphere/gizmo/mainboard.c index ec06ca2852..b3d1e6c9a3 100644 --- a/src/mainboard/gizmosphere/gizmo/mainboard.c +++ b/src/mainboard/gizmosphere/gizmo/mainboard.c @@ -19,6 +19,7 @@ #include <delay.h> #include <device/device.h> #include <device/pci_def.h> +#include <device/pci_ops.h> #include <southbridge/amd/sb800/sb800.h> #include "SBPLATFORM.h" diff --git a/src/mainboard/google/auron/variant.h b/src/mainboard/google/auron/variant.h index d5c23471e6..41c157fd65 100644 --- a/src/mainboard/google/auron/variant.h +++ b/src/mainboard/google/auron/variant.h @@ -15,6 +15,7 @@ #define VARIANT_H #include <arch/io.h> +#include <device/device.h> #include <soc/romstage.h> int variant_smbios_data(device_t dev, int *handle, unsigned long *current); diff --git a/src/mainboard/lenovo/x60/mainboard.c b/src/mainboard/lenovo/x60/mainboard.c index 81175ec39b..a0d4599fa8 100644 --- a/src/mainboard/lenovo/x60/mainboard.c +++ b/src/mainboard/lenovo/x60/mainboard.c @@ -18,6 +18,7 @@ #include <device/pci_def.h> #include <device/pci_ids.h> #include <device/device.h> +#include <device/pci_ops.h> #include <arch/io.h> #include <ec/acpi/ec.h> #include <northbridge/intel/i945/i945.h> diff --git a/src/northbridge/amd/agesa/family14/state_machine.c b/src/northbridge/amd/agesa/family14/state_machine.c index 025d94fffd..fd9e3d0eaa 100644 --- a/src/northbridge/amd/agesa/family14/state_machine.c +++ b/src/northbridge/amd/agesa/family14/state_machine.c @@ -20,6 +20,7 @@ #include <cbmem.h> #include <device/device.h> #include <device/pci_def.h> +#include <device/pci_ops.h> #include <halt.h> #include <reset.h> #include <smp/node.h> diff --git a/src/northbridge/intel/fsp_sandybridge/finalize.c b/src/northbridge/intel/fsp_sandybridge/finalize.c index 4ceb75688e..b02023db4b 100644 --- a/src/northbridge/intel/fsp_sandybridge/finalize.c +++ b/src/northbridge/intel/fsp_sandybridge/finalize.c @@ -16,6 +16,7 @@ #include <arch/io.h> #include <stdlib.h> +#include <device/pci_ops.h> #include "northbridge.h" #define PCI_DEV_SNB PCI_DEV(0, 0, 0) diff --git a/src/northbridge/intel/haswell/finalize.c b/src/northbridge/intel/haswell/finalize.c index 04f73566db..5f42518891 100644 --- a/src/northbridge/intel/haswell/finalize.c +++ b/src/northbridge/intel/haswell/finalize.c @@ -16,6 +16,7 @@ #include <arch/io.h> #include <stdlib.h> +#include <device/pci_ops.h> #include "haswell.h" #define PCI_DEV_HSW PCI_DEV(0, 0, 0) diff --git a/src/northbridge/intel/nehalem/finalize.c b/src/northbridge/intel/nehalem/finalize.c index 0b5cb74ce2..f90f93769f 100644 --- a/src/northbridge/intel/nehalem/finalize.c +++ b/src/northbridge/intel/nehalem/finalize.c @@ -16,6 +16,7 @@ #include <arch/io.h> #include <stdlib.h> +#include <device/pci_ops.h> #include "nehalem.h" #define PCI_DEV_SNB PCI_DEV(0, 0, 0) diff --git a/src/northbridge/intel/sandybridge/finalize.c b/src/northbridge/intel/sandybridge/finalize.c index 21bf9da332..3fb0aa6dee 100644 --- a/src/northbridge/intel/sandybridge/finalize.c +++ b/src/northbridge/intel/sandybridge/finalize.c @@ -16,6 +16,7 @@ #include <arch/io.h> #include <stdlib.h> +#include <device/pci_ops.h> #include "sandybridge.h" #define PCI_DEV_SNB PCI_DEV(0, 0, 0) diff --git a/src/soc/amd/stoneyridge/cpu.c b/src/soc/amd/stoneyridge/cpu.c index 15dd38147c..2c415a3e25 100644 --- a/src/soc/amd/stoneyridge/cpu.c +++ b/src/soc/amd/stoneyridge/cpu.c @@ -21,6 +21,7 @@ #include <cpu/x86/lapic.h> #include <cpu/amd/amdfam15.h> #include <device/device.h> +#include <device/pci_ops.h> #include <soc/pci_devs.h> #include <soc/cpu.h> #include <soc/northbridge.h> diff --git a/src/soc/amd/stoneyridge/nb_util.c b/src/soc/amd/stoneyridge/nb_util.c index 4d3e53faf3..d5de067814 100644 --- a/src/soc/amd/stoneyridge/nb_util.c +++ b/src/soc/amd/stoneyridge/nb_util.c @@ -15,6 +15,7 @@ #include <soc/northbridge.h> #include <soc/pci_devs.h> +#include <device/pci_ops.h> uint32_t nb_ioapic_read(unsigned int index) { diff --git a/src/soc/amd/stoneyridge/reset.c b/src/soc/amd/stoneyridge/reset.c index 886f33cdcc..a133a88b92 100644 --- a/src/soc/amd/stoneyridge/reset.c +++ b/src/soc/amd/stoneyridge/reset.c @@ -18,6 +18,7 @@ #include <reset.h> #include <soc/northbridge.h> #include <soc/pci_devs.h> +#include <device/pci_ops.h> #include <soc/southbridge.h> /* Clear bits 5, 9 & 10, used to signal the reset type */ diff --git a/src/soc/amd/stoneyridge/tsc_freq.c b/src/soc/amd/stoneyridge/tsc_freq.c index 1f48306afe..8c18884001 100644 --- a/src/soc/amd/stoneyridge/tsc_freq.c +++ b/src/soc/amd/stoneyridge/tsc_freq.c @@ -21,6 +21,7 @@ #include <cpu/amd/amdfam15.h> #include <console/console.h> #include <soc/pci_devs.h> +#include <device/pci_ops.h> unsigned long tsc_freq_mhz(void) { diff --git a/src/soc/intel/apollolake/cse.c b/src/soc/intel/apollolake/cse.c index 3e1792c84a..8842500fa8 100644 --- a/src/soc/intel/apollolake/cse.c +++ b/src/soc/intel/apollolake/cse.c @@ -20,6 +20,7 @@ #include <fmap.h> #include <intelblocks/cse.h> #include <soc/pci_devs.h> +#include <device/pci_ops.h> #include <stdint.h> #include <compiler.h> diff --git a/src/soc/intel/broadwell/acpi.c b/src/soc/intel/broadwell/acpi.c index 69c1eb81dc..162542fe3e 100644 --- a/src/soc/intel/broadwell/acpi.c +++ b/src/soc/intel/broadwell/acpi.c @@ -19,7 +19,7 @@ #include <arch/io.h> #include <arch/smp/mpspec.h> #include <cbmem.h> -#include <console/console.h> +#include <device/pci_ops.h> #include <cpu/x86/smm.h> #include <console/console.h> #include <types.h> diff --git a/src/soc/intel/broadwell/pcie.c b/src/soc/intel/broadwell/pcie.c index aff66a3e09..12d278fce7 100644 --- a/src/soc/intel/broadwell/pcie.c +++ b/src/soc/intel/broadwell/pcie.c @@ -20,6 +20,7 @@ #include <device/pciexp.h> #include <device/pci_def.h> #include <device/pci_ids.h> +#include <device/pci_ops.h> #include <soc/gpio.h> #include <soc/lpc.h> #include <soc/iobp.h> diff --git a/src/soc/intel/broadwell/romstage/pch.c b/src/soc/intel/broadwell/romstage/pch.c index 35a361ae4f..7e614c1aa4 100644 --- a/src/soc/intel/broadwell/romstage/pch.c +++ b/src/soc/intel/broadwell/romstage/pch.c @@ -17,6 +17,7 @@ #include <console/console.h> #include <device/device.h> #include <device/pci_def.h> +#include <device/pci_ops.h> #include <reg_script.h> #include <soc/iomap.h> #include <soc/lpc.h> diff --git a/src/soc/intel/cannonlake/pmc.c b/src/soc/intel/cannonlake/pmc.c index cd77747716..c6c1694561 100644 --- a/src/soc/intel/cannonlake/pmc.c +++ b/src/soc/intel/cannonlake/pmc.c @@ -19,6 +19,7 @@ #include <chip.h> #include <console/console.h> #include <device/device.h> +#include <device/pci_ops.h> #include <intelblocks/pmc.h> #include <intelblocks/pmclib.h> #include <intelblocks/rtc.h> diff --git a/src/soc/intel/common/block/fast_spi/fast_spi.c b/src/soc/intel/common/block/fast_spi/fast_spi.c index 288e0c4389..b13408af7b 100644 --- a/src/soc/intel/common/block/fast_spi/fast_spi.c +++ b/src/soc/intel/common/block/fast_spi/fast_spi.c @@ -16,6 +16,7 @@ #include <arch/io.h> #include <assert.h> #include <device/pci_def.h> +#include <device/pci_ops.h> #include <commonlib/helpers.h> #include <console/console.h> #include <cpu/x86/mtrr.h> diff --git a/src/soc/intel/common/block/gspi/gspi.c b/src/soc/intel/common/block/gspi/gspi.c index 8bf27de1cf..175fad8b24 100644 --- a/src/soc/intel/common/block/gspi/gspi.c +++ b/src/soc/intel/common/block/gspi/gspi.c @@ -21,6 +21,7 @@ #include <delay.h> #include <device/device.h> #include <device/pci_def.h> +#include <device/pci_ops.h> #include <intelblocks/gspi.h> #include <string.h> #include <timer.h> diff --git a/src/soc/intel/common/block/pcie/pcie.c b/src/soc/intel/common/block/pcie/pcie.c index 7d383fdfaa..4cd057d363 100644 --- a/src/soc/intel/common/block/pcie/pcie.c +++ b/src/soc/intel/common/block/pcie/pcie.c @@ -18,6 +18,7 @@ #include <device/pciexp.h> #include <device/pci_def.h> #include <device/pci_ids.h> +#include <device/pci_ops.h> #define CACHE_LINE_SIZE 0x10 /* Latency tolerance reporting, max non-snoop latency value 3.14ms */ diff --git a/src/soc/intel/common/block/pcr/pcr.c b/src/soc/intel/common/block/pcr/pcr.c index cf487c5589..39f9bb832f 100644 --- a/src/soc/intel/common/block/pcr/pcr.c +++ b/src/soc/intel/common/block/pcr/pcr.c @@ -17,6 +17,7 @@ #include <assert.h> #include <console/console.h> #include <intelblocks/pcr.h> +#include <device/pci_ops.h> #include <soc/pci_devs.h> #include <soc/pcr_ids.h> #include <timer.h> diff --git a/src/soc/intel/skylake/acpi.c b/src/soc/intel/skylake/acpi.c index 699d76affa..3d133f9266 100644 --- a/src/soc/intel/skylake/acpi.c +++ b/src/soc/intel/skylake/acpi.c @@ -49,6 +49,7 @@ #include <types.h> #include <vendorcode/google/chromeos/gnvs.h> #include <wrdd.h> +#include <device/pci_ops.h> /* * List of suported C-states in this processor. diff --git a/src/soc/intel/skylake/pmc.c b/src/soc/intel/skylake/pmc.c index 297188bfe4..ecdc6bb93b 100644 --- a/src/soc/intel/skylake/pmc.c +++ b/src/soc/intel/skylake/pmc.c @@ -19,6 +19,7 @@ #include <chip.h> #include <console/console.h> #include <device/device.h> +#include <device/pci_ops.h> #include <intelblocks/pmc.h> #include <intelblocks/pmclib.h> #include <intelblocks/rtc.h> diff --git a/src/soc/intel/skylake/systemagent.c b/src/soc/intel/skylake/systemagent.c index 1d635834ab..2c4408fec6 100644 --- a/src/soc/intel/skylake/systemagent.c +++ b/src/soc/intel/skylake/systemagent.c @@ -20,6 +20,7 @@ #include <console/console.h> #include <delay.h> #include <device/device.h> +#include <device/pci_ops.h> #include <intelblocks/systemagent.h> #include <soc/cpu.h> #include <soc/iomap.h> diff --git a/src/soc/intel/skylake/vr_config.c b/src/soc/intel/skylake/vr_config.c index 053e793107..0659d04e3a 100644 --- a/src/soc/intel/skylake/vr_config.c +++ b/src/soc/intel/skylake/vr_config.c @@ -16,6 +16,7 @@ #include <arch/io.h> #include <device/pci_ids.h> +#include <device/pci_ops.h> #include <fsp/api.h> #include <soc/ramstage.h> #include <soc/vr_config.h> diff --git a/src/southbridge/intel/bd82x6x/early_pch_common.c b/src/southbridge/intel/bd82x6x/early_pch_common.c index a41c2f3ee4..2ef47a2e46 100644 --- a/src/southbridge/intel/bd82x6x/early_pch_common.c +++ b/src/southbridge/intel/bd82x6x/early_pch_common.c @@ -18,6 +18,7 @@ #include <timestamp.h> #include <cpu/x86/tsc.h> #include <device/pci_def.h> +#include <device/pci_ops.h> #include "pch.h" #include <arch/acpi.h> #include <console/console.h> diff --git a/src/southbridge/intel/bd82x6x/finalize.c b/src/southbridge/intel/bd82x6x/finalize.c index f5cd9cc274..9724f08d93 100644 --- a/src/southbridge/intel/bd82x6x/finalize.c +++ b/src/southbridge/intel/bd82x6x/finalize.c @@ -15,6 +15,7 @@ */ #include <arch/io.h> +#include <device/pci_ops.h> #include <console/post_codes.h> #include <cpu/x86/smm.h> #include <southbridge/intel/common/rcba.h> diff --git a/src/southbridge/intel/bd82x6x/lpc.c b/src/southbridge/intel/bd82x6x/lpc.c index c57eeca769..8d125eb6d8 100644 --- a/src/southbridge/intel/bd82x6x/lpc.c +++ b/src/southbridge/intel/bd82x6x/lpc.c @@ -18,6 +18,7 @@ #include <device/device.h> #include <device/pci.h> #include <device/pci_ids.h> +#include <device/pci_ops.h> #include <pc80/mc146818rtc.h> #include <pc80/isa-dma.h> #include <pc80/i8259.h> diff --git a/src/southbridge/intel/common/acpi_pirq_gen.c b/src/southbridge/intel/common/acpi_pirq_gen.c index 3ff591c1e5..fc26d1aa95 100644 --- a/src/southbridge/intel/common/acpi_pirq_gen.c +++ b/src/southbridge/intel/common/acpi_pirq_gen.c @@ -17,6 +17,7 @@ #include <arch/io.h> #include <console/console.h> #include <device/pci_def.h> +#include <device/pci_ops.h> #include <string.h> #include "acpi_pirq_gen.h" diff --git a/src/southbridge/intel/fsp_bd82x6x/finalize.c b/src/southbridge/intel/fsp_bd82x6x/finalize.c index 5b65fb0a0d..af2f4e1561 100644 --- a/src/southbridge/intel/fsp_bd82x6x/finalize.c +++ b/src/southbridge/intel/fsp_bd82x6x/finalize.c @@ -15,6 +15,7 @@ */ #include <arch/io.h> +#include <device/pci_ops.h> #include <console/post_codes.h> #include "pch.h" #include <spi-generic.h> diff --git a/src/southbridge/intel/fsp_i89xx/finalize.c b/src/southbridge/intel/fsp_i89xx/finalize.c index 5b65fb0a0d..af2f4e1561 100644 --- a/src/southbridge/intel/fsp_i89xx/finalize.c +++ b/src/southbridge/intel/fsp_i89xx/finalize.c @@ -15,6 +15,7 @@ */ #include <arch/io.h> +#include <device/pci_ops.h> #include <console/post_codes.h> #include "pch.h" #include <spi-generic.h> diff --git a/src/southbridge/intel/lynxpoint/finalize.c b/src/southbridge/intel/lynxpoint/finalize.c index e95872be3c..590a24513a 100644 --- a/src/southbridge/intel/lynxpoint/finalize.c +++ b/src/southbridge/intel/lynxpoint/finalize.c @@ -15,6 +15,7 @@ */ #include <arch/io.h> +#include <device/pci_ops.h> #include <console/post_codes.h> #include <spi-generic.h> #include "me.h" diff --git a/src/southbridge/intel/lynxpoint/lpc.c b/src/southbridge/intel/lynxpoint/lpc.c index 03a77d9b3e..2e3795040d 100644 --- a/src/southbridge/intel/lynxpoint/lpc.c +++ b/src/southbridge/intel/lynxpoint/lpc.c @@ -19,6 +19,7 @@ #include <device/device.h> #include <device/pci.h> #include <device/pci_ids.h> +#include <device/pci_ops.h> #include <pc80/mc146818rtc.h> #include <pc80/isa-dma.h> #include <pc80/i8259.h> diff --git a/src/southbridge/intel/lynxpoint/pcie.c b/src/southbridge/intel/lynxpoint/pcie.c index 006bec2200..73c81b484f 100644 --- a/src/southbridge/intel/lynxpoint/pcie.c +++ b/src/southbridge/intel/lynxpoint/pcie.c @@ -19,6 +19,7 @@ #include <device/pci.h> #include <device/pciexp.h> #include <device/pci_ids.h> +#include <device/pci_ops.h> #include "pch.h" #include <southbridge/intel/common/gpio.h> |