diff options
| -rw-r--r-- | src/soc/amd/stoneyridge/bootblock/bootblock.c | 3 | ||||
| -rw-r--r-- | src/soc/amd/stoneyridge/include/soc/cpu.h | 11 |
2 files changed, 13 insertions, 1 deletions
diff --git a/src/soc/amd/stoneyridge/bootblock/bootblock.c b/src/soc/amd/stoneyridge/bootblock/bootblock.c index fafaf079ce..db5c9b62b9 100644 --- a/src/soc/amd/stoneyridge/bootblock/bootblock.c +++ b/src/soc/amd/stoneyridge/bootblock/bootblock.c @@ -25,6 +25,7 @@ #include <amdblocks/agesawrapper.h> #include <amdblocks/agesawrapper_call.h> #include <soc/pci_devs.h> +#include <soc/cpu.h> #include <soc/northbridge.h> #include <soc/southbridge.h> #include <amdblocks/psp.h> @@ -61,7 +62,7 @@ static void amd_initmmio(void) * todo: AGESA currently writes variable MTRRs. Once that is * corrected, un-hardcode this MTRR. */ - mtrr = (mtrr_cap.lo & MTRR_CAP_VCNT) - 2; + mtrr = (mtrr_cap.lo & MTRR_CAP_VCNT) - SOC_EARLY_VMTRR_FLASH; set_var_mtrr(mtrr, FLASH_BASE_ADDR, CONFIG_ROM_SIZE, MTRR_TYPE_WRPROT); } diff --git a/src/soc/amd/stoneyridge/include/soc/cpu.h b/src/soc/amd/stoneyridge/include/soc/cpu.h index d2c412f4ef..bf8ed496ef 100644 --- a/src/soc/amd/stoneyridge/include/soc/cpu.h +++ b/src/soc/amd/stoneyridge/include/soc/cpu.h @@ -16,6 +16,17 @@ #ifndef __STONEYRIDGE_CPU_H__ #define __STONEYRIDGE_CPU_H__ +#include <device/device.h> + +/* + * Set a variable MTRR in bootblock and/or romstage. AGESA will use the lowest + * numbered registers. Any values defined below are subtracted from the + * highest numbered registers. + * + * todo: Revisit this once AGESA no longer programs MTRRs. + */ +#define SOC_EARLY_VMTRR_FLASH 2 + void stoney_init_cpus(struct device *dev); #endif /* __STONEYRIDGE_CPU_H__ */ |