diff options
| -rw-r--r-- | src/mainboard/google/octopus/bootblock.c | 1 | ||||
| -rw-r--r-- | src/mainboard/google/octopus/variants/baseboard/gpio.c | 7 | ||||
| -rw-r--r-- | src/mainboard/google/octopus/variants/bip/gpio.c | 7 | ||||
| -rw-r--r-- | src/mainboard/intel/glkrvp/variants/baseboard/gpio.c | 17 | ||||
| -rw-r--r-- | src/soc/intel/apollolake/lpc.c | 17 |
5 files changed, 28 insertions, 21 deletions
diff --git a/src/mainboard/google/octopus/bootblock.c b/src/mainboard/google/octopus/bootblock.c index 53e4e22dc9..6826e5db9b 100644 --- a/src/mainboard/google/octopus/bootblock.c +++ b/src/mainboard/google/octopus/bootblock.c @@ -24,6 +24,7 @@ void bootblock_mainboard_init(void) const struct pad_config *pads; size_t num; + lpc_configure_pads(); pads = variant_early_gpio_table(&num); gpio_configure_pads(pads, num); mainboard_ec_init(); diff --git a/src/mainboard/google/octopus/variants/baseboard/gpio.c b/src/mainboard/google/octopus/variants/baseboard/gpio.c index a641315f90..19dcebce88 100644 --- a/src/mainboard/google/octopus/variants/baseboard/gpio.c +++ b/src/mainboard/google/octopus/variants/baseboard/gpio.c @@ -206,7 +206,12 @@ static const struct pad_config gpio_table[] = { PAD_CFG_GPI_SCI_LOW(GPIO_144, NONE, DEEP, LEVEL),/* GPIO_144 -- PEN_EJECT_ODL(wake) */ PAD_CFG_GPI_GPIO_DRIVER(GPIO_145, NONE, DEEP),/* GPIO_145 -- PEN_EJECT_ODL(notifications) */ PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_146, NONE, DEEP, NF5, HIZCRx0, DISPUPD),/* GPIO_146 -- NC */ - PAD_CFG_GPO_IOSSTATE_IOSTERM(GPIO_154, 1, DEEP, UP_20K, HIZCRx1, DISPUPD),/* LPC_CLKRUNB */ + + /* + * GPIO_154 - LPC_CLKRUN# has a native function for LPC but not for + * eSPI. Nonetheless if we use eSPI, it should be configured as a GPIO + * and kept unconnected to allow S0ix entry. + */ /* AUDIO COMMUNITY GPIOS*/ PAD_CFG_GPO_IOSSTATE_IOSTERM(GPIO_156, 0, DEEP, NONE, HIZCRx0, DISPUPD), /* AVS_I2S0_MCLK */ diff --git a/src/mainboard/google/octopus/variants/bip/gpio.c b/src/mainboard/google/octopus/variants/bip/gpio.c index f169ac32a0..f676690468 100644 --- a/src/mainboard/google/octopus/variants/bip/gpio.c +++ b/src/mainboard/google/octopus/variants/bip/gpio.c @@ -206,7 +206,12 @@ static const struct pad_config gpio_table[] = { PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_144, NONE, DEEP, NF5, HIZCRx0, DISPUPD),/* PANEL1_VDDN */ PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_145, NONE, DEEP, NF5, HIZCRx0, DISPUPD),/* PANEL1_BKLTEN */ PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_146, NONE, DEEP, NF5, HIZCRx0, DISPUPD),/* PANEL1_BKLTCTL */ - PAD_CFG_GPO_IOSSTATE_IOSTERM(GPIO_154, 1, DEEP, UP_20K, HIZCRx1, DISPUPD),/* LPC_CLKRUNB */ + + /* + * GPIO_154 - LPC_CLKRUN# has a native function for LPC but not for + * eSPI. Nonetheless if we use eSPI, it should be configured as a GPIO + * and kept unconnected to allow S0ix entry. + */ /* AUDIO COMMUNITY GPIOS*/ PAD_CFG_GPIO_HI_Z(GPIO_156, NONE, DEEP, HIZCRx0, DISPUPD),/* AVS_I2S0_MCLK -- unused */ diff --git a/src/mainboard/intel/glkrvp/variants/baseboard/gpio.c b/src/mainboard/intel/glkrvp/variants/baseboard/gpio.c index 7ff68a4826..806f1cbf25 100644 --- a/src/mainboard/intel/glkrvp/variants/baseboard/gpio.c +++ b/src/mainboard/intel/glkrvp/variants/baseboard/gpio.c @@ -163,9 +163,9 @@ static const struct pad_config gpio_table[] = { PAD_CFG_NF_IOSSTATE(GPIO_128, DN_20K, DEEP, NF1, Tx0RxDCRx0),/*PANEL0_VDDEN*/ PAD_CFG_NF_IOSSTATE(GPIO_129, DN_20K, DEEP, NF1, Tx0RxDCRx0),/*PANEL0_BKLTEN*/ PAD_CFG_NF_IOSSTATE(GPIO_130, DN_20K, DEEP, NF1, Tx0RxDCRx0),/*PANEL0_BKLTCTL*/ - PAD_CFG_NF_IOSSTATE(GPIO_131, UP_20K, DEEP, NF1, TxDRxE ),/*HV_DDI0_HPD*/ - PAD_CFG_NF_IOSSTATE(GPIO_132, UP_20K, DEEP, NF1, TxDRxE ),/*HV_DDI1_HPD*/ - PAD_CFG_NF_IOSSTATE(GPIO_133, UP_20K, DEEP, NF1, TxDRxE ),/*HV_EDP_HPD*/ + PAD_CFG_NF_IOSSTATE(GPIO_131, UP_20K, DEEP, NF1, TxDRxE),/*HV_DDI0_HPD*/ + PAD_CFG_NF_IOSSTATE(GPIO_132, UP_20K, DEEP, NF1, TxDRxE),/*HV_DDI1_HPD*/ + PAD_CFG_NF_IOSSTATE(GPIO_133, UP_20K, DEEP, NF1, TxDRxE),/*HV_EDP_HPD*/ PAD_CFG_GPO_IOSSTATE_IOSTERM(GPIO_134, 1, DEEP, UP_20K, IGNORE, SAME),/*Slot-1 Power Enable*/ PAD_CFG_GPO_IOSSTATE_IOSTERM(GPIO_135, 1, DEEP, UP_20K, IGNORE, SAME),/*Slot-2 Power Enable*/ PAD_CFG_GPO_IOSSTATE_IOSTERM(GPIO_136, 1, DEEP, DN_20K, IGNORE, SAME),/*DGPU Power Select*/ @@ -179,17 +179,6 @@ static const struct pad_config gpio_table[] = { PAD_CFG_NF_IOSSTATE(GPIO_144, UP_20K, DEEP, NF5, HIZCRx1),/*PANEL1_VDDEN*/ PAD_CFG_NF_IOSSTATE(GPIO_145, UP_20K, DEEP, NF5, HIZCRx1),/*PANEL1_BKLTEN*/ PAD_CFG_NF_IOSSTATE(GPIO_146, UP_20K, DEEP, NF5, HIZCRx1),/*PANEL1_BKLTCTL*/ -#if !IS_ENABLED(CONFIG_SOC_ESPI) - PAD_CFG_NF(GPIO_147, UP_20K, DEEP, NF1),/*LPC_ILB_SERIRQ*/ - PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_148, NONE, DEEP, NF1, HIZCRx1, DISPUPD),/*LPC_CLKOUT0*/ - PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_149, NONE, DEEP, NF1, HIZCRx1, DISPUPD),/*LPC_CLKOUT1*/ - PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_150, UP_20K, DEEP, NF1, HIZCRx1, DISPUPD),/*LPC_AD0*/ - PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_151, UP_20K, DEEP, NF1, HIZCRx1, DISPUPD),/*LPC_AD1*/ - PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_152, UP_20K, DEEP, NF1, HIZCRx1, DISPUPD),/*LPC_AD2*/ - PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_153, UP_20K, DEEP, NF1, HIZCRx1, DISPUPD),/*LPC_AD3*/ - PAD_CFG_NF(GPIO_154, UP_20K, DEEP, NF1),/*LPC_CLKRUNB*/ - PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_155, UP_20K, DEEP, NF1, HIZCRx1, DISPUPD),/*LPC_FRAMEB*/ -#endif /* !IS_ENABLED(CONFIG_SOC_ESPI) */ PAD_CFG_GPO_IOSSTATE_IOSTERM(GPIO_157, 1, DEEP, UP_20K, IGNORE, SAME),/*WWAN_Reset/dGPS Reset*/ PAD_CFG_GPO_IOSSTATE_IOSTERM(GPIO_158, 0, DEEP, DN_20K, IGNORE, SAME),/*NFC_DFU*/ PAD_CFG_GPO_IOSSTATE_IOSTERM(GPIO_159, 1, DEEP, UP_20K, TxDRxE, ENPD),/*NFC reset*/ diff --git a/src/soc/intel/apollolake/lpc.c b/src/soc/intel/apollolake/lpc.c index 70b29b5a42..451aa736d1 100644 --- a/src/soc/intel/apollolake/lpc.c +++ b/src/soc/intel/apollolake/lpc.c @@ -47,9 +47,9 @@ static const struct pad_config lpc_gpios[] = { #if IS_ENABLED(CONFIG_SOC_INTEL_GLK) #if !IS_ENABLED(CONFIG_SOC_ESPI) PAD_CFG_NF(GPIO_147, UP_20K, DEEP, NF1), /* LPC_ILB_SERIRQ */ - PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_148, UP_20K, DEEP, NF1, HIZCRx1, + PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_148, NONE, DEEP, NF1, HIZCRx1, DISPUPD), /* LPC_CLKOUT0 */ - PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_149, UP_20K, DEEP, NF1, HIZCRx1, + PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_149, NONE, DEEP, NF1, HIZCRx1, DISPUPD), /* LPC_CLKOUT1 */ PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_150, UP_20K, DEEP, NF1, HIZCRx1, DISPUPD), /* LPC_AD0 */ @@ -59,10 +59,17 @@ static const struct pad_config lpc_gpios[] = { DISPUPD), /* LPC_AD2 */ PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_153, UP_20K, DEEP, NF1, HIZCRx1, DISPUPD), /* LPC_AD3 */ - PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_154, UP_20K, DEEP, NF1, HIZCRx1, - DISPUPD), /* LPC_CLKRUNB */ + PAD_CFG_NF(GPIO_154, UP_20K, DEEP, NF1), /* LPC_CLKRUNB */ PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_155, UP_20K, DEEP, NF1, HIZCRx1, - DISPUPD), /* LPC_FRAMEB*/ + DISPUPD), /* LPC_FRAMEB */ +#else + /* + * LPC_CLKRUNB should be in GPIO mode for eSPI. Other pin settings + * i.e. Rx path enable/disable, Tx path enable/disable, pull up + * enable/disable etc are ignored. Leaving this pin in Native mode + * will keep LPC Controller awake and prevent S0ix entry + */ + PAD_NC(GPIO_154, NONE), #endif /* !IS_ENABLED(CONFIG_SOC_ESPI) */ #else PAD_CFG_NF(LPC_ILB_SERIRQ, UP_20K, DEEP, NF1), |