diff options
| -rw-r--r-- | src/soc/intel/common/block/include/intelblocks/lpss.h | 10 | ||||
| -rw-r--r-- | src/soc/intel/common/block/lpss/lpss.c | 18 |
2 files changed, 28 insertions, 0 deletions
diff --git a/src/soc/intel/common/block/include/intelblocks/lpss.h b/src/soc/intel/common/block/include/intelblocks/lpss.h index eb38f13a71..dafe351f02 100644 --- a/src/soc/intel/common/block/include/intelblocks/lpss.h +++ b/src/soc/intel/common/block/include/intelblocks/lpss.h @@ -16,8 +16,15 @@ #ifndef SOC_INTEL_COMMON_BLOCK_LPSS_H #define SOC_INTEL_COMMON_BLOCK_LPSS_H +#include <device/device.h> #include <stdint.h> +/* D0 and D3 enable config */ +enum lpss_pwr_state { + STATE_D0 = 0, + STATE_D3 = 3 +}; + /* Gets controller out of reset */ void lpss_reset_release(uintptr_t base); @@ -30,4 +37,7 @@ void lpss_clk_update(uintptr_t base, uint32_t clk_m_val, uint32_t clk_n_val); /* Check if controller is in reset. */ bool lpss_is_controller_in_reset(uintptr_t base); +/* Set controller power state to D0 or D3*/ +void lpss_set_power_state(const struct device *dev, enum lpss_pwr_state state); + #endif /* SOC_INTEL_COMMON_BLOCK_LPSS_H */ diff --git a/src/soc/intel/common/block/lpss/lpss.c b/src/soc/intel/common/block/lpss/lpss.c index 6b6d17b106..226b4d30a8 100644 --- a/src/soc/intel/common/block/lpss/lpss.c +++ b/src/soc/intel/common/block/lpss/lpss.c @@ -14,6 +14,7 @@ */ #include <device/mmio.h> +#include <device/pci_ops.h> #include <intelblocks/lpss.h> /* Clock register */ @@ -39,6 +40,11 @@ /* DMA Software Reset Control */ #define LPSS_DMA_RST_RELEASE (1 << 2) +/* Power management control and status register */ +#define PME_CTRL_STATUS 0x84 +/* Bit 1:0 Powerstate, controls D0 and D3 state */ +#define POWER_STATE_MASK 3 + bool lpss_is_controller_in_reset(uintptr_t base) { uint8_t *addr = (void *)base; @@ -69,3 +75,15 @@ void lpss_clk_update(uintptr_t base, uint32_t clk_m_val, uint32_t clk_n_val) write32(addr, clk_sel); } + +/* Set controller power state to D0 or D3 */ +void lpss_set_power_state(const struct device *dev, enum lpss_pwr_state state) +{ +#if defined(__SIMPLE_DEVICE__) + pci_devfn_t lpss_dev = dev->path.pci.devfn; +#else + const struct device *lpss_dev = dev; +#endif + + pci_update_config8(lpss_dev, PME_CTRL_STATUS, ~POWER_STATE_MASK, state); +} |