diff options
| -rw-r--r-- | src/mainboard/amd/bimini_fam10/romstage.c | 6 |
1 files changed, 1 insertions, 5 deletions
diff --git a/src/mainboard/amd/bimini_fam10/romstage.c b/src/mainboard/amd/bimini_fam10/romstage.c index 7bd4ddd08b..e3955748b5 100644 --- a/src/mainboard/amd/bimini_fam10/romstage.c +++ b/src/mainboard/amd/bimini_fam10/romstage.c @@ -49,6 +49,7 @@ #include "southbridge/amd/rs780/early_setup.c" #include "southbridge/amd/sb800/early_setup.c" #include "northbridge/amd/amdfam10/debug.c" +#include <spd.h> static void activate_spd_rom(const struct mem_controller *ctrl) { @@ -77,11 +78,6 @@ static int spd_read_byte(u32 device, u32 address) #define RC00 0 #define RC01 1 -#define DIMM0 0x50 -#define DIMM1 0x51 -#define DIMM2 0x52 -#define DIMM3 0x53 - void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) { struct sys_info *sysinfo = (struct sys_info *)(CONFIG_DCACHE_RAM_BASE + CONFIG_DCACHE_RAM_SIZE - CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE); |