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-rw-r--r--src/mainboard/intel/tglrvp/variants/tglrvp_up3/gpio.c74
-rw-r--r--src/mainboard/intel/tglrvp/variants/tglrvp_up4/gpio.c75
2 files changed, 74 insertions, 75 deletions
diff --git a/src/mainboard/intel/tglrvp/variants/tglrvp_up3/gpio.c b/src/mainboard/intel/tglrvp/variants/tglrvp_up3/gpio.c
index 30d148a6de..b0c5bc1bd4 100644
--- a/src/mainboard/intel/tglrvp/variants/tglrvp_up3/gpio.c
+++ b/src/mainboard/intel/tglrvp/variants/tglrvp_up3/gpio.c
@@ -20,52 +20,52 @@
/* Pad configuration in ramstage*/
static const struct pad_config gpio_table[] = {
/* PCH M.2 SSD */
- PAD_CFG_GPO(GPP_B16, 1, PLTRST),
- PAD_CFG_GPO(GPP_H0, 1, PLTRST),
+ PAD_CFG_GPO(GPP_B16, 1, DEEP),
+ PAD_CFG_GPO(GPP_H0, 1, DEEP),
/* Camera */
- PAD_CFG_NF(GPP_H6, NONE, PLTRST, NF1), /* I2C3_SDA */
- PAD_CFG_NF(GPP_H7, NONE, PLTRST, NF1), /* I2C3_SCL */
- PAD_CFG_NF(GPP_B9, NONE, PLTRST, NF1), /* I2C5_SDA */
- PAD_CFG_NF(GPP_B10, NONE, PLTRST, NF1), /* I2C5_SCL */
- PAD_CFG_GPO(GPP_B23, 0, PLTRST),
- PAD_CFG_GPO(GPP_C15, 0, PLTRST),
- PAD_CFG_GPO(GPP_R6, 0, PLTRST),
- PAD_CFG_GPO(GPP_H12, 0, PLTRST),
+ PAD_CFG_NF(GPP_H6, NONE, DEEP, NF1), /* I2C3_SDA */
+ PAD_CFG_NF(GPP_H7, NONE, DEEP, NF1), /* I2C3_SCL */
+ PAD_CFG_NF(GPP_B9, NONE, DEEP, NF1), /* I2C5_SDA */
+ PAD_CFG_NF(GPP_B10, NONE, DEEP, NF1), /* I2C5_SCL */
+ PAD_CFG_GPO(GPP_B23, 0, DEEP),
+ PAD_CFG_GPO(GPP_C15, 0, DEEP),
+ PAD_CFG_GPO(GPP_R6, 0, DEEP),
+ PAD_CFG_GPO(GPP_H12, 0, DEEP),
/* Image clock: IMGCLKOUT_0, IMGCLKOUT_1 */
- PAD_CFG_NF(GPP_D4, NONE, PLTRST, NF1),
- PAD_CFG_NF(GPP_H20, NONE, PLTRST, NF1),
+ PAD_CFG_NF(GPP_D4, NONE, DEEP, NF1),
+ PAD_CFG_NF(GPP_H20, NONE, DEEP, NF1),
/* ISH UART0 RX/TX */
- PAD_CFG_NF(GPP_D13, NONE, PLTRST, NF1),
- PAD_CFG_NF(GPP_D14, NONE, PLTRST, NF1),
+ PAD_CFG_NF(GPP_D13, NONE, DEEP, NF1),
+ PAD_CFG_NF(GPP_D14, NONE, DEEP, NF1),
/* ISH I2C0 */
- PAD_CFG_NF(GPP_B5, NONE, PLTRST, NF1),
- PAD_CFG_NF(GPP_B6, NONE, PLTRST, NF1),
+ PAD_CFG_NF(GPP_B5, NONE, DEEP, NF1),
+ PAD_CFG_NF(GPP_B6, NONE, DEEP, NF1),
/* ISH GPI 0-6 */
- PAD_CFG_NF(GPP_D0, NONE, PLTRST, NF1),
- PAD_CFG_NF(GPP_D1, NONE, PLTRST, NF1),
- PAD_CFG_NF(GPP_D2, NONE, PLTRST, NF1),
- PAD_CFG_NF(GPP_D3, NONE, PLTRST, NF1),
- PAD_CFG_NF(GPP_D17, NONE, PLTRST, NF1),
- PAD_CFG_NF(GPP_D18, NONE, PLTRST, NF1),
- PAD_CFG_NF(GPP_E15, NONE, PLTRST, NF1),
- PAD_CFG_NF(GPP_E16, NONE, PLTRST, NF1),
-
- /*Audio */
+ PAD_CFG_NF(GPP_D0, NONE, DEEP, NF1),
+ PAD_CFG_NF(GPP_D1, NONE, DEEP, NF1),
+ PAD_CFG_NF(GPP_D2, NONE, DEEP, NF1),
+ PAD_CFG_NF(GPP_D3, NONE, DEEP, NF1),
+ PAD_CFG_NF(GPP_D17, NONE, DEEP, NF1),
+ PAD_CFG_NF(GPP_D18, NONE, DEEP, NF1),
+ PAD_CFG_NF(GPP_E15, NONE, DEEP, NF1),
+ PAD_CFG_NF(GPP_E16, NONE, DEEP, NF1),
+
+ /* Audio */
PAD_CFG_NF(GPP_C16, NONE, DEEP, NF1), /* I2C0_SDA */
PAD_CFG_NF(GPP_C17, NONE, DEEP, NF1), /* I2C0_SCL */
- PAD_CFG_GPO(GPP_C5, 1, PLTRST),
- PAD_CFG_GPI_APIC(GPP_C12, NONE, PLTRST, EDGE_BOTH, INVERT), /* AUDIO JACK IRQ */
+ PAD_CFG_GPO(GPP_C5, 1, DEEP),
+ PAD_CFG_GPI_APIC(GPP_C12, NONE, DEEP, EDGE_BOTH, INVERT), /* AUDIO JACK IRQ */
};
/* Early pad configuration in bootblock */
static const struct pad_config early_gpio_table[] = {
- /*Audio */
+ /* Audio */
PAD_CFG_NF(GPP_R0, NONE, DEEP, NF2), /* I2S0_HP_SCLK */
PAD_CFG_NF(GPP_R1, NONE, DEEP, NF2), /* I2S0_HP_SFRM */
PAD_CFG_NF(GPP_R2, DN_20K, DEEP, NF2), /* I2S0_HP_TX */
@@ -87,14 +87,14 @@ static const struct pad_config early_gpio_table[] = {
PAD_CFG_NF(GPP_S7, NONE, DEEP, NF2), /* DMIC0_DATA */
/* DP */
- PAD_CFG_NF(GPP_L_BKLTEN, NONE, PLTRST, NF1), /* L_BKLTEN */
- PAD_CFG_NF(GPP_L_BKLTCTL, NONE, PLTRST, NF1), /* L_BKLTCTL */
- PAD_CFG_NF(GPP_L_VDDEN, NONE, PLTRST, NF1), /* L_VDDEN */
- PAD_CFG_NF(GPP_E14, NONE, PLTRST, NF1), /* HPD_A */
- PAD_CFG_NF(GPP_A18, NONE, PLTRST, NF1), /* HPD_B */
- PAD_CFG_NF(GPP_A19, NONE, PLTRST, NF1), /* HPD_1 */
- PAD_CFG_NF(GPP_E18, NONE, PLTRST, NF1), /* DDP_1_CTRCLK */
- PAD_CFG_NF(GPP_E19, NONE, PLTRST, NF1), /* DDP_1_CTRDATA */
+ PAD_CFG_NF(GPP_L_BKLTEN, NONE, DEEP, NF1), /* L_BKLTEN */
+ PAD_CFG_NF(GPP_L_BKLTCTL, NONE, DEEP, NF1), /* L_BKLTCTL */
+ PAD_CFG_NF(GPP_L_VDDEN, NONE, DEEP, NF1), /* L_VDDEN */
+ PAD_CFG_NF(GPP_E14, NONE, DEEP, NF1), /* HPD_A */
+ PAD_CFG_NF(GPP_A18, NONE, DEEP, NF1), /* HPD_B */
+ PAD_CFG_NF(GPP_A19, NONE, DEEP, NF1), /* HPD_1 */
+ PAD_CFG_NF(GPP_E18, NONE, DEEP, NF1), /* DDP_1_CTRCLK */
+ PAD_CFG_NF(GPP_E19, NONE, DEEP, NF1), /* DDP_1_CTRDATA */
};
const struct pad_config *variant_gpio_table(size_t *num)
diff --git a/src/mainboard/intel/tglrvp/variants/tglrvp_up4/gpio.c b/src/mainboard/intel/tglrvp/variants/tglrvp_up4/gpio.c
index 2f952d2188..c00f6d1137 100644
--- a/src/mainboard/intel/tglrvp/variants/tglrvp_up4/gpio.c
+++ b/src/mainboard/intel/tglrvp/variants/tglrvp_up4/gpio.c
@@ -20,53 +20,52 @@
/* Pad configuration in ramstage*/
static const struct pad_config gpio_table[] = {
/* PCH M.2 SSD */
- PAD_CFG_GPO(GPP_B16, 1, PLTRST),
- PAD_CFG_GPO(GPP_H0, 1, PLTRST),
+ PAD_CFG_GPO(GPP_B16, 1, DEEP),
+ PAD_CFG_GPO(GPP_H0, 1, DEEP),
/* Camera */
- PAD_CFG_NF(GPP_H6, NONE, PLTRST, NF1), /* I2C3_SDA */
- PAD_CFG_NF(GPP_H7, NONE, PLTRST, NF1), /* I2C3_SCL */
- PAD_CFG_NF(GPP_B9, NONE, PLTRST, NF1), /* I2C5_SDA */
- PAD_CFG_NF(GPP_B10, NONE, PLTRST, NF1), /* I2C5_SCL */
- PAD_CFG_GPO(GPP_B23, 0, PLTRST),
- PAD_CFG_GPO(GPP_C15, 0, PLTRST),
- PAD_CFG_GPO(GPP_E22, 0, PLTRST),
- PAD_CFG_GPO(GPP_H12, 0, PLTRST),
+ PAD_CFG_NF(GPP_H6, NONE, DEEP, NF1), /* I2C3_SDA */
+ PAD_CFG_NF(GPP_H7, NONE, DEEP, NF1), /* I2C3_SCL */
+ PAD_CFG_NF(GPP_B9, NONE, DEEP, NF1), /* I2C5_SDA */
+ PAD_CFG_NF(GPP_B10, NONE, DEEP, NF1), /* I2C5_SCL */
+ PAD_CFG_GPO(GPP_B23, 0, DEEP),
+ PAD_CFG_GPO(GPP_C15, 0, DEEP),
+ PAD_CFG_GPO(GPP_E22, 0, DEEP),
+ PAD_CFG_GPO(GPP_H12, 0, DEEP),
/* Image clock: IMGCLKOUT_0, IMGCLKOUT_1 */
- PAD_CFG_NF(GPP_D4, NONE, PLTRST, NF1),
- PAD_CFG_NF(GPP_H20, NONE, PLTRST, NF1),
+ PAD_CFG_NF(GPP_D4, NONE, DEEP, NF1),
+ PAD_CFG_NF(GPP_H20, NONE, DEEP, NF1),
/* ISH UART0 RX/TX */
- PAD_CFG_NF(GPP_D13, NONE, PLTRST, NF1),
- PAD_CFG_NF(GPP_D14, NONE, PLTRST, NF1),
+ PAD_CFG_NF(GPP_D13, NONE, DEEP, NF1),
+ PAD_CFG_NF(GPP_D14, NONE, DEEP, NF1),
/* ISH I2C0 */
- PAD_CFG_NF(GPP_B5, NONE, PLTRST, NF1),
- PAD_CFG_NF(GPP_B6, NONE, PLTRST, NF1),
+ PAD_CFG_NF(GPP_B5, NONE, DEEP, NF1),
+ PAD_CFG_NF(GPP_B6, NONE, DEEP, NF1),
/* ISH GPI 0-6 */
- PAD_CFG_NF(GPP_D0, NONE, PLTRST, NF1),
- PAD_CFG_NF(GPP_D1, NONE, PLTRST, NF1),
- PAD_CFG_NF(GPP_D2, NONE, PLTRST, NF1),
- PAD_CFG_NF(GPP_D3, NONE, PLTRST, NF1),
- PAD_CFG_NF(GPP_D17, NONE, PLTRST, NF1),
- PAD_CFG_NF(GPP_D18, NONE, PLTRST, NF1),
- PAD_CFG_NF(GPP_E15, NONE, PLTRST, NF1),
- PAD_CFG_NF(GPP_E16, NONE, PLTRST, NF1),
-
- /*Audio */
+ PAD_CFG_NF(GPP_D0, NONE, DEEP, NF1),
+ PAD_CFG_NF(GPP_D1, NONE, DEEP, NF1),
+ PAD_CFG_NF(GPP_D2, NONE, DEEP, NF1),
+ PAD_CFG_NF(GPP_D3, NONE, DEEP, NF1),
+ PAD_CFG_NF(GPP_D17, NONE, DEEP, NF1),
+ PAD_CFG_NF(GPP_D18, NONE, DEEP, NF1),
+ PAD_CFG_NF(GPP_E15, NONE, DEEP, NF1),
+ PAD_CFG_NF(GPP_E16, NONE, DEEP, NF1),
+
+ /* Audio */
PAD_CFG_NF(GPP_C16, NONE, DEEP, NF1), /* I2C0_SDA */
PAD_CFG_NF(GPP_C17, NONE, DEEP, NF1), /* I2C0_SCL */
- PAD_CFG_GPO(GPP_C5, 1, PLTRST),
- PAD_CFG_GPI_APIC(GPP_C12, NONE, PLTRST, EDGE_BOTH, INVERT), /* AUDIO JACK IRQ */
+ PAD_CFG_GPO(GPP_C5, 1, DEEP),
+ PAD_CFG_GPI_APIC(GPP_C12, NONE, DEEP, EDGE_BOTH, INVERT), /* AUDIO JACK IRQ */
};
/* Early pad configuration in bootblock */
static const struct pad_config early_gpio_table[] = {
-
- /*Audio */
+ /* Audio */
PAD_CFG_NF(GPP_R0, NONE, DEEP, NF2), /* I2S0_HP_SCLK */
PAD_CFG_NF(GPP_R1, NONE, DEEP, NF2), /* I2S0_HP_SFRM */
PAD_CFG_NF(GPP_R2, DN_20K, DEEP, NF2), /* I2S0_HP_TX */
@@ -88,14 +87,14 @@ static const struct pad_config early_gpio_table[] = {
PAD_CFG_NF(GPP_S7, NONE, DEEP, NF2), /* DMIC0_DATA */
/* DP */
- PAD_CFG_NF(GPP_L_BKLTEN, NONE, PLTRST, NF1), /* L_BKLTEN */
- PAD_CFG_NF(GPP_L_BKLTCTL, NONE, PLTRST, NF1), /* L_BKLTCTL */
- PAD_CFG_NF(GPP_L_VDDEN, NONE, PLTRST, NF1), /* L_VDDEN */
- PAD_CFG_NF(GPP_E14, NONE, PLTRST, NF1), /* HPD_A */
- PAD_CFG_NF(GPP_A18, NONE, PLTRST, NF1), /* HPD_B */
- PAD_CFG_NF(GPP_A19, NONE, PLTRST, NF1), /* HPD_1 */
- PAD_CFG_NF(GPP_E18, NONE, PLTRST, NF1), /* DDP_1_CTRCLK */
- PAD_CFG_NF(GPP_E19, NONE, PLTRST, NF1), /* DDP_1_CTRDATA */
+ PAD_CFG_NF(GPP_L_BKLTEN, NONE, DEEP, NF1), /* L_BKLTEN */
+ PAD_CFG_NF(GPP_L_BKLTCTL, NONE, DEEP, NF1), /* L_BKLTCTL */
+ PAD_CFG_NF(GPP_L_VDDEN, NONE, DEEP, NF1), /* L_VDDEN */
+ PAD_CFG_NF(GPP_E14, NONE, DEEP, NF1), /* HPD_A */
+ PAD_CFG_NF(GPP_A18, NONE, DEEP, NF1), /* HPD_B */
+ PAD_CFG_NF(GPP_A19, NONE, DEEP, NF1), /* HPD_1 */
+ PAD_CFG_NF(GPP_E18, NONE, DEEP, NF1), /* DDP_1_CTRCLK */
+ PAD_CFG_NF(GPP_E19, NONE, DEEP, NF1), /* DDP_1_CTRDATA */
};
const struct pad_config *variant_gpio_table(size_t *num)
generated by cgit v1.2.3 (git 2.39.1) at 2024-07-03 01:36:06 +0000