diff options
| -rw-r--r-- | src/mainboard/google/hatch/variants/baseboard/devicetree.cb | 4 |
1 files changed, 3 insertions, 1 deletions
diff --git a/src/mainboard/google/hatch/variants/baseboard/devicetree.cb b/src/mainboard/google/hatch/variants/baseboard/devicetree.cb index 1123d53734..61b712dbec 100644 --- a/src/mainboard/google/hatch/variants/baseboard/devicetree.cb +++ b/src/mainboard/google/hatch/variants/baseboard/devicetree.cb @@ -99,7 +99,9 @@ chip soc/intel/cannonlake register "gpio_pm[COMM_1]" = "MISCCFG_ENABLE_GPIO_PM_CONFIG" register "gpio_pm[COMM_2]" = "MISCCFG_ENABLE_GPIO_PM_CONFIG" register "gpio_pm[COMM_3]" = "MISCCFG_ENABLE_GPIO_PM_CONFIG" - register "gpio_pm[COMM_4]" = "MISCCFG_GPSIDEDPCGEN | MISCCFG_GPRTCDLCGEN | MISCCFG_GSXSLCGEN | MISCCFG_GPDPCGEN | MISCCFG_GPDLCGEN" + # Disable clock gating on this community so that cr50's short irq + # pulses won't be missed. + register "gpio_pm[COMM_4]" = "0" device cpu_cluster 0 on device lapic 0 on end |