diff options
| -rw-r--r-- | src/northbridge/intel/i945/early_init.c | 5 | ||||
| -rw-r--r-- | src/northbridge/intel/pineview/early_init.c | 8 | ||||
| -rw-r--r-- | src/southbridge/intel/i82801gx/bootblock_gcc.c | 4 | ||||
| -rw-r--r-- | src/southbridge/intel/i82801gx/early_init.c | 12 | ||||
| -rw-r--r-- | src/southbridge/intel/i82801gx/i82801gx.h | 1 |
5 files changed, 17 insertions, 13 deletions
diff --git a/src/northbridge/intel/i945/early_init.c b/src/northbridge/intel/i945/early_init.c index ee10fdccb6..a5bfe6f6a9 100644 --- a/src/northbridge/intel/i945/early_init.c +++ b/src/northbridge/intel/i945/early_init.c @@ -159,11 +159,8 @@ static void i945_setup_bars(void) /* Setting up Southbridge. In the northbridge code. */ printk(BIOS_DEBUG, "Setting up static southbridge registers..."); - pci_write_config32(PCI_DEV(0, 0x1f, 0), PMBASE, DEFAULT_PMBASE | 1); - pci_write_config8(PCI_DEV(0, 0x1f, 0), ACPI_CNTL, ACPI_EN); + i82801gx_setup_bars(); - pci_write_config32(PCI_DEV(0, 0x1f, 0), GPIOBASE, DEFAULT_GPIOBASE | 1); - pci_write_config8(PCI_DEV(0, 0x1f, 0), GPIO_CNTL, GPIO_EN); setup_pch_gpios(&mainboard_gpio_map); printk(BIOS_DEBUG, " done.\n"); diff --git a/src/northbridge/intel/pineview/early_init.c b/src/northbridge/intel/pineview/early_init.c index 1638f0e15a..3a9df510b7 100644 --- a/src/northbridge/intel/pineview/early_init.c +++ b/src/northbridge/intel/pineview/early_init.c @@ -158,12 +158,8 @@ static void pineview_setup_bars(void) { /* Setting up Southbridge. In the northbridge code. */ printk(BIOS_DEBUG, "Setting up static southbridge registers..."); - pci_write_config32(LPC, RCBA, (uintptr_t)DEFAULT_RCBA | 1); - pci_write_config32(LPC, PMBASE, DEFAULT_PMBASE | 1); - pci_write_config8(LPC, 0x44 /* ACPI_CNTL */, 0x80); /* Enable ACPI */ - pci_write_config32(LPC, GPIOBASE, DEFAULT_GPIOBASE | 1); - pci_write_config8(LPC, 0x4c /* GC */, 0x10); /* Enable GPIOs */ - pci_write_config32(LPC, 0x88, 0x007c0291); + + i82801gx_setup_bars(); pci_write_config32(PCI_DEV(0, 0x1e, 0), 0x1b, 0x20); printk(BIOS_DEBUG, " done.\n"); diff --git a/src/southbridge/intel/i82801gx/bootblock_gcc.c b/src/southbridge/intel/i82801gx/bootblock_gcc.c index 063a461e43..4c464ff920 100644 --- a/src/southbridge/intel/i82801gx/bootblock_gcc.c +++ b/src/southbridge/intel/i82801gx/bootblock_gcc.c @@ -32,9 +32,7 @@ void bootblock_early_southbridge_init(void) { enable_spi_prefetch(); - /* Enable RCBA */ - pci_devfn_t lpc_dev = PCI_DEV(0, 0x1f, 0); - pci_write_config32(lpc_dev, RCBA, (uintptr_t)DEFAULT_RCBA | 1); + i82801gx_setup_bars(); /* Enable upper 128bytes of CMOS */ RCBA32(0x3400) = (1 << 2); diff --git a/src/southbridge/intel/i82801gx/early_init.c b/src/southbridge/intel/i82801gx/early_init.c index 533aaefe14..7f5f442333 100644 --- a/src/southbridge/intel/i82801gx/early_init.c +++ b/src/southbridge/intel/i82801gx/early_init.c @@ -11,6 +11,7 @@ * GNU General Public License for more details. */ +#include <stdint.h> #include <device/pci_ops.h> #include "i82801gx.h" #include "chip.h" @@ -50,3 +51,14 @@ void i82801gx_lpc_setup(void) pci_write_config32(d31f0, GEN3_DEC, config->gen3_dec); pci_write_config32(d31f0, GEN4_DEC, config->gen4_dec); } + +void i82801gx_setup_bars(void) +{ + const pci_devfn_t d31f0 = PCI_DEV(0, 0x1f, 0); + pci_write_config32(d31f0, RCBA, (uint32_t)DEFAULT_RCBA | 1); + pci_write_config32(d31f0, PMBASE, DEFAULT_PMBASE | 1); + pci_write_config8(d31f0, ACPI_CNTL, ACPI_EN); + + pci_write_config32(d31f0, GPIOBASE, DEFAULT_GPIOBASE | 1); + pci_write_config8(d31f0, GPIO_CNTL, GPIO_EN); +} diff --git a/src/southbridge/intel/i82801gx/i82801gx.h b/src/southbridge/intel/i82801gx/i82801gx.h index 259fb49f54..9eea262997 100644 --- a/src/southbridge/intel/i82801gx/i82801gx.h +++ b/src/southbridge/intel/i82801gx/i82801gx.h @@ -41,6 +41,7 @@ void i82801gx_enable(struct device *dev); void enable_smbus(void); void i82801gx_lpc_setup(void); +void i82801gx_setup_bars(void); #if ENV_ROMSTAGE int smbus_read_byte(unsigned int device, unsigned int address); |