diff options
| -rw-r--r-- | src/soc/intel/apollolake/chip.c | 3 | ||||
| -rw-r--r-- | src/soc/intel/apollolake/cpu.c | 37 | ||||
| -rw-r--r-- | src/soc/intel/apollolake/include/soc/cpu.h | 3 |
3 files changed, 11 insertions, 32 deletions
diff --git a/src/soc/intel/apollolake/chip.c b/src/soc/intel/apollolake/chip.c index ef29a0311f..cd7fa62b1f 100644 --- a/src/soc/intel/apollolake/chip.c +++ b/src/soc/intel/apollolake/chip.c @@ -38,6 +38,7 @@ #include <soc/nvs.h> #include <soc/pci_devs.h> #include <spi-generic.h> +#include <soc/cpu.h> #include <soc/pm.h> #include <soc/p2sb.h> #include <soc/systemagent.h> @@ -149,7 +150,7 @@ static struct device_operations cpu_bus_ops = { .read_resources = DEVICE_NOOP, .set_resources = DEVICE_NOOP, .enable_resources = DEVICE_NOOP, - .init = DEVICE_NOOP, + .init = apollolake_init_cpus, .scan_bus = NULL, .acpi_fill_ssdt_generator = generate_cpu_entries, }; diff --git a/src/soc/intel/apollolake/cpu.c b/src/soc/intel/apollolake/cpu.c index ec202e4e29..43f9b8381f 100644 --- a/src/soc/intel/apollolake/cpu.c +++ b/src/soc/intel/apollolake/cpu.c @@ -16,8 +16,6 @@ * GNU General Public License for more details. */ -#include <assert.h> -#include <bootstate.h> #include <console/console.h> #include <cpu/cpu.h> #include <cpu/x86/cache.h> @@ -27,12 +25,10 @@ #include <cpu/x86/mtrr.h> #include <device/device.h> #include <device/pci.h> -#include <fsp/api.h> #include <intelblocks/cpulib.h> #include <intelblocks/fast_spi.h> #include <intelblocks/msr.h> #include <reg_script.h> -#include <romstage_handoff.h> #include <soc/cpu.h> #include <soc/iomap.h> #include <soc/pm.h> @@ -109,17 +105,14 @@ static void read_cpu_topology(unsigned int *num_phys, unsigned int *num_virt) /* * Do essential initialization tasks before APs can be fired up - * - * Skip Pre MP init MTRR programming, as MTRRs are mirrored from BSP, - * that are set prior to ramstage. - * Real MTRRs programming are being done after resource allocation. - * - * Do, FSP loading before MP Init to ensure that the FSP cmponent stored in - * external stage cache in TSEG does not flush off due to SMM relocation - * during MP Init stage. + * 1. Prevent race condition in MTRR solution. Enable MTRRs on the BSP. This + * creates the MTRR solution that the APs will use. Otherwise APs will try to + * apply the incomplete solution as the BSP is calculating it. */ static void pre_mp_init(void) { - fsps_load(romstage_handoff_is_resume()); + x86_setup_mtrrs_with_detect(); + x86_mtrr_check(); } /* Find CPU topology */ @@ -201,32 +194,14 @@ static const struct mp_ops mp_ops = { .post_mp_init = southbridge_smm_enable_smi, }; -static void soc_init_cpus(void *unused) +void apollolake_init_cpus(struct device *dev) { - device_t dev = dev_find_path(NULL, DEVICE_PATH_CPU_CLUSTER); - assert(dev != NULL); - /* Clear for take-off */ if (mp_init_with_smm(dev->link_list, &mp_ops) < 0) printk(BIOS_ERR, "MP initialization failure.\n"); -} - -/* Ensure to re-program all MTRRs based on DRAM resource settings */ -static void soc_post_cpus_init(void *unused) -{ - if (mp_run_on_all_cpus(&x86_setup_mtrrs_with_detect, 1000) < 0) - printk(BIOS_ERR, "MTRR programming failure\n"); /* Temporarily cache the memory-mapped boot media. */ if (IS_ENABLED(CONFIG_BOOT_DEVICE_MEMORY_MAPPED) && IS_ENABLED(CONFIG_BOOT_DEVICE_SPI_FLASH)) fast_spi_cache_bios_region(); - - x86_mtrr_check(); } - -/* - * Do CPU MP Init before FSP Silicon Init - */ -BOOT_STATE_INIT_ENTRY(BS_DEV_INIT_CHIPS, BS_ON_ENTRY, soc_init_cpus, NULL); -BOOT_STATE_INIT_ENTRY(BS_DEV_INIT, BS_ON_EXIT, soc_post_cpus_init, NULL); diff --git a/src/soc/intel/apollolake/include/soc/cpu.h b/src/soc/intel/apollolake/include/soc/cpu.h index 0e73d115f4..386ac52d2c 100644 --- a/src/soc/intel/apollolake/include/soc/cpu.h +++ b/src/soc/intel/apollolake/include/soc/cpu.h @@ -24,4 +24,7 @@ /* Common Timer Copy (CTC) frequency - 19.2MHz. */ #define CTC_FREQ 19200000 +struct device; +void apollolake_init_cpus(struct device *dev); + #endif /* _SOC_APOLLOLAKE_CPU_H_ */ |