diff options
| -rw-r--r-- | src/soc/intel/braswell/include/soc/gpio.h | 2 | ||||
| -rw-r--r-- | src/soc/intel/braswell/smihandler.c | 6 |
2 files changed, 8 insertions, 0 deletions
diff --git a/src/soc/intel/braswell/include/soc/gpio.h b/src/soc/intel/braswell/include/soc/gpio.h index 5dda732ea0..3cc5cf0fcf 100644 --- a/src/soc/intel/braswell/include/soc/gpio.h +++ b/src/soc/intel/braswell/include/soc/gpio.h @@ -110,6 +110,8 @@ #define MMC1_D7_MMIO_OFFSET GPIO_OFFSET(68) #define HV_DDI2_DDC_SDA_MMIO_OFFSET GPIO_OFFSET(62) #define HV_DDI2_DDC_SCL_MMIO_OFFSET GPIO_OFFSET(67) +#define CFIO_139_MMIO_OFFSET GPIO_OFFSET(64) +#define CFIO_140_MMIO_OFFSET GPIO_OFFSET(67) /* GPIO Security registers offset */ #define GPIO_READ_ACCESS_POLICY_REG 0x0000 diff --git a/src/soc/intel/braswell/smihandler.c b/src/soc/intel/braswell/smihandler.c index eb8ee63ff1..576e1182c2 100644 --- a/src/soc/intel/braswell/smihandler.c +++ b/src/soc/intel/braswell/smihandler.c @@ -127,6 +127,12 @@ static void tristate_gpios(uint32_t val) HV_DDI2_DDC_SDA_MMIO_OFFSET, val); write32((void *)COMMUNITY_GPNORTH_BASE + HV_DDI2_DDC_SCL_MMIO_OFFSET, val); + + /* Tri-state CFIO 139 and 140 */ + write32((void *)COMMUNITY_GPSOUTHWEST_BASE + + CFIO_139_MMIO_OFFSET, val); + write32((void *)COMMUNITY_GPSOUTHWEST_BASE + + CFIO_140_MMIO_OFFSET, val); } |