diff options
| -rw-r--r-- | src/boot/hardwaremain.c | 21 | ||||
| -rw-r--r-- | src/config/Options.lb | 6 | ||||
| -rw-r--r-- | src/cpu/amd/car/clear_init_ram.c | 3 | ||||
| -rw-r--r-- | src/cpu/x86/lapic/lapic_cpu_init.c | 17 |
4 files changed, 44 insertions, 3 deletions
diff --git a/src/boot/hardwaremain.c b/src/boot/hardwaremain.c index 74f3dfcd97..9a3adf7c5d 100644 --- a/src/boot/hardwaremain.c +++ b/src/boot/hardwaremain.c @@ -37,6 +37,7 @@ it with the version available from LANL. #include <part/init_timer.h> #include <boot/elf.h> #include <romfs.h> +#include <arch/acpi.h> /** * @brief Main function of the DRAM part of coreboot. @@ -47,9 +48,11 @@ it with the version available from LANL. * Device Enumeration: * In the dev_enumerate() phase, */ + void hardwaremain(int boot_complete) { struct lb_memory *lb_mem; + void *wake_vec; post_code(0x80); @@ -84,11 +87,27 @@ void hardwaremain(int boot_complete) dev_initialize(); post_code(0x89); +#if HAVE_ACPI_RESUME == 1 + +#if MEM_TRAIN_SEQ != 0 + #error "So far it works on AMD and MEM_TRAIN_SEQ == 0" +#endif + +#if _RAMBASE < 0x1F00000 + #error "For ACPI RESUME you need to have _RAMBASE at least 31MB" + #error "Chipset support (S3_NVRAM_EARLY and ACPI_IS_WAKEUP_EARLY functions and memory ctrl)" + #error "And coreboot memory reserved in mainboard.c" +#endif + /* if we happen to be resuming find wakeup vector and jump to OS */ + wake_vec = acpi_find_wakeup_vector(); + if (wake_vec) + acpi_jump_to_wakeup(wake_vec); +#endif + /* Now that we have collected all of our information * write our configuration tables. */ lb_mem = write_tables(); - #if CONFIG_ROMFS == 1 # if USE_FALLBACK_IMAGE == 1 void (*pl)(void) = romfs_load_payload(lb_mem, "fallback/payload"); diff --git a/src/config/Options.lb b/src/config/Options.lb index 0acf8a491f..9739b6d909 100644 --- a/src/config/Options.lb +++ b/src/config/Options.lb @@ -927,6 +927,12 @@ define HAVE_ACPI_TABLES comment "Define to build ACPI tables" end +define HAVE_ACPI_RESUME + default 0 + export always + comment "Define to build ACPI with resume support" +end + define ACPI_SSDTX_NUM default 0 export always diff --git a/src/cpu/amd/car/clear_init_ram.c b/src/cpu/amd/car/clear_init_ram.c index ff05f0d439..293912175f 100644 --- a/src/cpu/amd/car/clear_init_ram.c +++ b/src/cpu/amd/car/clear_init_ram.c @@ -6,8 +6,7 @@ static void __attribute__((noinline)) clear_init_ram(void) // gcc 3.4.5 will inline the copy_and_run and clear_init_ram in post_cache_as_ram // will reuse %edi as 0 from clear_memory for copy_and_run part, actually it is increased already // so noline clear_init_ram - clear_memory(0, ((CONFIG_LB_MEM_TOPK<<10) - DCACHE_RAM_SIZE)); - + clear_memory( _RAMBASE, (CONFIG_LB_MEM_TOPK << 10) - _RAMBASE - DCACHE_RAM_SIZE); } /* be warned, this file will be used by core other than core 0/node 0 or core0/node0 when cpu_reset*/ diff --git a/src/cpu/x86/lapic/lapic_cpu_init.c b/src/cpu/x86/lapic/lapic_cpu_init.c index 1ec13845f3..1562114b39 100644 --- a/src/cpu/x86/lapic/lapic_cpu_init.c +++ b/src/cpu/x86/lapic/lapic_cpu_init.c @@ -31,6 +31,12 @@ static unsigned long get_valid_start_eip(unsigned long orig_start_eip) } #endif +#if HAVE_ACPI_RESUME == 1 +char *lowmem_backup; +char *lowmem_backup_ptr; +int lowmem_backup_size; +#endif + static void copy_secondary_start_to_1m_below(void) { #if _RAMBASE >= 0x100000 @@ -45,6 +51,17 @@ static void copy_secondary_start_to_1m_below(void) start_eip = get_valid_start_eip((unsigned long)_secondary_start); code_size = (unsigned long)_secondary_start_end - (unsigned long)_secondary_start; +#if HAVE_ACPI_RESUME == 1 + /* need to save it for RAM resume */ + lowmem_backup_size = code_size; + lowmem_backup = malloc(code_size); + lowmem_backup_ptr = (unsigned char *)start_eip; + + if (lowmem_backup == NULL) + die("Out of backup memory\n"); + + memcpy(lowmem_backup, lowmem_backup_ptr, lowmem_backup_size); +#endif /* copy the _secondary_start to the ram below 1M*/ memcpy((unsigned char *)start_eip, (unsigned char *)_secondary_start, code_size); |