diff options
-rw-r--r-- | src/cpu/amd/microcode/Config.lb | 1 | ||||
-rw-r--r-- | src/cpu/amd/microcode/microcode.c | 136 | ||||
-rw-r--r-- | src/cpu/amd/model_fxx/Config.lb | 1 | ||||
-rw-r--r-- | src/cpu/amd/model_fxx/model_fxx_init.c | 102 |
4 files changed, 240 insertions, 0 deletions
diff --git a/src/cpu/amd/microcode/Config.lb b/src/cpu/amd/microcode/Config.lb new file mode 100644 index 0000000000..f19d210a58 --- /dev/null +++ b/src/cpu/amd/microcode/Config.lb @@ -0,0 +1 @@ +object microcode.o
\ No newline at end of file diff --git a/src/cpu/amd/microcode/microcode.c b/src/cpu/amd/microcode/microcode.c new file mode 100644 index 0000000000..c05268e845 --- /dev/null +++ b/src/cpu/amd/microcode/microcode.c @@ -0,0 +1,136 @@ +/*============================================================================ +Copyright 2005 ADVANCED MICRO DEVICES, INC. All Rights Reserved. +This software and any related documentation (the "Materials") are the +confidential proprietary information of AMD. Unless otherwise provided in a +software agreement specifically licensing the Materials, the Materials are +provided in confidence and may not be distributed, modified, or reproduced in +whole or in part by any means. +LIMITATION OF LIABILITY: THE MATERIALS ARE PROVIDED "AS IS" WITHOUT ANY +EXPRESS OR IMPLIED WARRANTY OF ANY KIND, INCLUDING BUT NOT LIMITED TO +WARRANTIES OF MERCHANTABILITY, NONINFRINGEMENT, TITLE, FITNESS FOR ANY +PARTICULAR PURPOSE, OR WARRANTIES ARISING FROM CONDUCT, COURSE OF DEALING, OR +USAGE OF TRADE. IN NO EVENT SHALL AMD OR ITS LICENSORS BE LIABLE FOR ANY +DAMAGES WHATSOEVER (INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF PROFITS, +BUSINESS INTERRUPTION, OR LOSS OF INFORMATION) ARISING OUT OF THE USE OF OR +INABILITY TO USE THE MATERIALS, EVEN IF AMD HAS BEEN ADVISED OF THE +POSSIBILITY OF SUCH DAMAGES. BECAUSE SOME JURISDICTIONS PROHIBIT THE EXCLUSION +OR LIMITATION OF LIABILITY FOR CONSEQUENTIAL OR INCIDENTAL DAMAGES, THE ABOVE +LIMITATION MAY NOT APPLY TO YOU. +AMD does not assume any responsibility for any errors which may appear in the +Materials nor any responsibility to support or update the Materials. AMD +retains the right to modify the Materials at any time, without notice, and is +not obligated to provide such modified Materials to you. +NO SUPPORT OBLIGATION: AMD is not obligated to furnish, support, or make any +further information, software, technical information, know-how, or show-how +available to you. +U.S. GOVERNMENT RESTRICTED RIGHTS: The Materials are provided with "RESTRICTED +RIGHTS." Use, duplication, or disclosure by the Government is subject to the +restrictions as set forth in FAR 52.227-14 and DFAR 252.227-7013, et seq., or +its successor. Use of the Materials by the Government constitutes +acknowledgement of AMD's proprietary rights in them. +============================================================================*/ +//@DOC +// microcode.c +/* +$1.0$ +*/ +// Description: microcode patch support for k8 +// by yhlu +// +//============================================================================ +#include <stdint.h> +#include <console/console.h> +#include <cpu/cpu.h> +#include <cpu/x86/msr.h> +#include <cpu/amd/microcode.h> +#include <cpu/x86/cache.h> + +struct microcode { + uint32_t date_code; + uint32_t patch_id; + + uint16_t m_patch_data_id; + uint8_t m_patch_data_len; + uint8_t init_flag; + + uint32_t m_patch_data_cksum; + + uint32_t nb_dev_id; + uint32_t ht_io_hub_dev_id; + + uint16_t processor_rev_id; + uint8_t ht_io_hub_rev_id; + uint8_t nb_rev_id; + + uint8_t bios_api_rev; + uint8_t resv1[3]; + + uint32_t match_reg[8]; + + uint8_t m_patch_data[896]; + uint8_t resv2[896]; + + uint8_t x86_code_present; + uint8_t x86_code_entry[191]; +}; + +static int need_apply_patch(struct microcode *m, unsigned equivalent_processor_rev_id) +{ + + if (m->processor_rev_id != equivalent_processor_rev_id) return 0; + + if (m->nb_dev_id) { + //look at the device id, if not found return; + //if(m->nb_rev_id != installed_nb_rev_id) return 0; + } + + if (m->ht_io_hub_dev_id) { + //look at the device id, if not found return; + //if(m->ht_io_hub_rev_id != installed_ht_io_bub_rev_id) return 0; + } + + if (m->x86_code_present) { + //if(!x86_code_execute()) return 0; + } + + return 1; +} + + +void amd_update_microcode(void *microcode_updates, unsigned equivalent_processor_rev_id) +{ + unsigned int patch_id, new_patch_id; + struct microcode *m; + char *c; + msr_t msr; + + msr = rdmsr(0x8b); + patch_id = msr.lo; + + printk_debug("microcode: equivalent processor rev id = 0x%04x, patch id = 0x%08x\n", equivalent_processor_rev_id, patch_id); + + m = microcode_updates; + + for(c = microcode_updates; m->date_code; m = (struct microcode *)c) { + + if( need_apply_patch(m, equivalent_processor_rev_id) ) { + //apply patch + + msr.hi = 0; + msr.lo = (uint32_t)m; + + wrmsr(0xc0010020, msr); + + printk_debug("microcode: patch id that want to apply= 0x%08x\n", m->patch_id); + + //read the patch_id again + msr = rdmsr(0x8b); + new_patch_id = msr.lo; + + printk_debug("microcode: updated to patch id = 0x%08x %s\r\n", new_patch_id , (new_patch_id == m->patch_id)?" success":" fail" ); + break; + } + c += 2048; + } + +} diff --git a/src/cpu/amd/model_fxx/Config.lb b/src/cpu/amd/model_fxx/Config.lb index 924dc8f155..d54f6be91c 100644 --- a/src/cpu/amd/model_fxx/Config.lb +++ b/src/cpu/amd/model_fxx/Config.lb @@ -11,5 +11,6 @@ dir /cpu/x86/cache dir /cpu/x86/pae dir /cpu/amd/mtrr dir /cpu/amd/dualcore +dir /cpu/amd/microcode driver model_fxx_init.o object apic_timer.o diff --git a/src/cpu/amd/model_fxx/model_fxx_init.c b/src/cpu/amd/model_fxx/model_fxx_init.c index bd3a1cea08..937906abca 100644 --- a/src/cpu/amd/model_fxx/model_fxx_init.c +++ b/src/cpu/amd/model_fxx/model_fxx_init.c @@ -3,7 +3,49 @@ * 2004.11 yhlu add d0 e0 support * 2004.12 yhlu add dual core support * 2005.02 yhlu add e0 memory hole support + +*/ +/*============================================================================ +Copyright 2005 ADVANCED MICRO DEVICES, INC. All Rights Reserved. +This software and any related documentation (the "Materials") are the +confidential proprietary information of AMD. Unless otherwise provided in a +software agreement specifically licensing the Materials, the Materials are +provided in confidence and may not be distributed, modified, or reproduced in +whole or in part by any means. +LIMITATION OF LIABILITY: THE MATERIALS ARE PROVIDED "AS IS" WITHOUT ANY +EXPRESS OR IMPLIED WARRANTY OF ANY KIND, INCLUDING BUT NOT LIMITED TO +WARRANTIES OF MERCHANTABILITY, NONINFRINGEMENT, TITLE, FITNESS FOR ANY +PARTICULAR PURPOSE, OR WARRANTIES ARISING FROM CONDUCT, COURSE OF DEALING, OR +USAGE OF TRADE. IN NO EVENT SHALL AMD OR ITS LICENSORS BE LIABLE FOR ANY +DAMAGES WHATSOEVER (INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF PROFITS, +BUSINESS INTERRUPTION, OR LOSS OF INFORMATION) ARISING OUT OF THE USE OF OR +INABILITY TO USE THE MATERIALS, EVEN IF AMD HAS BEEN ADVISED OF THE +POSSIBILITY OF SUCH DAMAGES. BECAUSE SOME JURISDICTIONS PROHIBIT THE EXCLUSION +OR LIMITATION OF LIABILITY FOR CONSEQUENTIAL OR INCIDENTAL DAMAGES, THE ABOVE +LIMITATION MAY NOT APPLY TO YOU. +AMD does not assume any responsibility for any errors which may appear in the +Materials nor any responsibility to support or update the Materials. AMD +retains the right to modify the Materials at any time, without notice, and is +not obligated to provide such modified Materials to you. +NO SUPPORT OBLIGATION: AMD is not obligated to furnish, support, or make any +further information, software, technical information, know-how, or show-how +available to you. +U.S. GOVERNMENT RESTRICTED RIGHTS: The Materials are provided with "RESTRICTED +RIGHTS." Use, duplication, or disclosure by the Government is subject to the +restrictions as set forth in FAR 52.227-14 and DFAR 252.227-7013, et seq., or +its successor. Use of the Materials by the Government constitutes +acknowledgement of AMD's proprietary rights in them. +============================================================================*/ +//@DOC +// in model_fxx_init.c +/* +$1.0$ */ +// Description: microcode patch support for k8 +// by yhlu +// +//============================================================================ + #include <console/console.h> #include <cpu/x86/msr.h> #include <cpu/amd/mtrr.h> @@ -18,11 +60,24 @@ #include "../../../northbridge/amd/amdk8/amdk8.h" #include "../../../northbridge/amd/amdk8/cpu_rev.c" #include <cpu/cpu.h> +#include <cpu/amd/microcode.h> #include <cpu/x86/cache.h> #include <cpu/x86/mtrr.h> #include <cpu/x86/mem.h> #include <cpu/amd/dualcore.h> +static uint8_t microcode_updates[] __attribute__ ((aligned(16))) = { + +#include "microcode_rev_c.h" +#include "microcode_rev_d.h" +#include "microcode_rev_e.h" + /* Dummy terminator */ + 0x0, 0x0, 0x0, 0x0, + 0x0, 0x0, 0x0, 0x0, + 0x0, 0x0, 0x0, 0x0, + 0x0, 0x0, 0x0, 0x0, +}; + #include "model_fxx_msr.h" #define MCI_STATUS 0x401 @@ -365,17 +420,64 @@ static inline void k8_errata(void) } +static unsigned id_mapping_table[] = { + 0x0f48, 0x0048, + 0x0f58, 0x0048, + + 0x0f4a, 0x004a, + 0x0f5a, 0x004a, + 0x0f7a, 0x004a, + 0x0f82, 0x004a, + 0x0fc0, 0x004a, + 0x0ff0, 0x004a, + + 0x10f50, 0x0150, + 0x10f70, 0x0150, + 0x10f80, 0x0150, + 0x10fc0, 0x0150, + 0x10ff0, 0x0150, + + 0x20f10, 0x0210, + 0x20f12, 0x0210, + 0x20f32, 0x0210, + 0x20fb1, 0x0210, + +}; + +static unsigned get_equivalent_processor_rev_id(unsigned orig_id) { + unsigned new_id; + int i; + + new_id = 0; + + for(i=0; i<sizeof(id_mapping_table); i+=2 ) { + if(id_mapping_table[i]==orig_id) { + new_id = id_mapping_table[i+1]; + break; + } + } + + return new_id; + +} + void model_fxx_init(device_t cpu) { unsigned long i; msr_t msr; struct node_core_id id; + unsigned equivalent_processor_rev_id; /* Turn on caching if we haven't already */ x86_enable_cache(); amd_setup_mtrrs(); x86_mtrr_check(); + /* Update the microcode */ + equivalent_processor_rev_id = get_equivalent_processor_rev_id(cpu->device ); + if(equivalent_processor_rev_id != 0) + amd_update_microcode(microcode_updates, equivalent_processor_rev_id); + disable_cache(); /* zero the machine check error status registers */ |