diff options
277 files changed, 15404 insertions, 5320 deletions
diff --git a/src/cpu/amd/agesa/family14/Makefile.inc b/src/cpu/amd/agesa/family14/Makefile.inc index 3039300976..774d401b63 100644 --- a/src/cpu/amd/agesa/family14/Makefile.inc +++ b/src/cpu/amd/agesa/family14/Makefile.inc @@ -63,9 +63,10 @@ agesa_lib_src += $(AGESA_ROOT)/Proc/GNB/PCIe/Family/0x14/F14PcieAlib.c agesa_lib_src += $(AGESA_ROOT)/Proc/CPU/Family/0x14/F14IoCstate.c agesa_lib_src += $(AGESA_ROOT)/Proc/CPU/Feature/cpuIoCstate.c agesa_lib_src += $(AGESA_ROOT)/Proc/Mem/NB/ON/mnprotoon.c -agesa_lib_src += $(AGESA_ROOT)/Proc/CPU/Family/0x14/F14MicrocodePatch05000025.c agesa_lib_src += $(AGESA_ROOT)/Proc/CPU/Family/0x14/F14MicrocodePatch0500000B.c agesa_lib_src += $(AGESA_ROOT)/Proc/CPU/Family/0x14/F14MicrocodePatch0500001A.c +agesa_lib_src += $(AGESA_ROOT)/Proc/CPU/Family/0x14/F14MicrocodePatch05000028.c +agesa_lib_src += $(AGESA_ROOT)/Proc/CPU/Family/0x14/F14MicrocodePatch05000101.c agesa_lib_src += $(AGESA_ROOT)/Proc/GNB/PCIe/Family/0x14/F14PciePifServices.c agesa_lib_src += $(AGESA_ROOT)/Proc/CPU/Family/0x14/ON/F14OnInitEarlyTable.c agesa_lib_src += $(AGESA_ROOT)/Proc/CPU/cpuInitEarlyTable.c @@ -103,6 +104,7 @@ agesa_lib_src += $(AGESA_ROOT)/Proc/Mem/Main/mmParallelTraining.c agesa_lib_src += $(AGESA_ROOT)/Proc/Mem/Feat/LVDDR3/mflvddr3.c agesa_lib_src += $(AGESA_ROOT)/Proc/GNB/PCIe/Family/0x14/F14PcieComplexConfig.c agesa_lib_src += $(AGESA_ROOT)/Proc/CPU/Family/0x14/cpuF14PowerPlane.c +agesa_lib_src += $(AGESA_ROOT)/Proc/CPU/Family/0x14/cpuF14LowPowerInit.c agesa_lib_src += $(AGESA_ROOT)/Proc/Mem/NB/mnreg.c agesa_lib_src += $(AGESA_ROOT)/Proc/Mem/NB/ON/mnflowon.c agesa_lib_src += $(AGESA_ROOT)/Proc/Mem/Feat/CHINTLV/mfchi.c @@ -113,6 +115,7 @@ agesa_lib_src += $(AGESA_ROOT)/Proc/Mem/Ps/ON/mpuon3.c agesa_lib_src += $(AGESA_ROOT)/Proc/CPU/cahalt.c agesa_lib_src += $(AGESA_ROOT)/Proc/Mem/Tech/mt.c agesa_lib_src += $(AGESA_ROOT)/Proc/CPU/Family/0x14/ON/F14OnMicrocodePatchTables.c +agesa_lib_src += $(AGESA_ROOT)/Proc/CPU/Family/0x14/ON/F14OnPciTables.c agesa_lib_src += $(AGESA_ROOT)/Proc/GNB/PCIe/PciePortInit.c agesa_lib_src += $(AGESA_ROOT)/Proc/Mem/NB/mnflow.c agesa_lib_src += $(AGESA_ROOT)/Proc/CPU/Feature/cpuFeatureLeveling.c @@ -138,6 +141,7 @@ agesa_lib_src += $(AGESA_ROOT)/Proc/GNB/Gfx/GfxStrapsInit.c agesa_lib_src += $(AGESA_ROOT)/Proc/GNB/Nb/NbInitAtEarly.c agesa_lib_src += $(AGESA_ROOT)/Lib/amdlib.c agesa_lib_src += $(AGESA_ROOT)/Proc/CPU/Feature/cpuCacheFlushOnHalt.c +agesa_lib_src += $(AGESA_ROOT)/Proc/CPU/Feature/cpuCpb.c agesa_lib_src += $(AGESA_ROOT)/Proc/Mem/Main/minit.c agesa_lib_src += $(AGESA_ROOT)/Proc/GNB/PCIe/Family/0x14/F14PciePhyServices.c agesa_lib_src += $(AGESA_ROOT)/Proc/GNB/GnbInitAtLate.c @@ -213,6 +217,7 @@ agesa_lib_src += $(AGESA_ROOT)/Proc/Common/AmdInitLate.c agesa_lib_src += $(AGESA_ROOT)/Proc/HT/htFeat.c agesa_lib_src += $(AGESA_ROOT)/Proc/GNB/Nb/NbInitAtReset.c agesa_lib_src += $(AGESA_ROOT)/Proc/CPU/Family/0x14/ON/F14OnLogicalIdTables.c +agesa_lib_src += $(AGESA_ROOT)/Proc/CPU/Family/0x14/ON/F14OnCpb.c agesa_lib_src += $(AGESA_ROOT)/Legacy/Proc/hobTransfer.c agesa_lib_src += $(AGESA_ROOT)/Proc/CPU/cpuApicUtilities.c agesa_lib_src += $(AGESA_ROOT)/Proc/GNB/GnbInitAtEnv.c diff --git a/src/vendorcode/amd/agesa/f12/Include/ComalInstall.h b/src/vendorcode/amd/agesa/f12/Include/ComalInstall.h deleted file mode 100755 index 331ca11ba3..0000000000 --- a/src/vendorcode/amd/agesa/f12/Include/ComalInstall.h +++ /dev/null @@ -1,147 +0,0 @@ -/* $NoKeywords:$ */ -/** - * @file - * - * Install of build options for a Comal platform solution - * - * This file generates the defaults tables for the "Comal" platform solution - * set of processors. The documented build options are imported from a user - * controlled file for processing. - * - * @xrefitem bom "File Content Label" "Release Content" - * @e project: AGESA - * @e sub-project: Core - * @e \$Revision: 49803 $ @e \$Date: 2011-03-29 15:20:04 +0800 (Tue, 29 Mar 2011) $ - */ -/***************************************************************************** - * - * Copyright (c) 2011, Advanced Micro Devices, Inc. - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * * Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * * Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * * Neither the name of Advanced Micro Devices, Inc. nor the names of - * its contributors may be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY - * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND - * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - ***************************************************************************/ - -#include "cpuRegisters.h" -#include "cpuFamRegisters.h" -#include "cpuFamilyTranslation.h" -#include "AdvancedApi.h" -#include "heapManager.h" -#include "CreateStruct.h" -#include "cpuFeatures.h" -#include "Table.h" -#include "CommonReturns.h" -#include "cpuEarlyInit.h" -#include "cpuLateInit.h" -#include "GnbInterface.h" - -/***************************************************************************** - * Define the RELEASE VERSION string - * - * The Release Version string should identify the next planned release. - * When a branch is made in preparation for a release, the release manager - * should change/confirm that the branch version of this file contains the - * string matching the desired version for the release. The trunk version of - * the file should always contain a trailing 'X'. This will make sure that a - * development build from trunk will not be confused for a released version. - * The release manager will need to remove the trailing 'X' and update the - * version string as appropriate for the release. The trunk copy of this file - * should also be updated/incremented for the next expected version, + trailing 'X' - ****************************************************************************/ - // This is the delivery package title, "TrinyPI " - // This string MUST be exactly 8 characters long -#define AGESA_PACKAGE_STRING {'T', 'r', 'i', 'n', 'y', 'P', 'I', ' '} - - // This is the release version number of the AGESA component - // This string MUST be exactly 12 characters long -#define AGESA_VERSION_STRING {'V', '0', '.', '0', '.', '6', '.', '0', 'X', ' ', ' ', ' '} - - -// The Comal solution is defined to be family 0x15 in the FS1 and FP2 sockets. -#define INSTALL_FS1_SOCKET_SUPPORT TRUE -#define INSTALL_FP2_SOCKET_SUPPORT TRUE -#define INSTALL_FAMILY_15_SUPPORT TRUE - -#ifdef BLDOPT_REMOVE_FS1_SOCKET_SUPPORT - #if BLDOPT_REMOVE_FS1_SOCKET_SUPPORT == TRUE - #undef INSTALL_FS1_SOCKET_SUPPORT - #define INSTALL_FS1_SOCKET_SUPPORT FALSE - #endif -#endif - -#ifdef BLDOPT_REMOVE_FP2_SOCKET_SUPPORT - #if BLDOPT_REMOVE_FP2_SOCKET_SUPPORT == TRUE - #undef INSTALL_FP2_SOCKET_SUPPORT - #define INSTALL_FP2_SOCKET_SUPPORT FALSE - #endif -#endif - - -// The following definitions specify the default values for various parameters in which there are -// no clearly defined defaults to be used in the common file. The values below are based on product -// and BKDG content, please consult the AGESA Memory team for consultation. -#define DFLT_SCRUB_DRAM_RATE (0) -#define DFLT_SCRUB_L2_RATE (0) -#define DFLT_SCRUB_L3_RATE (0) -#define DFLT_SCRUB_IC_RATE (0) -#define DFLT_SCRUB_DC_RATE (0) -#define DFLT_MEMORY_QUADRANK_TYPE QUADRANK_UNBUFFERED -#define DFLT_VRM_SLEW_RATE (5000) - - -#define DFLT_SMBUS0_BASE_ADDRESS 0xB00 -#define DFLT_SMBUS1_BASE_ADDRESS 0xB20 -#define DFLT_SIO_PME_BASE_ADDRESS 0xE00 -#define DFLT_ACPI_PM1_EVT_BLOCK_ADDRESS 0x400 -#define DFLT_ACPI_PM1_CNT_BLOCK_ADDRESS 0x404 -#define DFLT_ACPI_PM_TMR_BLOCK_ADDRESS 0x408 -#define DFLT_ACPI_CPU_CNT_BLOCK_ADDRESS 0x410 -#define DFLT_ACPI_GPE0_BLOCK_ADDRESS 0x420 -#define DFLT_SPI_BASE_ADDRESS 0xFEC10000 -#define DFLT_WATCHDOG_TIMER_BASE_ADDRESS 0xFEC00000 -#define DFLT_HPET_BASE_ADDRESS 0xFED00000 -#define DFLT_SMI_CMD_PORT 0xB0 -#define DFLT_ACPI_PMA_CNT_BLK_ADDRESS 0xFE00 -#define DFLT_GEC_BASE_ADDRESS 0xFED61000 -#define DFLT_AZALIA_SSID 0x780D1022 -#define DFLT_SMBUS_SSID 0x780B1022 -#define DFLT_IDE_SSID 0x780C1022 -#define DFLT_SATA_AHCI_SSID 0x78011022 -#define DFLT_SATA_IDE_SSID 0x78001022 -#define DFLT_SATA_RAID5_SSID 0x78031022 -#define DFLT_SATA_RAID_SSID 0x78021022 -#define DFLT_EHCI_SSID 0x78081022 -#define DFLT_OHCI_SSID 0x78071022 -#define DFLT_LPC_SSID 0x780E1022 -#define DFLT_FCH_GPP_LINK_CONFIG PortA4 -#define DFLT_FCH_GPP_PORT0_PRESENT FALSE -#define DFLT_FCH_GPP_PORT1_PRESENT FALSE -#define DFLT_FCH_GPP_PORT2_PRESENT FALSE -#define DFLT_FCH_GPP_PORT3_PRESENT FALSE -#define DFLT_FCH_GPP_PORT0_HOTPLUG FALSE -#define DFLT_FCH_GPP_PORT1_HOTPLUG FALSE -#define DFLT_FCH_GPP_PORT2_HOTPLUG FALSE -#define DFLT_FCH_GPP_PORT3_HOTPLUG FALSE -// Instantiate all solution relevant data. -#include "PlatformInstall.h" - diff --git a/src/vendorcode/amd/agesa/f12/Include/DeccanInstall.h b/src/vendorcode/amd/agesa/f12/Include/DeccanInstall.h deleted file mode 100755 index d4c8ba5956..0000000000 --- a/src/vendorcode/amd/agesa/f12/Include/DeccanInstall.h +++ /dev/null @@ -1,132 +0,0 @@ -/* $NoKeywords:$ */ -/** - * @file - * - * Install of build options for a Deccan platform solution - * - * This file generates the defaults tables for the "Deccan" platform solution - * set of processors. The documented build options are imported from a user - * controlled file for processing. - * - * @xrefitem bom "File Content Label" "Release Content" - * @e project: AGESA - * @e sub-project: Core - * @e \$Revision: 35276 $ @e \$Date: 2010-07-19 10:47:05 -0700 (Mon, 19 Jul 2010) $ - */ -/***************************************************************************** - * - * Copyright (c) 2011, Advanced Micro Devices, Inc. - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * * Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * * Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * * Neither the name of Advanced Micro Devices, Inc. nor the names of - * its contributors may be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY - * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND - * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - ***************************************************************************/ - -#include "cpuRegisters.h" -#include "cpuFamRegisters.h" -#include "cpuFamilyTranslation.h" -#include "AdvancedApi.h" -#include "heapManager.h" -#include "CreateStruct.h" -#include "cpuFeatures.h" -#include "Table.h" -#include "CommonReturns.h" -#include "cpuEarlyInit.h" -#include "cpuLateInit.h" -#include "GnbInterface.h" - -/***************************************************************************** - * Define the RELEASE VERSION string - * - * The Release Version string should identify the next planned release. - * When a branch is made in preparation for a release, the release manager - * should change/confirm that the branch version of this file contains the - * string matching the desired version for the release. The trunk version of - * the file should always contain a trailing 'X'. This will make sure that a - * development build from trunk will not be confused for a released version. - * The release manager will need to remove the trailing 'X' and update the - * version string as appropriate for the release. The trunk copy of this file - * should also be updated/incremented for the next expected version, + trailing 'X' - ****************************************************************************/ - // This is the delivery package title, "KrishaPI" - // This string MUST be exactly 8 characters long -#define AGESA_PACKAGE_STRING {'K', 'r', 'i', 's', 'h', 'a', 'P', 'I'} - - // This is the release version number of the AGESA component - // This string MUST be exactly 12 characters long -#define AGESA_VERSION_STRING {'V', '0', '.', '0', '.', '3', '.', '0', 'X', ' ', ' ', ' '} - - -// The Deccan solution is defined to be family 0x14, models 10h-1fh in the FT2 socket. -#define INSTALL_FT2_SOCKET_SUPPORT TRUE -#define INSTALL_FAMILY_14_SUPPORT TRUE - - -// The following definitions specify the default values for various parameters in which there are -// no clearly defined defaults to be used in the common file. The values below are based on product -// and BKDG content, please consult the AGESA Memory team for consultation. -#define DFLT_SCRUB_DRAM_RATE (0) -#define DFLT_SCRUB_L2_RATE (0) -#define DFLT_SCRUB_L3_RATE (0) -#define DFLT_SCRUB_IC_RATE (0) -#define DFLT_SCRUB_DC_RATE (0) -#define DFLT_MEMORY_QUADRANK_TYPE QUADRANK_UNBUFFERED -#define DFLT_VRM_SLEW_RATE (5000) - - -#define DFLT_SMBUS0_BASE_ADDRESS 0xB00 -#define DFLT_SMBUS1_BASE_ADDRESS 0xB20 -#define DFLT_SIO_PME_BASE_ADDRESS 0xE00 -#define DFLT_ACPI_PM1_EVT_BLOCK_ADDRESS 0x400 -#define DFLT_ACPI_PM1_CNT_BLOCK_ADDRESS 0x404 -#define DFLT_ACPI_PM_TMR_BLOCK_ADDRESS 0x408 -#define DFLT_ACPI_CPU_CNT_BLOCK_ADDRESS 0x410 -#define DFLT_ACPI_GPE0_BLOCK_ADDRESS 0x420 -#define DFLT_SPI_BASE_ADDRESS 0xFEC10000 -#define DFLT_WATCHDOG_TIMER_BASE_ADDRESS 0xFEC00000 -#define DFLT_HPET_BASE_ADDRESS 0xFED00000 -#define DFLT_SMI_CMD_PORT 0xB0 -#define DFLT_ACPI_PMA_CNT_BLK_ADDRESS 0xFE00 -#define DFLT_GEC_BASE_ADDRESS 0xFED61000 -#define DFLT_AZALIA_SSID 0x780D1022 -#define DFLT_SMBUS_SSID 0x780B1022 -#define DFLT_IDE_SSID 0x780C1022 -#define DFLT_SATA_AHCI_SSID 0x78011022 -#define DFLT_SATA_IDE_SSID 0x78001022 -#define DFLT_SATA_RAID5_SSID 0x78031022 -#define DFLT_SATA_RAID_SSID 0x78021022 -#define DFLT_EHCI_SSID 0x78081022 -#define DFLT_OHCI_SSID 0x78071022 -#define DFLT_LPC_SSID 0x780E1022 -#define DFLT_FCH_GPP_LINK_CONFIG PortA4 -#define DFLT_FCH_GPP_PORT0_PRESENT FALSE -#define DFLT_FCH_GPP_PORT1_PRESENT FALSE -#define DFLT_FCH_GPP_PORT2_PRESENT FALSE -#define DFLT_FCH_GPP_PORT3_PRESENT FALSE -#define DFLT_FCH_GPP_PORT0_HOTPLUG FALSE -#define DFLT_FCH_GPP_PORT1_HOTPLUG FALSE -#define DFLT_FCH_GPP_PORT2_HOTPLUG FALSE -#define DFLT_FCH_GPP_PORT3_HOTPLUG FALSE -// Instantiate all solution relevant data. -#include "PlatformInstall.h" - diff --git a/src/vendorcode/amd/agesa/f12/Proc/CPU/Family/cpuFamRegisters.h b/src/vendorcode/amd/agesa/f12/Proc/CPU/Family/cpuFamRegisters.h index fd8073837e..db4e7ad7ce 100755 --- a/src/vendorcode/amd/agesa/f12/Proc/CPU/Family/cpuFamRegisters.h +++ b/src/vendorcode/amd/agesa/f12/Proc/CPU/Family/cpuFamRegisters.h @@ -80,24 +80,18 @@ // Family 12h equates #define AMD_FAMILY_12_LN 0x0000000000000020ull -#define AMD_FAMILY_12 (AMD_FAMILY_12_LN) -#define AMD_FAMILY_LN (AMD_FAMILY_12_LN) +#define AMD_FAMILY_12 (AMD_FAMILY_12_LN) +#define AMD_FAMILY_LN (AMD_FAMILY_12_LN) // Family 14h equates #define AMD_FAMILY_14_ON 0x0000000000000040ull -#define AMD_FAMILY_ON (AMD_FAMILY_14_ON) -#define AMD_FAMILY_14_KR 0x0000000000000080ull -#define AMD_FAMILY_KR (AMD_FAMILY_14_KR) -#define AMD_FAMILY_14 (AMD_FAMILY_14_ON | AMD_FAMILY_14_KR) +#define AMD_FAMILY_14 (AMD_FAMILY_14_ON) +#define AMD_FAMILY_ON (AMD_FAMILY_14_ON) // Family 15h equates #define AMD_FAMILY_15_OR 0x0000000000000100ull #define AMD_FAMILY_OR (AMD_FAMILY_15_OR) -#define AMD_FAMILY_15_TN 0x0000000000000200ull -#define AMD_FAMILY_TN (AMD_FAMILY_15_TN) -#define AMD_FAMILY_15_KM 0x0000000000000400ull -#define AMD_FAMILY_KM (AMD_FAMILY_15_KM) -#define AMD_FAMILY_15 (AMD_FAMILY_15_OR | AMD_FAMILY_15_TN | AMD_FAMILY_15_KM) +#define AMD_FAMILY_15 (AMD_FAMILY_15_OR) // Family 16h equates #define AMD_FAMILY_16 0x0000000000000800ull @@ -203,11 +197,7 @@ #define AMD_F14_ON_Cx (AMD_F14_ON_C0) #define AMD_F14_ON_ALL (AMD_F14_ON_Ax | AMD_F14_ON_Bx | AMD_F14_ON_Cx) -#define AMD_F14_KR_Ax (AMD_F14_KR_A0 | AMD_F14_KR_A1) -#define AMD_F14_KR_Bx AMD_F14_KR_B0 -#define AMD_F14_KR_ALL (AMD_F14_KR_Ax | AMD_F14_KR_Bx) - -#define AMD_F14_ALL (AMD_F14_ON_ALL | AMD_F14_KR_ALL | AMD_F14_UNKNOWN) +#define AMD_F14_ALL (AMD_F14_ON_ALL | AMD_F14_UNKNOWN) // Family 15h CPU_LOGICAL_ID.Revision equates // ------------------------------------- @@ -227,10 +217,7 @@ #define AMD_F15_OR_LT_B1 (AMD_F15_OR_Ax | AMD_F15_OR_B0) #define AMD_F15_OR_ALL (AMD_F15_OR_Ax | AMD_F15_OR_Bx) -#define AMD_F15_TN_Ax (AMD_F15_TN_A0) -#define AMD_F15_TN_ALL (AMD_F15_TN_Ax) - -#define AMD_F15_ALL (AMD_F15_OR_ALL | AMD_F15_TN_ALL | AMD_F15_UNKNOWN) +#define AMD_F15_ALL (AMD_F15_OR_ALL | AMD_F15_UNKNOWN) // Family 16h CPU_LOGICAL_ID.Revision equates // TBD diff --git a/src/vendorcode/amd/agesa/f12/Proc/GNB/Modules/GnbPcieAlibV1/PcieAlib.c b/src/vendorcode/amd/agesa/f12/Proc/GNB/Modules/GnbPcieAlibV1/PcieAlib.c index 8563d6e538..333f46c4eb 100755 --- a/src/vendorcode/amd/agesa/f12/Proc/GNB/Modules/GnbPcieAlibV1/PcieAlib.c +++ b/src/vendorcode/amd/agesa/f12/Proc/GNB/Modules/GnbPcieAlibV1/PcieAlib.c @@ -192,7 +192,7 @@ PcieAlibBuildAcpiTable ( LibAmdMemCopy (AlibSsdtBuffer, &AlibSsdt[0], AlibSsdtlength, StdHeader); // Set PCI MMIO configuration // AmlObjName = '10DA'; - AmlObjName = 0x31304441; + AmlObjName = Int32FromChar ('1', '0', 'D', 'A'); AmlObjPtr = GnbLibFind (AlibSsdtBuffer, AlibSsdtlength, (UINT8*) &AmlObjName, sizeof (AmlObjName)); ASSERT (AmlObjPtr != NULL); if (AmlObjPtr != NULL) { @@ -211,7 +211,7 @@ PcieAlibBuildAcpiTable ( ASSERT (PpFuseArray != NULL); if (PpFuseArray != NULL) { // AmlObjName = '30DA'; - AmlObjName = 0x33304441; + AmlObjName = Int32FromChar ('3', '0', 'D', 'A'); AmlObjPtr = GnbLibFind (AlibSsdtBuffer, AlibSsdtlength, (UINT8*) &AmlObjName, sizeof (AmlObjName)); ASSERT (AmlObjPtr != NULL); if (AmlObjPtr != NULL) { @@ -226,7 +226,7 @@ PcieAlibBuildAcpiTable ( Gen1VidIndex = GnbLocateLowestVidIndex (StdHeader); BootUpVidIndex = GnbLocateHighestVidIndex (StdHeader); // AmlObjName = '40DA'; - AmlObjName = 0x34304441; + AmlObjName = Int32FromChar ('4', '0', 'D', 'A'); AmlObjPtr = GnbLibFind (AlibSsdtBuffer, AlibSsdtlength, (UINT8*) &AmlObjName, sizeof (AmlObjName)); ASSERT (AmlObjPtr != NULL); if (AmlObjPtr != NULL) { @@ -235,7 +235,7 @@ PcieAlibBuildAcpiTable ( AgesaStatus = AGESA_FATAL; } // AmlObjName = '50DA'; - AmlObjName = 0x35304441; + AmlObjName = Int32FromChar ('5', '0', 'D', 'A'); AmlObjPtr = GnbLibFind (AlibSsdtBuffer, AlibSsdtlength, (UINT8*) &AmlObjName, sizeof (AmlObjName)); ASSERT (AmlObjPtr != NULL); if (AmlObjPtr != NULL) { @@ -244,7 +244,7 @@ PcieAlibBuildAcpiTable ( AgesaStatus = AGESA_FATAL; } // AmlObjName = '01DA'; - AmlObjName = 0x30314441; + AmlObjName = Int32FromChar ('0', '1', 'D', 'A'); AmlObjPtr = GnbLibFind (AlibSsdtBuffer, AlibSsdtlength, (UINT8*) &AmlObjName, sizeof (AmlObjName)); ASSERT (AmlObjPtr != NULL); if (AmlObjPtr != NULL) { @@ -255,7 +255,7 @@ PcieAlibBuildAcpiTable ( // Set PCIe configuration if (PcieLocateConfigurationData (StdHeader, &Pcie) == AGESA_SUCCESS) { // AmlObjName = '20DA'; - AmlObjName = 0x32304441; + AmlObjName = Int32FromChar ('2', '0', 'D', 'A'); AmlObjPtr = GnbLibFind (AlibSsdtBuffer, AlibSsdtlength, (UINT8*) &AmlObjName, sizeof (AmlObjName)); ASSERT (AmlObjPtr != NULL); if (AmlObjPtr != NULL) { @@ -264,7 +264,7 @@ PcieAlibBuildAcpiTable ( AgesaStatus = AGESA_FATAL; } // AmlObjName = '60DA'; - AmlObjName = 0x36304441; + AmlObjName = Int32FromChar ('6', '0', 'D', 'A'); AmlObjPtr = GnbLibFind (AlibSsdtBuffer, AlibSsdtlength, (UINT8*) &AmlObjName, sizeof (AmlObjName)); ASSERT (AmlObjPtr != NULL); if (AmlObjPtr != NULL) { @@ -278,7 +278,7 @@ PcieAlibBuildAcpiTable ( AgesaStatus = AGESA_FATAL; } // AmlObjName = '60DA'; - AmlObjName = 0x36304441; + AmlObjName = Int32FromChar ('6', '0', 'D', 'A'); AmlObjPtr = GnbLibFind (AlibSsdtBuffer, AlibSsdtlength, (UINT8*) &AmlObjName, sizeof (AmlObjName)); ASSERT (AmlObjPtr != NULL); if (AmlObjPtr != NULL) { @@ -292,7 +292,7 @@ PcieAlibBuildAcpiTable ( AgesaStatus = AGESA_FATAL; } // AmlObjName = '70DA'; - AmlObjName = 0x37304441; + AmlObjName = Int32FromChar ('7', '0', 'D', 'A'); AmlObjPtr = GnbLibFind (AlibSsdtBuffer, AlibSsdtlength, (UINT8*) &AmlObjName, sizeof (AmlObjName)); ASSERT (AmlObjPtr != NULL); if (AmlObjPtr != NULL) { diff --git a/src/vendorcode/amd/agesa/f12/Proc/GNB/PCIe/Family/LN/F12PcieAlib.c b/src/vendorcode/amd/agesa/f12/Proc/GNB/PCIe/Family/LN/F12PcieAlib.c index 630d688c5a..80095063c9 100755 --- a/src/vendorcode/amd/agesa/f12/Proc/GNB/PCIe/Family/LN/F12PcieAlib.c +++ b/src/vendorcode/amd/agesa/f12/Proc/GNB/PCIe/Family/LN/F12PcieAlib.c @@ -110,7 +110,7 @@ PcieFmAlibBuildAcpiTable ( AgesaStatus = AGESA_SUCCESS; AltVddNbSupport = TRUE; // AmlObjName = 'A0DA'; - AmlObjName = 0x41304441; + AmlObjName = Int32FromChar ('A', '0', 'D', 'A'); AmlObjPtr = GnbLibFind (AlibSsdtPtr, ((ACPI_TABLE_HEADER*) &AlibSsdt[0])->TableLength, (UINT8*) &AmlObjName, sizeof (AmlObjName)); ASSERT (AmlObjPtr != NULL); if (AmlObjPtr != NULL) { diff --git a/src/vendorcode/amd/agesa/f14/AGESA.h b/src/vendorcode/amd/agesa/f14/AGESA.h index 0f348d60ef..511be69338 100644 --- a/src/vendorcode/amd/agesa/f14/AGESA.h +++ b/src/vendorcode/amd/agesa/f14/AGESA.h @@ -9,7 +9,7 @@ * @xrefitem bom "File Content Label" "Release Content" * @e project: AGESA * @e sub-project: Include - * @e \$Revision: 41504 $ @e \$Date: 2010-11-05 21:59:13 +0800 (Fri, 05 Nov 2010) $ + * @e \$Revision: 47417 $ @e \$Date: 2011-02-18 12:48:20 -0700 (Fri, 18 Feb 2011) $ */ /* ***************************************************************************** @@ -822,6 +822,38 @@ typedef enum { * GNB configuration info *---------------------------------------------------------------------------- */ + +/// LVDS Misc Control Field +typedef struct { + IN UINT8 FpdiMode:1; ///< This item configures LVDS 888bit panel mode + ///< @li FALSE = LVDS 888 panel in LDI mode + ///< @li TRUE = LVDS 888 panel in FPDI mode + ///< @BldCfgItem{BLDCFG_LVDS_MISC_888_FPDI_MODE} + IN UINT8 DlChSwap:1; ///< This item configures LVDS panel lower and upper link mapping + ///< @li FALSE = Lower link and upper link not swap + ///< @li TRUE = Lower link and upper link are swapped + ///< @BldCfgItem{BLDCFG_LVDS_MISC_DL_CH_SWAP} + IN UINT8 VsyncActiveLow:1; ///< This item configures polarity of frame pulse encoded in lvds data stream + ///< @li FALSE = Active high Frame Pulse/Vsync + ///< @li TRUE = Active low Frame Pulse/Vsync + ///< @BldCfgItem{BLDCFG_LVDS_MISC_VSYNC_ACTIVE_LOW} + IN UINT8 HsyncActiveLow:1; ///< This item configures polarity of line pulse encoded in lvds data + ///< @li FALSE = Active high Line Pulse + ///< @li TRUE = Active low Line Pulse / Hsync + ///< @BldCfgItem{BLDCFG_LVDS_MISC_HSYNC_ACTIVE_LOW} + IN UINT8 BLONActiveLow:1; ///< This item configures polarity of signal sent to digital BLON output pin + ///< @li FALSE = Not inverted(active high) + ///< @li TRUE = Inverted (active low) + ///< @BldCfgItem{BLDCFG_LVDS_MISC_BLON_ACTIVE_LOW} + IN UINT8 Reserved:3; ///< Reserved +} LVDS_MISC_CONTROL_FIELD; + +/// LVDS Misc Control +typedef union _LVDS_MISC_CONTROL { + IN LVDS_MISC_CONTROL_FIELD Field; ///< LVDS_MISC_CONTROL_FIELD + IN UINT8 Value; ///< LVDS Misc Control Value +} LVDS_MISC_CONTROL; + /// Configuration settings for GNB. typedef struct { IN UINT8 Gnb3dStereoPinIndex; ///< 3D Stereo Pin ID. @@ -837,6 +869,9 @@ typedef struct { ///< BldCfgItem{BLDCFG_GFX_LVDS_SPREAD_SPECTRUM} IN UINT16 LvdsSpreadSpectrumRate; ///< Spread spectrum frequency used by SS hardware logic in unit of 10Hz, 0 - default frequency 40kHz ///< BldCfgItem{BLDCFG_GFX_LVDS_SPREAD_SPECTRUM_RATE} + IN LVDS_MISC_CONTROL LvdsMiscControl;///< This item configures LVDS swap/Hsync/Vsync/BLON + IN UINT16 PcieRefClkSpreadSpectrum; ///< Spread spectrum value in 0.01 % + ///< @BldCfgItem{BLDCFG_PCIE_REFCLK_SPREAD_SPECTRUM} } GNB_ENV_CONFIGURATION; /// GNB configuration info @@ -2240,6 +2275,9 @@ typedef struct { ///< Build-time customizable only - @BldCfgItem{BLDCFG_GFX_LVDS_SPREAD_SPECTRUM} IN UINT16 CfgLvdsSpreadSpectrumRate; ///< Lvds Spread Spectrum Rate ///< Build-time customizable only - @BldCfgItem{BLDCFG_GFX_LVDS_SPREAD_SPECTRUM_RATE} + IN LVDS_MISC_CONTROL CfgLvdsMiscControl; ///< The LVDS Misc control + IN UINT16 CfgPcieRefClkSpreadSpectrum; ///< PCIe Reference Clock Spread Spectrum + ///< Build-time customizable only - @BldCfgItem{BLDCFG_PCIE_REFCLK_SPREAD_SPECTRUM} IN BOOLEAN Reserved; ///< reserved... } BUILD_OPT_CFG; diff --git a/src/vendorcode/amd/agesa/f14/AMD.h b/src/vendorcode/amd/agesa/f14/AMD.h index f788da8476..5c77c58269 100644 --- a/src/vendorcode/amd/agesa/f14/AMD.h +++ b/src/vendorcode/amd/agesa/f14/AMD.h @@ -167,7 +167,7 @@ typedef struct { IN UINT32 AltImageBasePtr; ///< Alternate Image location IN CALLOUT_ENTRY CalloutPtr; ///< For Callout from AGESA IN UINT8 HeapStatus; ///< For heap status from boot time slide. - IN UINT64 HeapBasePtr; ///< Location of the heap + IN VOID *HeapBasePtr; ///< Location of the heap IN OUT UINT8 Reserved[7]; ///< This space is reserved for future use. } AMD_CONFIG_PARAMS; diff --git a/src/vendorcode/amd/agesa/f14/Include/AdvancedApi.h b/src/vendorcode/amd/agesa/f14/Include/AdvancedApi.h index 573650a739..4d59387d0a 100644 --- a/src/vendorcode/amd/agesa/f14/Include/AdvancedApi.h +++ b/src/vendorcode/amd/agesa/f14/Include/AdvancedApi.h @@ -10,14 +10,13 @@ * @xrefitem bom "File Content Label" "Release Content" * @e project: AGESA * @e sub-project: Include - * @e \$Revision: 34897 $ @e \$Date: 2010-07-14 10:07:10 +0800 (Wed, 14 Jul 2010) $ + * @e \$Revision: 44325 $ @e \$Date: 2010-12-22 03:29:53 -0700 (Wed, 22 Dec 2010) $ */ -/* - ***************************************************************************** +/***************************************************************************** * * Copyright (c) 2011, Advanced Micro Devices, Inc. * All rights reserved. - * + * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions are met: * * Redistributions of source code must retain the above copyright @@ -28,7 +27,7 @@ * * Neither the name of Advanced Micro Devices, Inc. nor the names of * its contributors may be used to endorse or promote products derived * from this software without specific prior written permission. - * + * * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE @@ -39,7 +38,7 @@ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * + * * *************************************************************************** * */ @@ -165,4 +164,11 @@ BOOLEAN memDefFalse ( VOID ); + +VOID +MemRecDefRet (VOID); + +BOOLEAN +MemRecDefTrue (VOID); + #endif // _ADVANCED_API_H_ diff --git a/src/vendorcode/amd/agesa/f14/Include/BrazosInstall.h b/src/vendorcode/amd/agesa/f14/Include/BrazosInstall.h index 67539655ce..b309cd4f9f 100644 --- a/src/vendorcode/amd/agesa/f14/Include/BrazosInstall.h +++ b/src/vendorcode/amd/agesa/f14/Include/BrazosInstall.h @@ -11,10 +11,9 @@ * @xrefitem bom "File Content Label" "Release Content" * @e project: AGESA * @e sub-project: Core - * @e \$Revision: 40817 $ @e \$Date: 2010-10-28 03:28:12 +0800 (Thu, 28 Oct 2010) $ + * @e \$Revision: 53801 $ @e \$Date: 2011-05-25 12:03:55 -0600 (Wed, 25 May 2011) $ */ -/* - ***************************************************************************** +/***************************************************************************** * * Copyright (c) 2011, Advanced Micro Devices, Inc. * All rights reserved. @@ -41,7 +40,7 @@ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. * - * *************************************************************************** + **************************************************************************** * */ @@ -77,7 +76,7 @@ // This is the release version number of the AGESA component // This string MUST be exactly 12 characters long -#define AGESA_VERSION_STRING {'V', '1', '.', '0', '.', '0', '.', '1', ' ', ' ', ' ', ' '} +#define AGESA_VERSION_STRING {'V', '1', '.', '1', '.', '0', '.', '0', ' ', ' ', ' ', ' '} // The Brazos solution is defined to be family 0x14 in the FT1 socket. diff --git a/src/vendorcode/amd/agesa/f14/Include/Filecode.h b/src/vendorcode/amd/agesa/f14/Include/Filecode.h index 9ba1b29f8f..bc574cc2db 100644 --- a/src/vendorcode/amd/agesa/f14/Include/Filecode.h +++ b/src/vendorcode/amd/agesa/f14/Include/Filecode.h @@ -12,7 +12,7 @@ * @xrefitem bom "File Content Label" "Release Content" * @e project: AGESA * @e sub-project: Include - * @e \$Revision: 40742 $ @e \$Date: 2010-10-27 04:04:08 +0800 (Wed, 27 Oct 2010) $ + * @e \$Revision: 46485 $ @e \$Date: 2011-02-03 09:03:14 -0700 (Thu, 03 Feb 2011) $ */ /* ***************************************************************************** @@ -426,12 +426,15 @@ #define PROC_CPU_FAMILY_0X14_CPUF14PSTATE_FILECODE (0xCA0D) #define PROC_CPU_FAMILY_0X14_F14C6STATE_FILECODE (0xCA0E) #define PROC_CPU_FAMILY_0X14_F14IOCSTATE_FILECODE (0xCA0F) +#define PROC_CPU_FAMILY_0X14_CPUF14PERCOREPCITABLES_FILECODE (0xCA10) +#define PROC_CPU_FAMILY_0X14_CPUF14LOWPOWERINIT_FILECODE (0xCA11) #define PROC_CPU_FAMILY_0X14_ON_F14ONLOGICALIDTABLES_FILECODE (0xCA21) #define PROC_CPU_FAMILY_0X14_ON_F14ONMICROCODEPATCHTABLES_FILECODE (0xCA22) #define PROC_CPU_FAMILY_0X14_ON_F14ONEQUIVALENCETABLE_FILECODE (0xCA23) #define PROC_CPU_FAMILY_0X14_ON_F14ONINITEARLYTABLE_FILECODE (0xCA24) -#define PROC_CPU_FAMILY_0X14_CPUF14PERCOREPCITABLES_FILECODE (0xCA25) #define PROC_CPU_FAMILY_0X14_ON_F14ONEARLYSAMPLES_FILECODE (0xCA26) +#define PROC_CPU_FAMILY_0X14_ON_F14ONCPB_FILECODE (0xCA2C) +#define PROC_CPU_FAMILY_0X14_ON_F14ONPCITABLES_FILECODE (0xCA2D) // Family 15h #define PROC_CPU_FAMILY_0X15_CPUCOMMONF15UTILITIES_FILECODE (0xCB01) diff --git a/src/vendorcode/amd/agesa/f14/Include/GnbInterface.h b/src/vendorcode/amd/agesa/f14/Include/GnbInterface.h index 761cf3af7e..ed708c9727 100644 --- a/src/vendorcode/amd/agesa/f14/Include/GnbInterface.h +++ b/src/vendorcode/amd/agesa/f14/Include/GnbInterface.h @@ -9,7 +9,7 @@ * @xrefitem bom "File Content Label" "Release Content" * @e project: AGESA * @e sub-project: GNB - * @e \$Revision: 37658 $ @e \$Date: 2010-09-09 15:25:38 +0800 (Thu, 09 Sep 2010) $ + * @e \$Revision: 44325 $ @e \$Date: 2010-12-22 03:29:53 -0700 (Wed, 22 Dec 2010) $ * */ /* @@ -17,7 +17,7 @@ * * Copyright (c) 2011, Advanced Micro Devices, Inc. * All rights reserved. - * + * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions are met: * * Redistributions of source code must retain the above copyright @@ -28,7 +28,7 @@ * * Neither the name of Advanced Micro Devices, Inc. nor the names of * its contributors may be used to endorse or promote products derived * from this software without specific prior written permission. - * + * * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE @@ -39,8 +39,8 @@ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - * *************************************************************************** + * + **************************************************************************** * */ diff --git a/src/vendorcode/amd/agesa/f14/Include/GnbInterfaceStub.h b/src/vendorcode/amd/agesa/f14/Include/GnbInterfaceStub.h index 0b3ff08223..231e06a801 100644 --- a/src/vendorcode/amd/agesa/f14/Include/GnbInterfaceStub.h +++ b/src/vendorcode/amd/agesa/f14/Include/GnbInterfaceStub.h @@ -9,40 +9,40 @@ * @xrefitem bom "File Content Label" "Release Content" * @e project: AGESA * @e sub-project: GNB - * @e \$Revision: 37658 $ @e \$Date: 2010-09-09 15:25:38 +0800 (Thu, 09 Sep 2010) $ + * @e \$Revision: 44325 $ @e \$Date: 2010-12-22 03:29:53 -0700 (Wed, 22 Dec 2010) $ * */ /* - ***************************************************************************** - * - * Copyright (c) 2011, Advanced Micro Devices, Inc. - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * * Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * * Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * * Neither the name of Advanced Micro Devices, Inc. nor the names of - * its contributors may be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY - * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND - * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - * *************************************************************************** - * - */ +***************************************************************************** +* +* Copyright (c) 2011, Advanced Micro Devices, Inc. +* All rights reserved. +* +* Redistribution and use in source and binary forms, with or without +* modification, are permitted provided that the following conditions are met: +* * Redistributions of source code must retain the above copyright +* notice, this list of conditions and the following disclaimer. +* * Redistributions in binary form must reproduce the above copyright +* notice, this list of conditions and the following disclaimer in the +* documentation and/or other materials provided with the distribution. +* * Neither the name of Advanced Micro Devices, Inc. nor the names of +* its contributors may be used to endorse or promote products derived +* from this software without specific prior written permission. +* +* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND +* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +* DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY +* DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES +* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; +* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND +* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS +* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +* +* *************************************************************************** +* +*/ /*---------------------------------------------------------------------------------------- * M O D U L E S U S E D diff --git a/src/vendorcode/amd/agesa/f14/Include/Ids.h b/src/vendorcode/amd/agesa/f14/Include/Ids.h index cbd0b131be..7baa67bd0c 100644 --- a/src/vendorcode/amd/agesa/f14/Include/Ids.h +++ b/src/vendorcode/amd/agesa/f14/Include/Ids.h @@ -9,14 +9,14 @@ * @xrefitem bom "File Content Label" "Release Content" * @e project: AGESA * @e sub-project: IDS - * @e \$Revision: 38634 $ @e \$Date: 2010-09-27 21:39:01 +0800 (Mon, 27 Sep 2010) $ + * @e \$Revision: 44325 $ @e \$Date: 2010-12-22 03:29:53 -0700 (Wed, 22 Dec 2010) $ */ /* ***************************************************************************** * * Copyright (c) 2011, Advanced Micro Devices, Inc. * All rights reserved. - * + * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions are met: * * Redistributions of source code must retain the above copyright @@ -27,7 +27,7 @@ * * Neither the name of Advanced Micro Devices, Inc. nor the names of * its contributors may be used to endorse or promote products derived * from this software without specific prior written permission. - * + * * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE @@ -38,7 +38,7 @@ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * + * * *************************************************************************** * */ @@ -568,12 +568,12 @@ typedef enum { //vv- for debug reference only #define IDS_HDT_CONSOLE(f, s, ...) #endif #else - #pragma warning(disable: 4127) - #ifdef __GNUC__ + #ifndef __GNUC__ + #pragma warning(disable: 4127) #define IDS_HDT_CONSOLE(f, s, ...) - #else - #define IDS_HDT_CONSOLE(f, s, ...) - #endif + #else + #define IDS_HDT_CONSOLE(f, s, ...) printk (BIOS_DEBUG, s, ##__VA_ARGS__); + #endif #endif #define IDS_HDT_CONSOLE_FLUSH_BUFFER(x) @@ -625,7 +625,7 @@ typedef enum { //vv- for debug reference only #endif ///For IDS feat use -#define IDS_FAMILY_ALL 0x0ull +#define IDS_FAMILY_ALL 0xFFFFFFFFFFFFFFFFull #define IDS_BSP_ONLY TRUE #define IDS_ALL_CORES FALSE diff --git a/src/vendorcode/amd/agesa/f14/Include/OptionCpbInstall.h b/src/vendorcode/amd/agesa/f14/Include/OptionCpbInstall.h index 45f8498d69..f377a8e1dd 100644 --- a/src/vendorcode/amd/agesa/f14/Include/OptionCpbInstall.h +++ b/src/vendorcode/amd/agesa/f14/Include/OptionCpbInstall.h @@ -56,10 +56,11 @@ #define OPTION_CPB_FEAT #define F10_CPB_SUPPORT #define F12_CPB_SUPPORT +#define F14_ON_CPB_SUPPORT #define F15_CPB_SUPPORT #if OPTION_CPB == TRUE - #if (AGESA_ENTRY_INIT_EARLY == TRUE) || (AGESA_ENTRY_INIT_LATE == TRUE) + #if (AGESA_ENTRY_INIT_EARLY == TRUE) || (AGESA_ENTRY_INIT_LATE == TRUE) || (AGESA_ENTRY_INIT_LATE_RESTORE == TRUE) // Family 10h #ifdef OPTION_FAMILY10H #if OPTION_FAMILY10H == TRUE @@ -88,6 +89,20 @@ #endif #endif + // Family 14h + #ifdef OPTION_FAMILY14H + #if OPTION_FAMILY14H == TRUE + #if OPTION_FAMILY14H_ON == TRUE + extern CONST CPU_FEATURE_DESCRIPTOR ROMDATA CpuFeatureCpb; + #undef OPTION_CPB_FEAT + #define OPTION_CPB_FEAT &CpuFeatureCpb, + extern CONST CPB_FAMILY_SERVICES ROMDATA F14OnCpbSupport; + #undef F14_ON_CPB_SUPPORT + #define F14_ON_CPB_SUPPORT {AMD_FAMILY_14_ON, &F14OnCpbSupport}, + #endif + #endif + #endif + // Family 15h #ifdef OPTION_FAMILY15H #if OPTION_FAMILY15H == TRUE @@ -109,6 +124,7 @@ CONST CPU_SPECIFIC_SERVICES_XLAT ROMDATA CpbFamilyServiceArray[] = { F10_CPB_SUPPORT F12_CPB_SUPPORT + F14_ON_CPB_SUPPORT F15_CPB_SUPPORT {0, NULL} }; diff --git a/src/vendorcode/amd/agesa/f14/Include/OptionFamily14hInstall.h b/src/vendorcode/amd/agesa/f14/Include/OptionFamily14hInstall.h index 38a287d5c0..1187c03be3 100644 --- a/src/vendorcode/amd/agesa/f14/Include/OptionFamily14hInstall.h +++ b/src/vendorcode/amd/agesa/f14/Include/OptionFamily14hInstall.h @@ -69,7 +69,7 @@ extern F_CPU_GET_FAMILY_SPECIFIC_ARRAY GetF14BrandIdString2; extern F_CPU_GET_FAMILY_SPECIFIC_ARRAY GetF14CacheInfo; extern F_CPU_GET_FAMILY_SPECIFIC_ARRAY GetF14SysPmTable; extern F_CPU_GET_FAMILY_SPECIFIC_ARRAY GetF14WheaInitData; -extern F_CPU_GET_FAMILY_SPECIFIC_ARRAY GetEmptyArray; +//extern F_CPU_GET_FAMILY_SPECIFIC_ARRAY GetEmptyArray; extern F_CPU_GET_PLATFORM_TYPE_SPECIFIC_INFO F14GetPlatformTypeSpecificInfo; extern F_CPU_GET_IDD_MAX F14GetProcIddMax; extern CONST REGISTER_TABLE ROMDATA F14PciRegisterTable; @@ -90,6 +90,7 @@ extern F_IS_NB_PSTATE_ENABLED F14IsNbPstateEnabled; #if OPTION_FAMILY14H_ON == TRUE extern F_CPU_GET_FAMILY_SPECIFIC_ARRAY GetF14OnMicroCodePatchesStruct; extern F_CPU_GET_FAMILY_SPECIFIC_ARRAY GetF14OnMicrocodeEquivalenceTable; + extern CONST REGISTER_TABLE ROMDATA F14OnPciRegisterTable; #if USES_REGISTER_TABLES == TRUE CONST REGISTER_TABLE ROMDATA *F14OnRegisterTables[] = @@ -106,6 +107,9 @@ extern F_IS_NB_PSTATE_ENABLED F14IsNbPstateEnabled; &F14EarlySampleMsrRegisterTable, #endif #endif + #if MODEL_SPECIFIC_PCI == TRUE + &F14OnPciRegisterTable, + #endif // the end. NULL }; @@ -325,7 +329,8 @@ extern F_IS_NB_PSTATE_ENABLED F14IsNbPstateEnabled; #if GET_PATCHES == TRUE #define F14_ON_UCODE_0B #define F14_ON_UCODE_1A - #define F14_ON_UCODE_25 + #define F14_ON_UCODE_28 + #define F14_ON_UCODE_101 // If a patch is required for recovery mode to function properly, add a // conditional for AGESA_ENTRY_INIT_RECOVERY, and pull it in. @@ -339,16 +344,21 @@ extern F_IS_NB_PSTATE_ENABLED F14IsNbPstateEnabled; #undef F14_ON_UCODE_1A #define F14_ON_UCODE_1A &CpuF14MicrocodePatch0500001A, #endif - extern CONST MICROCODE_PATCHES ROMDATA CpuF14MicrocodePatch05000025; - #undef F14_ON_UCODE_25 - #define F14_ON_UCODE_25 &CpuF14MicrocodePatch05000025, + extern CONST MICROCODE_PATCHES ROMDATA CpuF14MicrocodePatch05000028; + #undef F14_ON_UCODE_28 + #define F14_ON_UCODE_28 &CpuF14MicrocodePatch05000028, + + extern CONST MICROCODE_PATCHES ROMDATA CpuF14MicrocodePatch05000101; + #undef F14_ON_UCODE_101 + #define F14_ON_UCODE_101 &CpuF14MicrocodePatch05000101, #endif CONST MICROCODE_PATCHES ROMDATA *CpuF14OnMicroCodePatchArray[] = { + F14_ON_UCODE_101 + F14_ON_UCODE_28 F14_ON_UCODE_0B F14_ON_UCODE_1A - F14_ON_UCODE_25 NULL }; diff --git a/src/vendorcode/amd/agesa/f14/Include/OptionGnb.h b/src/vendorcode/amd/agesa/f14/Include/OptionGnb.h index 5f3fbd60fc..ccc2292027 100644 --- a/src/vendorcode/amd/agesa/f14/Include/OptionGnb.h +++ b/src/vendorcode/amd/agesa/f14/Include/OptionGnb.h @@ -81,7 +81,12 @@ typedef struct { BOOLEAN LclkDpmEn; ///< Default for LCLK DPM BOOLEAN GmcPowerGateStutterOnly; ///< Force GMC power gate to stutter only BOOLEAN SmuSclkClockGatingEnable;///< Control SMU SCLK gating - BOOLEAN PcieAspmBlackListEnable; ///< Control Pcie Aspm Black List + BOOLEAN PcieAspmBlackListEnable; ///< Control Pcie Aspm Black List + UINT32 LinkReceiverDetectionPooling; ///< Receiver pooling detection time in us. + UINT32 LinkL0Pooling; ///< Pooling for link to get to L0 in us + UINT32 LinkGpioResetAssertionTime; ///< Gpio reset assertion time in us + UINT32 LinkResetToTrainingTime; ///< Time duration between deassert GPIO reset and release training in us /// + UINT8 TrainingAlgorithm; ///< Training algorithm (see PCIE_TRAINING_ALGORITHM) } GNB_BUILD_OPTIONS; /*---------------------------------------------------------------------------------------- diff --git a/src/vendorcode/amd/agesa/f14/Include/OptionGnbInstall.h b/src/vendorcode/amd/agesa/f14/Include/OptionGnbInstall.h index d8acee7c6d..db4730293d 100644 --- a/src/vendorcode/amd/agesa/f14/Include/OptionGnbInstall.h +++ b/src/vendorcode/amd/agesa/f14/Include/OptionGnbInstall.h @@ -10,7 +10,7 @@ * @xrefitem bom "File Content Label" "Release Content" * @e project: AGESA * @e sub-project: Options - * @e \$Revision: 40151 $ @e \$Date: 2010-10-20 06:38:17 +0800 (Wed, 20 Oct 2010) $ + * @e \$Revision: 44325 $ @e \$Date: 2010-12-22 03:29:53 -0700 (Wed, 22 Dec 2010) $ */ /* ***************************************************************************** @@ -58,6 +58,9 @@ #define GNB_TYPE_KR FALSE #define GNB_TYPE_TN FALSE +#include "Gnb.h" +#include "GnbPcie.h" + #ifndef CFG_IGFX_AS_PCIE_EP #define CFG_IGFX_AS_PCIE_EP TRUE #endif @@ -94,13 +97,40 @@ #define CFG_PCIE_ASPM_BLACK_LIST_ENABLE TRUE #endif +#ifndef CFG_GNB_PCIE_LINK_RECEIVER_DETECTION_POOLING + #define CFG_GNB_PCIE_LINK_RECEIVER_DETECTION_POOLING (60 * 1000) +#endif + +#ifndef CFG_GNB_PCIE_LINK_L0_POOLING + #define CFG_GNB_PCIE_LINK_L0_POOLING (60 * 1000) +#endif + +#ifndef CFG_GNB_PCIE_LINK_GPIO_RESET_ASSERT_TIME + #define CFG_GNB_PCIE_LINK_GPIO_RESET_ASSERT_TIME (2 * 1000) +#endif + +#ifndef CFG_GNB_PCIE_LINK_RESET_TO_TRAINING_TIME + #define CFG_GNB_PCIE_LINK_RESET_TO_TRAINING_TIME (2 * 1000) +#endif + +#ifdef BLDCFG_PCIE_TRAINING_ALGORITHM + #define CFG_GNB_PCIE_TRAINING_ALGORITHM BLDCFG_PCIE_TRAINING_ALGORITHM +#else + #define CFG_GNB_PCIE_TRAINING_ALGORITHM PcieTrainingStandard +#endif + GNB_BUILD_OPTIONS GnbBuildOptions = { CFG_IGFX_AS_PCIE_EP, CFG_LCLK_DEEP_SLEEP_EN, CFG_LCLK_DPM_EN, CFG_GMC_POWER_GATE_STUTTER_ONLY, CFG_SMU_SCLK_CLOCK_GATING_ENABLE, - CFG_PCIE_ASPM_BLACK_LIST_ENABLE + CFG_PCIE_ASPM_BLACK_LIST_ENABLE, + CFG_GNB_PCIE_LINK_RECEIVER_DETECTION_POOLING, + CFG_GNB_PCIE_LINK_L0_POOLING, + CFG_GNB_PCIE_LINK_GPIO_RESET_ASSERT_TIME, + CFG_GNB_PCIE_LINK_RESET_TO_TRAINING_TIME, + CFG_GNB_PCIE_TRAINING_ALGORITHM }; @@ -204,6 +234,16 @@ GNB_BUILD_OPTIONS GnbBuildOptions = { #define OPTION_NBINITATPOST_ENTRY #endif //--------------------------------------------------------------------------------------------------- + #ifndef OPTION_PCIE_POST_EALRY_INIT + #define OPTION_PCIE_POST_EALRY_INIT TRUE + #endif + #if (OPTION_PCIE_POST_EALRY_INIT == TRUE) && (GNB_TYPE_LN == TRUE || GNB_TYPE_ON == TRUE) + OPTION_GNB_FEATURE PcieInitAtPostEarly; + #define OPTION_PCIEINITATPOSTEARLY_ENTRY {AMD_FAMILY_LN | AMD_FAMILY_ON, PcieInitAtPostEarly}, + #else + #define OPTION_PCIEINITATPOSTEARLY_ENTRY + #endif +//--------------------------------------------------------------------------------------------------- #ifndef OPTION_PCIE_POST_INIT #define OPTION_PCIE_POST_INIT TRUE #endif @@ -215,6 +255,7 @@ GNB_BUILD_OPTIONS GnbBuildOptions = { #endif //--------------------------------------------------------------------------------------------------- OPTION_GNB_CONFIGURATION GnbPostFeatureTable[] = { + OPTION_PCIEINITATPOSTEARLY_ENTRY OPTION_GFXCONFIGPOSTINTERFACE_ENTRY OPTION_GFXINITATPOST_ENTRY {0, NULL} diff --git a/src/vendorcode/amd/agesa/f14/Include/OptionMemory.h b/src/vendorcode/amd/agesa/f14/Include/OptionMemory.h index 1d4c08f68b..a753c6dac2 100644 --- a/src/vendorcode/amd/agesa/f14/Include/OptionMemory.h +++ b/src/vendorcode/amd/agesa/f14/Include/OptionMemory.h @@ -320,10 +320,22 @@ BOOLEAN MemFDefRet ( BOOLEAN MemMDefRet ( IN MEM_MAIN_DATA_BLOCK *MMPtr ); + +BOOLEAN MemMDefRetFalse ( + IN MEM_MAIN_DATA_BLOCK *MMPtr + ); + /* Table Feature Default Return */ UINT8 MemFTableDefRet ( IN OUT MEM_TABLE_ALIAS **MTPtr ); + +BOOLEAN MemNIdentifyDimmConstructorRetDef ( + IN OUT MEM_NB_BLOCK *NBPtr, + IN OUT MEM_DATA_STRUCT *MemPtr, + IN UINT8 NodeID + ); + /* S3 Feature Default Return */ BOOLEAN MemFS3DefConstructorRet ( IN OUT VOID *S3NBPtr, diff --git a/src/vendorcode/amd/agesa/f14/Include/OptionMemoryInstall.h b/src/vendorcode/amd/agesa/f14/Include/OptionMemoryInstall.h index 2f41757e87..6072cd4d4c 100644 --- a/src/vendorcode/amd/agesa/f14/Include/OptionMemoryInstall.h +++ b/src/vendorcode/amd/agesa/f14/Include/OptionMemoryInstall.h @@ -314,74 +314,65 @@ BOOLEAN MemFS3DefConstructorRet ( * based upon the number of processor families that the BIOS will support. */ + extern MEM_FLOW_CFG MemMFlowDef; #if (OPTION_MEMCTLR_DR == TRUE) extern MEM_FLOW_CFG MemMFlowDr; #define MEM_MAIN_FLOW_CONTROL_PTR_Dr MemMFlowDr, #else - extern MEM_FLOW_CFG MemMFlowDef; #define MEM_MAIN_FLOW_CONTROL_PTR_Dr MemMFlowDef, #endif #if (OPTION_MEMCTLR_DA == TRUE) extern MEM_FLOW_CFG MemMFlowDA; #define MEM_MAIN_FLOW_CONTROL_PTR_DA MemMFlowDA, #else - extern MEM_FLOW_CFG MemMFlowDef; #define MEM_MAIN_FLOW_CONTROL_PTR_DA MemMFlowDef, #endif #if (OPTION_MEMCTLR_HY == TRUE) extern MEM_FLOW_CFG MemMFlowHy; #define MEM_MAIN_FLOW_CONTROL_PTR_Hy MemMFlowHy, #else - extern MEM_FLOW_CFG MemMFlowDef; #define MEM_MAIN_FLOW_CONTROL_PTR_Hy MemMFlowDef, #endif #if (OPTION_MEMCTLR_OR == TRUE) extern MEM_FLOW_CFG MemMFlowOr; #define MEM_MAIN_FLOW_CONTROL_PTR_OR MemMFlowOr, #else - extern MEM_FLOW_CFG MemMFlowDef; #define MEM_MAIN_FLOW_CONTROL_PTR_OR MemMFlowDef, #endif #if (OPTION_MEMCTLR_LN == TRUE) extern MEM_FLOW_CFG MemMFlowLN; #define MEM_MAIN_FLOW_CONTROL_PTR_LN MemMFlowLN, #else - extern MEM_FLOW_CFG MemMFlowDef; #define MEM_MAIN_FLOW_CONTROL_PTR_LN MemMFlowDef, #endif #if (OPTION_MEMCTLR_C32 == TRUE) extern MEM_FLOW_CFG MemMFlowC32; #define MEM_MAIN_FLOW_CONTROL_PTR_C32 MemMFlowC32, #else - extern MEM_FLOW_CFG MemMFlowDef; #define MEM_MAIN_FLOW_CONTROL_PTR_C32 MemMFlowDef, #endif #if (OPTION_MEMCTLR_ON == TRUE) extern MEM_FLOW_CFG MemMFlowON; #define MEM_MAIN_FLOW_CONTROL_PTR_ON MemMFlowON, #else - extern MEM_FLOW_CFG MemMFlowDef; #define MEM_MAIN_FLOW_CONTROL_PTR_ON MemMFlowDef, #endif #if (OPTION_MEMCTLR_Ni == TRUE) extern MEM_FLOW_CFG MemMFlowDA; #define MEM_MAIN_FLOW_CONTROL_PTR_Ni MemMFlowDA, #else - extern MEM_FLOW_CFG MemMFlowDef; #define MEM_MAIN_FLOW_CONTROL_PTR_Ni MemMFlowDef, #endif #if (OPTION_MEMCTLR_RB == TRUE) extern MEM_FLOW_CFG MemMFlowRb; #define MEM_MAIN_FLOW_CONTROL_PTR_RB MemMFlowRb, #else - extern MEM_FLOW_CFG MemMFlowDef; #define MEM_MAIN_FLOW_CONTROL_PTR_RB MemMFlowDef, #endif #if (OPTION_MEMCTLR_PH == TRUE) extern MEM_FLOW_CFG MemMFlowPh; #define MEM_MAIN_FLOW_CONTROL_PTR_PH MemMFlowPh, #else - extern MEM_FLOW_CFG MemMFlowDef; #define MEM_MAIN_FLOW_CONTROL_PTR_PH MemMFlowDef, #endif @@ -464,13 +455,6 @@ BOOLEAN MemFS3DefConstructorRet ( #define MEM_FEATURE_ECCX8 MemMDefRet #endif - #if (OPTION_EMP == TRUE) - extern OPTION_MEM_FEATURE_NB MemFInitEMP; - #define MEM_FEATURE_EMP MemFInitEMP - #else - #define MEM_FEATURE_EMP MemFDefRet - #endif - extern OPTION_MEM_FEATURE_MAIN MemMMctMemClr; #define MEM_MAIN_FEATURE_MEM_CLEAR MemMMctMemClr @@ -505,11 +489,11 @@ BOOLEAN MemFS3DefConstructorRet ( extern OPTION_MEM_FEATURE_MAIN MemMUmaAlloc; #define MEM_MAIN_FEATURE_UMAALLOC MemMUmaAlloc + extern OPTION_MEM_FEATURE_MAIN MemMStandardTraining; #if (OPTION_PARALLEL_TRAINING == TRUE) extern OPTION_MEM_FEATURE_MAIN MemMParallelTraining; #define MEM_MAIN_FEATURE_TRAINING MemMParallelTraining #else - extern OPTION_MEM_FEATURE_MAIN MemMStandardTraining; #define MEM_MAIN_FEATURE_TRAINING MemMStandardTraining #endif @@ -555,7 +539,7 @@ BOOLEAN MemFS3DefConstructorRet ( #define MEM_TECH_FEATURE_HW_DRAMINIT MemTFeatDef #endif #if (OPTION_SW_DRAM_INIT == TRUE) - extern MEM_TECH_FEAT MemTDramInitSw3; +// extern MEM_TECH_FEAT MemTDramInitSw3; #define MEM_TECH_FEATURE_SW_DRAMINIT MemTDramInitSw3 #else #define MEM_TECH_FEATURE_SW_DRAMINIT MemTFeatDef @@ -956,7 +940,6 @@ BOOLEAN MemFS3DefConstructorRet ( #undef MEM_MAIN_FEATURE_TRAINING #undef MEM_FEATURE_TRAINING - extern OPTION_MEM_FEATURE_MAIN MemMStandardTraining; #define MEM_MAIN_FEATURE_TRAINING MemMStandardTraining extern OPTION_MEM_FEATURE_NB MemFStandardTraining; #define MEM_FEATURE_TRAINING MemFStandardTraining @@ -2284,9 +2267,9 @@ BOOLEAN MemFS3DefConstructorRet ( TECH_TRAIN_OPT_SW_RD_WR_POS_DDR3, TECH_TRAIN_MAX_RD_LAT_DDR3 }; - extern OPTION_MEM_FEATURE_NB MemNDQSTiming3Nb; +// extern OPTION_MEM_FEATURE_NB MemNDQSTiming3Nb; #define NB_TRAIN_FLOW_DDR3 MemNDQSTiming3Nb - extern OPTION_MEM_FEATURE_NB memNSequenceDDR3Nb; +// extern OPTION_MEM_FEATURE_NB memNSequenceDDR3Nb; #define MEM_TECH_ENABLE_TRAINING_SEQUENCE_DDR3_ON {MEM_TECH_TRAIN_SEQUENCE_STRUCT_VERSION,memNSequenceDDR3Nb, memNEnableTrainSequenceON, &memTechTrainingFeatSequenceDDR3ON }, #else #undef TECH_TRAIN_ENTER_HW_TRN_DDR3 @@ -3253,9 +3236,9 @@ BOOLEAN MemFS3DefConstructorRet ( NULL }; CONST UINTN SIZE_OF_PLATFORM = (sizeof (memPlatformTypeInstalled) / sizeof (MEM_PLATFORM_CFG*)); - #if SIZE_OF_PLATFORM > MAX_PLATFORM_TYPES - #error Size of memPlatformTypeInstalled array larger than MAX_PLATFORM_TYPES - #endif +// #if SIZE_OF_PLATFORM > MAX_PLATFORM_TYPES +// #error Size of memPlatformTypeInstalled array larger than MAX_PLATFORM_TYPES +// #endif /*--------------------------------------------------------------------------------------------------- * EXTRACTABLE PLATFORM SPECIFIC CONFIGURATION diff --git a/src/vendorcode/amd/agesa/f14/Include/OptionMemoryRecoveryInstall.h b/src/vendorcode/amd/agesa/f14/Include/OptionMemoryRecoveryInstall.h index 20199473c4..91435dc1ce 100644 --- a/src/vendorcode/amd/agesa/f14/Include/OptionMemoryRecoveryInstall.h +++ b/src/vendorcode/amd/agesa/f14/Include/OptionMemoryRecoveryInstall.h @@ -579,7 +579,7 @@ * *--------------------------------------------------------------------------------------------------- */ - MEM_NB_SUPPORT MemRecNBInstalled[] = { + MEM_NB_SUPPORT* MemRecNBInstalled[] = { NULL }; /*---------------------------------------------------------------------- diff --git a/src/vendorcode/amd/agesa/f14/Include/OptionPstateInstall.h b/src/vendorcode/amd/agesa/f14/Include/OptionPstateInstall.h index 11ae4d3cfe..b289910429 100644 --- a/src/vendorcode/amd/agesa/f14/Include/OptionPstateInstall.h +++ b/src/vendorcode/amd/agesa/f14/Include/OptionPstateInstall.h @@ -101,7 +101,7 @@ #error BLDOPT: Option not defined: "OPTION_ACPI_PSTATES" #endif #if (OPTION_ACPI_PSTATES == TRUE) - OPTION_SSDT_FEATURE GenerateSsdt; +// OPTION_SSDT_FEATURE GenerateSsdt; #define USER_SSDT_MAIN GenerateSsdt #ifndef OPTION_MULTISOCKET #error BLDOPT: Option not defined: "OPTION_MULTISOCKET" diff --git a/src/vendorcode/amd/agesa/f14/Include/PlatformInstall.h b/src/vendorcode/amd/agesa/f14/Include/PlatformInstall.h index 31a311b865..d2d032896f 100644 --- a/src/vendorcode/amd/agesa/f14/Include/PlatformInstall.h +++ b/src/vendorcode/amd/agesa/f14/Include/PlatformInstall.h @@ -11,7 +11,7 @@ * @xrefitem bom "File Content Label" "Release Content" * @e project: AGESA * @e sub-project: Core - * @e \$Revision: 41504 $ @e \$Date: 2010-11-05 21:59:13 +0800 (Fri, 05 Nov 2010) $ + * @e \$Revision: 47417 $ @e \$Date: 2011-02-18 12:48:20 -0700 (Fri, 18 Feb 2011) $ */ /* ***************************************************************************** @@ -79,7 +79,7 @@ VOLATILE AMD_MODULE_HEADER mCpuModuleID = { //ModuleHeaderSignature // Remove 'DOM$' as temp solution before update BinUtil.exe , - '0000', + Int32FromChar ('0', '0', '0', '0'), //ModuleIdentifier[8] AGESA_ID, //ModuleVersion[12] @@ -1015,6 +1015,8 @@ VOLATILE AMD_MODULE_HEADER mCpuModuleID = { #define OPTION_GFX_RECOVERY TRUE #undef OPTION_C6_STATE #define OPTION_C6_STATE TRUE + #undef OPTION_CPB + #define OPTION_CPB TRUE #undef OPTION_IO_CSTATE #define OPTION_IO_CSTATE TRUE #undef OPTION_S3SCRIPT @@ -1937,6 +1939,12 @@ CONST UINT32 ROMDATA AmdPlatformTypeCgf = CFG_AMD_PLATFORM_TYPE; #define CFG_GFX_LVDS_SPREAD_SPECTRUM_RATE 0 #endif +#ifdef BLDCFG_PCIE_REFCLK_SPREAD_SPECTRUM + #define CFG_PCIE_REFCLK_SPREAD_SPECTRUM BLDCFG_PCIE_REFCLK_SPREAD_SPECTRUM +#else + #define CFG_PCIE_REFCLK_SPREAD_SPECTRUM 0 +#endif + #ifdef BLDCFG_CFG_TEMP_PCIE_MMIO_BASE_ADDRESS #define CFG_TEMP_PCIE_MMIO_BASE_ADDRESS BLDCFG_CFG_TEMP_PCIE_MMIO_BASE_ADDRESS #else @@ -1963,6 +1971,35 @@ CONST UINT32 ROMDATA AmdPlatformTypeCgf = CFG_AMD_PLATFORM_TYPE; #endif #endif +#ifdef BLDCFG_LVDS_MISC_888_FPDI_MODE + #define CFG_LVDS_MISC_888_FPDI_MODE BLDCFG_LVDS_MISC_888_FPDI_MODE +#else + #define CFG_LVDS_MISC_888_FPDI_MODE FALSE +#endif + +#ifdef BLDCFG_LVDS_MISC_DL_CH_SWAP + #define CFG_LVDS_MISC_DL_CH_SWAP BLDCFG_LVDS_MISC_DL_CH_SWAP +#else + #define CFG_LVDS_MISC_DL_CH_SWAP FALSE +#endif + +#ifdef BLDCFG_LVDS_MISC_VSYNC_ACTIVE_LOW + #define CFG_LVDS_MISC_VSYNC_ACTIVE_LOW BLDCFG_LVDS_MISC_VSYNC_ACTIVE_LOW +#else + #define CFG_LVDS_MISC_VSYNC_ACTIVE_LOW FALSE +#endif + +#ifdef BLDCFG_LVDS_MISC_HSYNC_ACTIVE_LOW + #define CFG_LVDS_MISC_HSYNC_ACTIVE_LOW BLDCFG_LVDS_MISC_HSYNC_ACTIVE_LOW +#else + #define CFG_LVDS_MISC_HSYNC_ACTIVE_LOW FALSE +#endif + +#ifdef BLDCFG_LVDS_MISC_BLON_ACTIVE_LOW + #define CFG_LVDS_MISC_BLON_ACTIVE_LOW BLDCFG_LVDS_MISC_BLON_ACTIVE_LOW +#else + #define CFG_LVDS_MISC_BLON_ACTIVE_LOW FALSE +#endif /*--------------------------------------------------------------------------- * Processing the options: Third, perform the option cross checks *--------------------------------------------------------------------------*/ @@ -2281,6 +2318,14 @@ BUILD_OPT_CFG UserOptions = { CFG_GFX_LVDS_SPREAD_SPECTRUM, // CfgLvdsSpreadSpectrum CFG_GFX_LVDS_SPREAD_SPECTRUM_RATE, // CfgLvdsSpreadSpectrumRate + {{ + CFG_LVDS_MISC_888_FPDI_MODE, // CfgLvdsMiscControl + CFG_LVDS_MISC_DL_CH_SWAP, // CfgLvdsMiscControl + CFG_LVDS_MISC_VSYNC_ACTIVE_LOW, // CfgLvdsMiscControl + CFG_LVDS_MISC_HSYNC_ACTIVE_LOW, // CfgLvdsMiscControl + CFG_LVDS_MISC_BLON_ACTIVE_LOW, // CfgLvdsMiscControl + }}, + CFG_PCIE_REFCLK_SPREAD_SPECTRUM, // CfgPcieRefClkSpreadSpectrum 0, //reserved... }; @@ -2384,7 +2429,7 @@ CONST FUNCTION_PARAMS_INFO ROMDATA FuncParamsInfo[] = AMD_LATE_RUN_AP_TASK_HANDLE }, #endif - { 0, NULL } + { 0, 0, NULL } }; CONST UINTN InitializerCount = ((sizeof (FuncParamsInfo)) / (sizeof (FuncParamsInfo[0]))); @@ -2591,6 +2636,12 @@ CONST DISPATCH_TABLE ROMDATA ApDispatchTable[] = MAKE_DBG_STR (\nCfgLvdsSpreadSpectrum , CFG_GFX_LVDS_SPREAD_SPECTRUM), MAKE_DBG_STR (\nCfgLvdsSpreadSpectrumRate , CFG_GFX_LVDS_SPREAD_SPECTRUM_RATE), + MAKE_DBG_STR (\nCfgLvdsMiscControl.FpdiMode , CFG_LVDS_MISC_888_FPDI_MODE), + MAKE_DBG_STR (\nCfgLvdsMiscControl.DlChSwap , CFG_LVDS_MISC_DL_CH_SWAP), + MAKE_DBG_STR (\nCfgLvdsMiscControl.VsyncActiveLow , CFG_LVDS_MISC_VSYNC_ACTIVE_LOW), + MAKE_DBG_STR (\nCfgLvdsMiscControl.HsyncActiveLow , CFG_LVDS_MISC_HSYNC_ACTIVE_LOW), + MAKE_DBG_STR (\nCfgLvdsMiscControl.BLONActiveLow , CFG_LVDS_MISC_BLON_ACTIVE_LOW), + MAKE_DBG_STR (\nCfgPcieRefClkSpreadSpectrum , CFG_PCIE_REFCLK_SPREAD_SPECTRUM), #endif NULL }; diff --git a/src/vendorcode/amd/agesa/f14/Legacy/Proc/Dispatcher.c b/src/vendorcode/amd/agesa/f14/Legacy/Proc/Dispatcher.c index fed63ed525..64993b0217 100644 --- a/src/vendorcode/amd/agesa/f14/Legacy/Proc/Dispatcher.c +++ b/src/vendorcode/amd/agesa/f14/Legacy/Proc/Dispatcher.c @@ -107,7 +107,7 @@ AmdAgesaDispatcher ( // 2. Try next dispatcher if possible, and we have not already got status back if ((mCpuModuleID.NextBlock != NULL) && (Status == AGESA_UNSUPPORTED)) { - ModuleEntry = (MODULE_ENTRY) (UINT64) mCpuModuleID.NextBlock->ModuleDispatcher; + ModuleEntry = (MODULE_ENTRY) mCpuModuleID.NextBlock->ModuleDispatcher; if (ModuleEntry != NULL) { Status = (*ModuleEntry) (ConfigPtr); } @@ -119,10 +119,10 @@ AmdAgesaDispatcher ( ImageStart = ((AMD_CONFIG_PARAMS *)ConfigPtr)->AltImageBasePtr; ImageEnd = ImageStart + 4; // Locate/test image base that matches this component - AltImagePtr = LibAmdLocateImage ((VOID *) (UINT64)ImageStart, (VOID *) (UINT64)ImageEnd, 4096, AGESA_ID); + AltImagePtr = LibAmdLocateImage ((VOID *)ImageStart, (VOID *)ImageEnd, 4096, (CHAR8 *)AGESA_ID); if (AltImagePtr != NULL) { //Invoke alternative Image - ImageEntry = (IMAGE_ENTRY) ((UINT64) AltImagePtr + AltImagePtr->EntryPointAddress); + ImageEntry = (IMAGE_ENTRY) (AltImagePtr + AltImagePtr->EntryPointAddress); Status = (*ImageEntry) (ConfigPtr); } } diff --git a/src/vendorcode/amd/agesa/f14/Legacy/Proc/agesaCallouts.c b/src/vendorcode/amd/agesa/f14/Legacy/Proc/agesaCallouts.c index ffb712ef0b..350c8918a2 100644 --- a/src/vendorcode/amd/agesa/f14/Legacy/Proc/agesaCallouts.c +++ b/src/vendorcode/amd/agesa/f14/Legacy/Proc/agesaCallouts.c @@ -71,6 +71,12 @@ *---------------------------------------------------------------------------------------- */ +AGESA_STATUS +AgesaGetIdsData ( + IN UINTN Data, + IN OUT IDS_CALLOUT_STRUCT *IdsCalloutData + ); + /*---------------------------------------------------------------------------------------- * E X P O R T E D F U N C T I O N S *---------------------------------------------------------------------------------------- diff --git a/src/vendorcode/amd/agesa/f14/Legacy/Proc/hobTransfer.c b/src/vendorcode/amd/agesa/f14/Legacy/Proc/hobTransfer.c index d205b5488c..d3987fb5e2 100644 --- a/src/vendorcode/amd/agesa/f14/Legacy/Proc/hobTransfer.c +++ b/src/vendorcode/amd/agesa/f14/Legacy/Proc/hobTransfer.c @@ -58,7 +58,8 @@ #include "cpuCacheInit.h" #include "cpuFamilyTranslation.h" #include "heapManager.h" -#include "cpuLateInit.h" +//#include "cpuLateInit.h" +#include "cpuEnvInit.h" #include "Filecode.h" CODE_GROUP (G1_PEICC) RDATA_GROUP (G1_PEICC) @@ -179,8 +180,8 @@ CopyHeapToTempRamAtPost ( // Region above 1MB // Variable MTTR region // Get family specific cache Info - GetCpuServicesOfCurrentCore (&FamilySpecificServices, StdHeader); - FamilySpecificServices->GetCacheInfo (FamilySpecificServices, &CacheInfoPtr, &Ignored, StdHeader); + GetCpuServicesOfCurrentCore ((const CPU_SPECIFIC_SERVICES **)&FamilySpecificServices, StdHeader); + FamilySpecificServices->GetCacheInfo (FamilySpecificServices, (const VOID **)&CacheInfoPtr, &Ignored, StdHeader); // Find an empty MTRRphysBase/MTRRphysMask for (HeapRamVariableMtrr = AMD_MTRR_VARIABLE_HEAP_BASE; @@ -215,7 +216,7 @@ CopyHeapToTempRamAtPost ( HeapInCacheOffset = HeapManagerInCache->FirstActiveBufferOffset; HeapInCache = (BUFFER_NODE *) (BaseAddressInCache + HeapInCacheOffset); - BaseAddressInTempMem = (UINT8 *) UserOptions.CfgHeapDramAddress; + BaseAddressInTempMem = (UINT8 *) (UserOptions.CfgHeapDramAddress); HeapManagerInTempMem = (HEAP_MANAGER *) BaseAddressInTempMem; HeapInTempMem = (BUFFER_NODE *) (BaseAddressInTempMem + TotalSize); @@ -370,15 +371,15 @@ CopyHeapToMainRamAtPost ( // if address of heap in temp memory is above 1M, then we must used one variable MTRR. if (StdHeader->HeapBasePtr >= 0x100000) { // Find out which variable MTRR was used in CopyHeapToTempRamAtPost. - GetCpuServicesOfCurrentCore (&FamilySpecificServices, StdHeader); - FamilySpecificServices->GetCacheInfo (FamilySpecificServices, &CacheInfoPtr, &Ignored, StdHeader); + GetCpuServicesOfCurrentCore ((const CPU_SPECIFIC_SERVICES **)&FamilySpecificServices, StdHeader); + FamilySpecificServices->GetCacheInfo (FamilySpecificServices, (const VOID **)&CacheInfoPtr, &Ignored, StdHeader); for (HeapRamVariableMtrr = AMD_MTRR_VARIABLE_HEAP_BASE; HeapRamVariableMtrr >= AMD_MTRR_VARIABLE_BASE0; HeapRamVariableMtrr--) { LibAmdMsrRead (HeapRamVariableMtrr, &VariableMtrrBase, StdHeader); LibAmdMsrRead ((HeapRamVariableMtrr + 1), &VariableMtrrMask, StdHeader); - if ((VariableMtrrBase == (UINT64) (StdHeader->HeapBasePtr & CacheInfoPtr->HeapBaseMask)) && - (VariableMtrrMask == (UINT64) (CacheInfoPtr->VariableMtrrHeapMask & AMD_HEAP_MTRR_MASK))) { + if ((VariableMtrrBase == ((UINT64)(StdHeader->HeapBasePtr) & CacheInfoPtr->HeapBaseMask)) && + (VariableMtrrMask == (CacheInfoPtr->VariableMtrrHeapMask & AMD_HEAP_MTRR_MASK))) { break; } } diff --git a/src/vendorcode/amd/agesa/f14/Legacy/agesa.inc b/src/vendorcode/amd/agesa/f14/Legacy/agesa.inc index 65dd0ef7fa..84f9ec7bf1 100644 --- a/src/vendorcode/amd/agesa/f14/Legacy/agesa.inc +++ b/src/vendorcode/amd/agesa/f14/Legacy/agesa.inc @@ -9,7 +9,7 @@ ; * @xrefitem bom "File Content Label" "Release Content" ; * @e project: AGESA ; * @e sub-project: Include -; * @e \$Revision: 41505 $ @e \$Date: 2010-11-05 22:06:20 +0800 (Fri, 05 Nov 2010) $ +; * @e \$Revision: 47417 $ @e \$Date: 2011-02-18 12:48:20 -0700 (Fri, 18 Feb 2011) $ ; ;***************************************************************************** ; @@ -714,6 +714,23 @@ PCIE_HDP_TYPE TEXTEQU <DWORD> ;---------------------------------------------------------------------------- ; +; LVDS Misc Control Field +LVDS_MISC_CONTROL_FIELD STRUCT + FpdiMode UINT8 ? + ;IN UINT8 FpdiMode:1; + ;IN UINT8 DlChSwap:1; + ;IN UINT8 VsyncActiveLow:1; + ;IN UINT8 HsyncActiveLow:1; + ;IN UINT8 BLONActiveLow:1; + ;IN UINT8 Reserved:3; +LVDS_MISC_CONTROL_FIELD ENDS + +; LVDS Misc Control +LVDS_MISC_CONTROL UNION + Field LVDS_MISC_CONTROL_FIELD {} + Value UINT8 ? +LVDS_MISC_CONTROL ENDS + ; Configuration settings for GNB. GNB_ENV_CONFIGURATION STRUCT Gnb3dStereoPinIndex UINT8 ? ;< 3D Stereo Pin ID. @@ -726,6 +743,8 @@ GNB_ENV_CONFIGURATION STRUCT ; @li 6 = Use processor pin HPD6 LvdsSpreadSpectrum UINT16 ? ; Spread spectrum value in 0.01 % LvdsSpreadSpectrumRate UINT16 ? ; Spread spectrum frequency used by SS hardware logic in unit of 10Hz, 0 - default frequency 40kHz + LvdsMiscControl LVDS_MISC_CONTROL {} ; This item configures LVDS swap/Hsync/Vsync/BLON + PcieRefClkSpreadSpectrum UINT16 ? ; Spread spectrum value in 0.01 % GNB_ENV_CONFIGURATION ENDS ; GNB configuration info @@ -1916,6 +1935,8 @@ BUILD_OPT_CFG STRUCT CfgGnbPcieSSID UINT32 ? ; < Gnb PCIe SSID CfgLvdsSpreadSpectrum UINT16 ? ; < Lvds Spread Spectrum. Build-time customizable only CfgLvdsSpreadSpectrumRate UINT16 ? ; < Lvds Spread Spectrum Rate. Build-time customizable only + CfgLvdsMiscControl LVDS_MISC_CONTROL {}; THe LVDS Misc control + CfgPcieRefClkSpreadSpectrum UINT16 ? ; PCIe Reference Clock Spread Spectrum Reserved BOOLEAN ? ; < reserved... BUILD_OPT_CFG ENDS @@ -2143,6 +2164,7 @@ TYPE17_DMI_INFO STRUCT PartNumber CHAR8 (19) DUP (?) ; < Part Number. Attributes UINT8 ? ; < Bits 7-4: Reserved, Bits 3-0: rank. ExtSize UINT32 ? ; < Extended Size. + ConfigSpeed UINT16 ? ; < Configured memory clock speed TYPE17_DMI_INFO ENDS ; Memory DMI Type 17 and 20 - for memory use @@ -2169,6 +2191,7 @@ MEM_DMI_INFO STRUCT EndingAddr UINT32 ? ; ///< The handle, or instance number, associated with ; ///< the Memory Device structure to which this address ; ///< range is mapped. + ConfigSpeed UINT16 ? ; ///< Configured memory clock speed MEM_DMI_INFO ENDS ; DMI Type 19 - Memory Array Mapped Address diff --git a/src/vendorcode/amd/agesa/f14/Lib/amdlib.c b/src/vendorcode/amd/agesa/f14/Lib/amdlib.c index 3fc5112f4f..31b3f1ea69 100644 --- a/src/vendorcode/amd/agesa/f14/Lib/amdlib.c +++ b/src/vendorcode/amd/agesa/f14/Lib/amdlib.c @@ -9,7 +9,7 @@ * @xrefitem bom "File Content Label" "Release Content" * @e project: AGESA * @e sub-project: Lib - * @e \$Revision: 35136 $ @e \$Date: 2010-07-16 11:29:48 +0800 (Fri, 16 Jul 2010) $ + * @e \$Revision: 44325 $ @e \$Date: 2010-12-22 03:29:53 -0700 (Wed, 22 Dec 2010) $ * */ /* diff --git a/src/vendorcode/amd/agesa/f14/Makefile.inc b/src/vendorcode/amd/agesa/f14/Makefile.inc index dc33dee046..6a266ec72d 100644 --- a/src/vendorcode/amd/agesa/f14/Makefile.inc +++ b/src/vendorcode/amd/agesa/f14/Makefile.inc @@ -2,7 +2,7 @@ # # Copyright (c) 2011, Advanced Micro Devices, Inc. # All rights reserved. -# +# # Redistribution and use in source and binary forms, with or without # modification, are permitted provided that the following conditions are met: # * Redistributions of source code must retain the above copyright @@ -13,7 +13,7 @@ # * Neither the name of Advanced Micro Devices, Inc. nor the names of # its contributors may be used to endorse or promote products derived # from this software without specific prior written permission. -# +# # THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND # ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED # WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE @@ -24,7 +24,7 @@ # ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT # (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS # SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -# +# #***************************************************************************** # AGESA V5 Files @@ -36,19 +36,16 @@ AGESA_INC += -I$(AGESA_ROOT)/Include AGESA_INC += -I$(AGESA_ROOT)/Lib AGESA_INC += -I$(AGESA_ROOT)/Legacy AGESA_INC += -I$(AGESA_ROOT)/Proc/Common -AGESA_INC += -I$(AGESA_ROOT)/Proc/HT AGESA_INC += -I$(AGESA_ROOT)/Proc/CPU -AGESA_INC += -I$(AGESA_ROOT)/Proc/CPU/Feature AGESA_INC += -I$(AGESA_ROOT)/Proc/CPU/Family AGESA_INC += -I$(AGESA_ROOT)/Proc/CPU/Family/0x14 AGESA_INC += -I$(AGESA_ROOT)/Proc/CPU/Family/0x14/ON -AGESA_INC += -I$(AGESA_ROOT)/Proc/Mem -AGESA_INC += -I$(AGESA_ROOT)/Proc/Mem/NB/ON -AGESA_INC += -I$(AGESA_ROOT)/Proc/IDS -AGESA_INC += -I$(AGESA_ROOT)/Proc/IDS/Family -AGESA_INC += -I$(AGESA_ROOT)/Proc/IDS/Family/0x14 +AGESA_INC += -I$(AGESA_ROOT)/Proc/CPU/Feature AGESA_INC += -I$(AGESA_ROOT)/Proc/GNB AGESA_INC += -I$(AGESA_ROOT)/Proc/GNB/Common +AGESA_INC += -I$(AGESA_ROOT)/Proc/GNB/Gfx +AGESA_INC += -I$(AGESA_ROOT)/Proc/GNB/Gfx/Family +AGESA_INC += -I$(AGESA_ROOT)/Proc/GNB/Modules/GnbCommonLib AGESA_INC += -I$(AGESA_ROOT)/Proc/GNB/Nb AGESA_INC += -I$(AGESA_ROOT)/Proc/GNB/Nb/Family AGESA_INC += -I$(AGESA_ROOT)/Proc/GNB/Nb/Family/0x14 @@ -57,8 +54,10 @@ AGESA_INC += -I$(AGESA_ROOT)/Proc/GNB/PCIe AGESA_INC += -I$(AGESA_ROOT)/Proc/GNB/PCIe/Family AGESA_INC += -I$(AGESA_ROOT)/Proc/GNB/PCIe/Family/0x14 AGESA_INC += -I$(AGESA_ROOT)/Proc/GNB/PCIe/Feature -AGESA_INC += -I$(AGESA_ROOT)/Proc/GNB/Gfx -AGESA_INC += -I$(AGESA_ROOT)/Proc/GNB/Gfx/Family +AGESA_INC += -I$(AGESA_ROOT)/Proc/HT +AGESA_INC += -I$(AGESA_ROOT)/Proc/IDS +AGESA_INC += -I$(AGESA_ROOT)/Proc/Mem +AGESA_INC += -I$(AGESA_ROOT)/Proc/Mem/NB/ON AGESA_INC += -I$(AGESA_ROOT)/Proc/Recovery/GNB AGESA_INC += -I$(AGESA_ROOT)/Proc/Recovery/CPU AGESA_INC += -I$(AGESA_ROOT)/Proc/Recovery/Mem diff --git a/src/vendorcode/amd/agesa/f14/Porting.h b/src/vendorcode/amd/agesa/f14/Porting.h index 4550c86c64..ed06802f0e 100644 --- a/src/vendorcode/amd/agesa/f14/Porting.h +++ b/src/vendorcode/amd/agesa/f14/Porting.h @@ -226,6 +226,7 @@ #define VOLATILE volatile #define TRUE 1 #define FALSE 0 +// #undef CONST #define CONST const #define ROMDATA #define CALLCONV @@ -267,10 +268,6 @@ #ifndef NULL #define NULL (void *)0 #endif -#ifdef ROMDATA -//#undef ROMDATA -#endif -//#define ROMDATA __attribute__ ((section("rom.data")) #else // ----------------------------------------------------------------------- diff --git a/src/vendorcode/amd/agesa/f14/Proc/CPU/Family/0x10/F10IoCstate.c b/src/vendorcode/amd/agesa/f14/Proc/CPU/Family/0x10/F10IoCstate.c index d6b1443ff0..4905e77aeb 100644 --- a/src/vendorcode/amd/agesa/f14/Proc/CPU/Family/0x10/F10IoCstate.c +++ b/src/vendorcode/amd/agesa/f14/Proc/CPU/Family/0x10/F10IoCstate.c @@ -108,19 +108,19 @@ F10InitializeIoCstate ( IN AMD_CONFIG_PARAMS *StdHeader ) { - UINT64 MsrRegister; + UINT64 MsrReg; AP_TASK TaskPtr; if ((EntryPoint & CPU_FEAT_AFTER_PM_INIT) != 0) { // Initialize MSRC001_0073[CstateAddr] on each core to a region of // the IO address map with 8 consecutive available addresses. - MsrRegister = 0; + MsrReg = 0; - ((CSTATE_ADDRESS_MSR *) &MsrRegister)->CstateAddr = PlatformConfig->CStateIoBaseAddress; + ((CSTATE_ADDRESS_MSR *) &MsrReg)->CstateAddr = PlatformConfig->CStateIoBaseAddress; TaskPtr.FuncAddress.PfApTaskI = F10InitializeIoCstateOnCore; TaskPtr.DataTransfer.DataSizeInDwords = 2; - TaskPtr.DataTransfer.DataPtr = &MsrRegister; + TaskPtr.DataTransfer.DataPtr = &MsrReg; TaskPtr.DataTransfer.DataTransferFlags = 0; TaskPtr.ExeFlags = WAIT_FOR_CORE; ApUtilRunCodeOnAllLocalCoresAtEarly (&TaskPtr, StdHeader, NULL); @@ -264,7 +264,7 @@ F10IsIoCstateFeatureSupported ( IN AMD_CONFIG_PARAMS *StdHeader ) { - UINT64 MsrRegister; + UINT64 MsrReg; CPUID_DATA CpuId; CPU_LOGICAL_ID LogicalId; @@ -274,8 +274,8 @@ F10IsIoCstateFeatureSupported ( if ((LogicalId.Revision & AMD_F10_Ex) != 0) { LibAmdCpuidRead (AMD_CPUID_APM, &CpuId, StdHeader); if (((CpuId.EDX_Reg & 0x00000200) >> 9) == 1) { - LibAmdMsrRead (MSR_PATCH_LEVEL, &MsrRegister, StdHeader); - if ((MsrRegister & 0xffffffff) >= 0x010000BF) { + LibAmdMsrRead (MSR_PATCH_LEVEL, &MsrReg, StdHeader); + if ((MsrReg & 0xffffffff) >= 0x010000BF) { return TRUE; } } diff --git a/src/vendorcode/amd/agesa/f14/Proc/CPU/Family/0x10/F10PmNbCofVidInit.c b/src/vendorcode/amd/agesa/f14/Proc/CPU/Family/0x10/F10PmNbCofVidInit.c index 9b99f15f72..badc725c86 100644 --- a/src/vendorcode/amd/agesa/f14/Proc/CPU/Family/0x10/F10PmNbCofVidInit.c +++ b/src/vendorcode/amd/agesa/f14/Proc/CPU/Family/0x10/F10PmNbCofVidInit.c @@ -250,16 +250,16 @@ PmNbCofVidInitP0P1Core ( ) { UINT32 MsrAddress; - UINT64 MsrRegister; + UINT64 MsrReg; CPU_SPECIFIC_SERVICES *FamilySpecificServices; - GetCpuServicesOfCurrentCore (&FamilySpecificServices, StdHeader); - LibAmdMsrRead (MSR_COFVID_STS, &MsrRegister, StdHeader); - MsrAddress = (UINT32) ((((COFVID_STS_MSR *) &MsrRegister)->StartupPstate) + PS_REG_BASE); - LibAmdMsrRead (MsrAddress, &MsrRegister, StdHeader); - LibAmdMsrWrite ((UINT32) (PS_REG_BASE + 1), &MsrRegister, StdHeader); - ((PSTATE_MSR *) &MsrRegister)->NbVid = *(UINT8 *) NewNbVid; - LibAmdMsrWrite (PS_REG_BASE, &MsrRegister, StdHeader); + GetCpuServicesOfCurrentCore ((const CPU_SPECIFIC_SERVICES **)&FamilySpecificServices, StdHeader); + LibAmdMsrRead (MSR_COFVID_STS, &MsrReg, StdHeader); + MsrAddress = (UINT32) ((((COFVID_STS_MSR *) &MsrReg)->StartupPstate) + PS_REG_BASE); + LibAmdMsrRead (MsrAddress, &MsrReg, StdHeader); + LibAmdMsrWrite ((UINT32) (PS_REG_BASE + 1), &MsrReg, StdHeader); + ((PSTATE_MSR *) &MsrReg)->NbVid = *(UINT8 *) NewNbVid; + LibAmdMsrWrite (PS_REG_BASE, &MsrReg, StdHeader); FamilySpecificServices->TransitionPstate (FamilySpecificServices, (UINT8) 1, (BOOLEAN) FALSE, StdHeader); } @@ -283,16 +283,16 @@ PmNbCofVidInitWarmCore ( ) { UINT32 MsrAddress; - UINT64 MsrRegister; + UINT64 MsrReg; CPU_SPECIFIC_SERVICES *FamilySpecificServices; - GetCpuServicesOfCurrentCore (&FamilySpecificServices, StdHeader); + GetCpuServicesOfCurrentCore ((const CPU_SPECIFIC_SERVICES **)&FamilySpecificServices, StdHeader); for (MsrAddress = PS_REG_BASE; MsrAddress <= PS_MAX_REG; MsrAddress++) { - LibAmdMsrRead (MsrAddress, &MsrRegister, StdHeader); - if (((PSTATE_MSR *) &MsrRegister)->IddValue != 0) { - if ((((PSTATE_MSR *) &MsrRegister)->NbDid == 0) || ((NB_COF_VID_INIT_WARM *) FunctionData)->NbVidUpdateAll) { - ((PSTATE_MSR *) &MsrRegister)->NbVid = ((NB_COF_VID_INIT_WARM *) FunctionData)->NewNbVid; - LibAmdMsrWrite (MsrAddress, &MsrRegister, StdHeader); + LibAmdMsrRead (MsrAddress, &MsrReg, StdHeader); + if (((PSTATE_MSR *) &MsrReg)->IddValue != 0) { + if ((((PSTATE_MSR *) &MsrReg)->NbDid == 0) || ((NB_COF_VID_INIT_WARM *) FunctionData)->NbVidUpdateAll) { + ((PSTATE_MSR *) &MsrReg)->NbVid = ((NB_COF_VID_INIT_WARM *) FunctionData)->NewNbVid; + LibAmdMsrWrite (MsrAddress, &MsrReg, StdHeader); } } } diff --git a/src/vendorcode/amd/agesa/f14/Proc/CPU/Family/0x10/F10PmNbPstateInit.c b/src/vendorcode/amd/agesa/f14/Proc/CPU/Family/0x10/F10PmNbPstateInit.c index f69436f60b..fd40297aed 100644 --- a/src/vendorcode/amd/agesa/f14/Proc/CPU/Family/0x10/F10PmNbPstateInit.c +++ b/src/vendorcode/amd/agesa/f14/Proc/CPU/Family/0x10/F10PmNbPstateInit.c @@ -174,14 +174,14 @@ PmNbPstateInitCore ( ) { UINT32 MsrAddress; - UINT64 MsrRegister; + UINT64 MsrReg; for (MsrAddress = (PS_REG_BASE + ((NB_PSTATE_INIT *) NbPstateParams)->NbPstate); MsrAddress <= PS_MAX_REG; MsrAddress++) { - LibAmdMsrRead (MsrAddress, &MsrRegister, StdHeader); - if (((PSTATE_MSR *) &MsrRegister)->PsEnable == 1) { - ((PSTATE_MSR *) &MsrRegister)->NbDid = 1; - ((PSTATE_MSR *) &MsrRegister)->NbVid = ((NB_PSTATE_INIT *) NbPstateParams)->NbVid1; - LibAmdMsrWrite (MsrAddress, &MsrRegister, StdHeader); + LibAmdMsrRead (MsrAddress, &MsrReg, StdHeader); + if (((PSTATE_MSR *) &MsrReg)->PsEnable == 1) { + ((PSTATE_MSR *) &MsrReg)->NbDid = 1; + ((PSTATE_MSR *) &MsrReg)->NbVid = ((NB_PSTATE_INIT *) NbPstateParams)->NbVid1; + LibAmdMsrWrite (MsrAddress, &MsrReg, StdHeader); } } } diff --git a/src/vendorcode/amd/agesa/f14/Proc/CPU/Family/0x10/RevC/F10RevCHwC1e.c b/src/vendorcode/amd/agesa/f14/Proc/CPU/Family/0x10/RevC/F10RevCHwC1e.c index d92bf99026..3c3fa89463 100644 --- a/src/vendorcode/amd/agesa/f14/Proc/CPU/Family/0x10/RevC/F10RevCHwC1e.c +++ b/src/vendorcode/amd/agesa/f14/Proc/CPU/Family/0x10/RevC/F10RevCHwC1e.c @@ -134,18 +134,18 @@ F10InitializeHwC1e ( IN AMD_CONFIG_PARAMS *StdHeader ) { - UINT64 MsrRegister; + UINT64 MsrReg; AP_TASK TaskPtr; - MsrRegister = 0; - ((INTPEND_MSR *) &MsrRegister)->IoMsgAddr = PlatformConfig->C1ePlatformData; - ((INTPEND_MSR *) &MsrRegister)->IoRd = 1; - ((INTPEND_MSR *) &MsrRegister)->C1eOnCmpHalt = 1; - ((INTPEND_MSR *) &MsrRegister)->SmiOnCmpHalt = 0; + MsrReg = 0; + ((INTPEND_MSR *) &MsrReg)->IoMsgAddr = PlatformConfig->C1ePlatformData; + ((INTPEND_MSR *) &MsrReg)->IoRd = 1; + ((INTPEND_MSR *) &MsrReg)->C1eOnCmpHalt = 1; + ((INTPEND_MSR *) &MsrReg)->SmiOnCmpHalt = 0; TaskPtr.FuncAddress.PfApTaskI = F10InitializeHwC1eOnCore; TaskPtr.DataTransfer.DataSizeInDwords = 2; - TaskPtr.DataTransfer.DataPtr = &MsrRegister; + TaskPtr.DataTransfer.DataPtr = &MsrReg; TaskPtr.DataTransfer.DataTransferFlags = 0; TaskPtr.ExeFlags = WAIT_FOR_CORE; ApUtilRunCodeOnAllLocalCoresAtEarly (&TaskPtr, StdHeader, NULL); @@ -168,16 +168,16 @@ F10InitializeHwC1eOnCore ( IN AMD_CONFIG_PARAMS *StdHeader ) { - UINT64 MsrRegister; + UINT64 MsrReg; // Enable C1e LibAmdMsrWrite (MSR_INTPEND, (UINT64 *) IntPendMsr, StdHeader); // Set OS Visible Workaround Status BIT1 to indicate that C1e // is enabled. - LibAmdMsrRead (MSR_OSVW_Status, &MsrRegister, StdHeader); - MsrRegister |= BIT1; - LibAmdMsrWrite (MSR_OSVW_Status, &MsrRegister, StdHeader); + LibAmdMsrRead (MSR_OSVW_Status, &MsrReg, StdHeader); + MsrReg |= BIT1; + LibAmdMsrWrite (MSR_OSVW_Status, &MsrReg, StdHeader); } diff --git a/src/vendorcode/amd/agesa/f14/Proc/CPU/Family/0x10/RevC/F10RevCSwC1e.c b/src/vendorcode/amd/agesa/f14/Proc/CPU/Family/0x10/RevC/F10RevCSwC1e.c index 45a1aacfe4..64fa687207 100644 --- a/src/vendorcode/amd/agesa/f14/Proc/CPU/Family/0x10/RevC/F10RevCSwC1e.c +++ b/src/vendorcode/amd/agesa/f14/Proc/CPU/Family/0x10/RevC/F10RevCSwC1e.c @@ -126,19 +126,19 @@ F10InitializeSwC1e ( IN AMD_CONFIG_PARAMS *StdHeader ) { - UINT64 MsrRegister; + UINT64 MsrReg; AP_TASK TaskPtr; - MsrRegister = 0; - ((INTPEND_MSR *) &MsrRegister)->IoMsgAddr = PlatformConfig->C1ePlatformData1; - ((INTPEND_MSR *) &MsrRegister)->IoMsgData = PlatformConfig->C1ePlatformData2; - ((INTPEND_MSR *) &MsrRegister)->IoRd = 0; - ((INTPEND_MSR *) &MsrRegister)->C1eOnCmpHalt = 0; - ((INTPEND_MSR *) &MsrRegister)->SmiOnCmpHalt = 1; + MsrReg = 0; + ((INTPEND_MSR *) &MsrReg)->IoMsgAddr = PlatformConfig->C1ePlatformData1; + ((INTPEND_MSR *) &MsrReg)->IoMsgData = PlatformConfig->C1ePlatformData2; + ((INTPEND_MSR *) &MsrReg)->IoRd = 0; + ((INTPEND_MSR *) &MsrReg)->C1eOnCmpHalt = 0; + ((INTPEND_MSR *) &MsrReg)->SmiOnCmpHalt = 1; TaskPtr.FuncAddress.PfApTaskI = F10InitializeSwC1eOnCore; TaskPtr.DataTransfer.DataSizeInDwords = 2; - TaskPtr.DataTransfer.DataPtr = &MsrRegister; + TaskPtr.DataTransfer.DataPtr = &MsrReg; TaskPtr.DataTransfer.DataTransferFlags = 0; TaskPtr.ExeFlags = WAIT_FOR_CORE; ApUtilRunCodeOnAllLocalCoresAtEarly (&TaskPtr, StdHeader, NULL); @@ -161,16 +161,16 @@ F10InitializeSwC1eOnCore ( IN AMD_CONFIG_PARAMS *StdHeader ) { - UINT64 MsrRegister; + UINT64 MsrReg; // Enable C1e LibAmdMsrWrite (MSR_INTPEND, (UINT64 *) IntPendMsr, StdHeader); // Set OS Visible Workaround Status BIT1 to indicate that C1e // is enabled. - LibAmdMsrRead (MSR_OSVW_Status, &MsrRegister, StdHeader); - MsrRegister |= BIT1; - LibAmdMsrWrite (MSR_OSVW_Status, &MsrRegister, StdHeader); + LibAmdMsrRead (MSR_OSVW_Status, &MsrReg, StdHeader); + MsrReg |= BIT1; + LibAmdMsrWrite (MSR_OSVW_Status, &MsrReg, StdHeader); } diff --git a/src/vendorcode/amd/agesa/f14/Proc/CPU/Family/0x10/RevC/F10RevCUtilities.c b/src/vendorcode/amd/agesa/f14/Proc/CPU/Family/0x10/RevC/F10RevCUtilities.c index c422955712..9910fd9a71 100644 --- a/src/vendorcode/amd/agesa/f14/Proc/CPU/Family/0x10/RevC/F10RevCUtilities.c +++ b/src/vendorcode/amd/agesa/f14/Proc/CPU/Family/0x10/RevC/F10RevCUtilities.c @@ -320,7 +320,7 @@ F10CommonRevCGetNbPstateInfo ( UINT32 NbVid; UINT32 PciRegister; UINT32 ProductInfoRegister; - UINT64 MsrRegister; + UINT64 MsrReg; BOOLEAN PstateIsValid; PstateIsValid = TRUE; @@ -339,8 +339,8 @@ F10CommonRevCGetNbPstateInfo ( PciAddress->Address.Register = CPTC0_REG; LibAmdPciRead (AccessWidth32, *PciAddress, &PciRegister, StdHeader); NbFid = ((CLK_PWR_TIMING_CTRL_REGISTER *) &PciRegister)->NbFid; - LibAmdMsrRead (MSR_COFVID_STS, &MsrRegister, StdHeader); - NbVid = (UINT32) ((COFVID_STS_MSR *) &MsrRegister)->CurNbVid; + LibAmdMsrRead (MSR_COFVID_STS, &MsrReg, StdHeader); + NbVid = (UINT32) ((COFVID_STS_MSR *) &MsrReg)->CurNbVid; } else { NbFid = ((PRODUCT_INFO_REGISTER *) &ProductInfoRegister)->SinglePlaneNbFid; NbVid = ((PRODUCT_INFO_REGISTER *) &ProductInfoRegister)->SinglePlaneNbVid; diff --git a/src/vendorcode/amd/agesa/f14/Proc/CPU/Family/0x10/RevD/F10RevDHtAssist.c b/src/vendorcode/amd/agesa/f14/Proc/CPU/Family/0x10/RevD/F10RevDHtAssist.c index 33f7e040a5..ec7b09be6d 100644 --- a/src/vendorcode/amd/agesa/f14/Proc/CPU/Family/0x10/RevD/F10RevDHtAssist.c +++ b/src/vendorcode/amd/agesa/f14/Proc/CPU/Family/0x10/RevD/F10RevDHtAssist.c @@ -324,11 +324,11 @@ F10HookDisableCache ( IN AMD_CONFIG_PARAMS *StdHeader ) { - UINT64 MsrRegister; + UINT64 MsrReg; - LibAmdMsrRead (MSR_BU_CFG2, &MsrRegister, StdHeader); - MsrRegister |= BIT42; - LibAmdMsrWrite (MSR_BU_CFG2, &MsrRegister, StdHeader); + LibAmdMsrRead (MSR_BU_CFG2, &MsrReg, StdHeader); + MsrReg |= BIT42; + LibAmdMsrWrite (MSR_BU_CFG2, &MsrReg, StdHeader); } diff --git a/src/vendorcode/amd/agesa/f14/Proc/CPU/Family/0x10/RevD/F10RevDMsgBasedC1e.c b/src/vendorcode/amd/agesa/f14/Proc/CPU/Family/0x10/RevD/F10RevDMsgBasedC1e.c index 54e0d5fd83..80be0777f0 100644 --- a/src/vendorcode/amd/agesa/f14/Proc/CPU/Family/0x10/RevD/F10RevDMsgBasedC1e.c +++ b/src/vendorcode/amd/agesa/f14/Proc/CPU/Family/0x10/RevD/F10RevDMsgBasedC1e.c @@ -225,22 +225,22 @@ F10InitializeMsgBasedC1eOnCore ( IN AMD_CONFIG_PARAMS *StdHeader ) { - UINT64 MsrRegister; + UINT64 MsrReg; // Set MSRC001_0055[SmiOnCmpHalt] = 0, MSRC001_0055[C1eOnCmpHalt] = 0 - LibAmdMsrRead (MSR_INTPEND, &MsrRegister, StdHeader); - ((INTPEND_MSR *) &MsrRegister)->SmiOnCmpHalt = 0; - ((INTPEND_MSR *) &MsrRegister)->C1eOnCmpHalt = 0; - ((INTPEND_MSR *) &MsrRegister)->BmStsClrOnHltEn = 1; - ((INTPEND_MSR *) &MsrRegister)->IntrPndMsgDis = 0; - ((INTPEND_MSR *) &MsrRegister)->IntrPndMsg = 0; - ((INTPEND_MSR *) &MsrRegister)->IoMsgAddr = (UINT64) *((UINT32 *) BmStsAddress); - LibAmdMsrWrite (MSR_INTPEND, &MsrRegister, StdHeader); + LibAmdMsrRead (MSR_INTPEND, &MsrReg, StdHeader); + ((INTPEND_MSR *) &MsrReg)->SmiOnCmpHalt = 0; + ((INTPEND_MSR *) &MsrReg)->C1eOnCmpHalt = 0; + ((INTPEND_MSR *) &MsrReg)->BmStsClrOnHltEn = 1; + ((INTPEND_MSR *) &MsrReg)->IntrPndMsgDis = 0; + ((INTPEND_MSR *) &MsrReg)->IntrPndMsg = 0; + ((INTPEND_MSR *) &MsrReg)->IoMsgAddr = (UINT64) *((UINT32 *) BmStsAddress); + LibAmdMsrWrite (MSR_INTPEND, &MsrReg, StdHeader); // Set MSRC001_0015[HltXSpCycEn] = 1 - LibAmdMsrRead (MSR_HWCR, &MsrRegister, StdHeader); - MsrRegister |= BIT12; - LibAmdMsrWrite (MSR_HWCR, &MsrRegister, StdHeader); + LibAmdMsrRead (MSR_HWCR, &MsrReg, StdHeader); + MsrReg |= BIT12; + LibAmdMsrWrite (MSR_HWCR, &MsrReg, StdHeader); } /*---------------------------------------------------------------------------------------*/ diff --git a/src/vendorcode/amd/agesa/f14/Proc/CPU/Family/0x10/RevD/F10RevDUtilities.c b/src/vendorcode/amd/agesa/f14/Proc/CPU/Family/0x10/RevD/F10RevDUtilities.c index 1d46de6e3a..3a4d127c0c 100644 --- a/src/vendorcode/amd/agesa/f14/Proc/CPU/Family/0x10/RevD/F10RevDUtilities.c +++ b/src/vendorcode/amd/agesa/f14/Proc/CPU/Family/0x10/RevD/F10RevDUtilities.c @@ -309,7 +309,7 @@ F10CommonRevDGetNbPstateInfo ( ) { UINT32 PciRegister; - UINT64 MsrRegister; + UINT64 MsrReg; BOOLEAN PstateIsValid; PstateIsValid = FALSE; @@ -319,8 +319,8 @@ F10CommonRevDGetNbPstateInfo ( LibAmdPciRead (AccessWidth32, *PciAddress, &PciRegister, StdHeader); *FreqNumeratorInMHz = ((((CLK_PWR_TIMING_CTRL_REGISTER *) &PciRegister)->NbFid + 4) * 200); *FreqDivisor = 1; - LibAmdMsrRead (MSR_COFVID_STS, &MsrRegister, StdHeader); - *VoltageInuV = (1550000 - (12500 * ((UINT32) ((COFVID_STS_MSR *) &MsrRegister)->CurNbVid))); + LibAmdMsrRead (MSR_COFVID_STS, &MsrReg, StdHeader); + *VoltageInuV = (1550000 - (12500 * ((UINT32) ((COFVID_STS_MSR *) &MsrReg)->CurNbVid))); PstateIsValid = TRUE; } return PstateIsValid; diff --git a/src/vendorcode/amd/agesa/f14/Proc/CPU/Family/0x10/RevD/HY/F10HyMsrTables.c b/src/vendorcode/amd/agesa/f14/Proc/CPU/Family/0x10/RevD/HY/F10HyMsrTables.c index 82a52e3495..53904122af 100644 --- a/src/vendorcode/amd/agesa/f14/Proc/CPU/Family/0x10/RevD/HY/F10HyMsrTables.c +++ b/src/vendorcode/amd/agesa/f14/Proc/CPU/Family/0x10/RevD/HY/F10HyMsrTables.c @@ -87,12 +87,12 @@ STATIC CONST MSR_TYPE_ENTRY_INITIALIZER ROMDATA F10HyMsrRegisters[] = AMD_FAMILY_10, // CpuFamily AMD_F10_GT_B0 // CpuRevision }, - AMD_PF_ALL, // platformFeatures - { + {AMD_PF_ALL}, // platformFeatures + {{ MSR_LS_CFG, // MSR Address 0x0000000000000000, // OR Mask (1 << 1) // NAND Mask - } + }} }, // MSR_BU_CFG (0xC0011023) @@ -103,12 +103,12 @@ STATIC CONST MSR_TYPE_ENTRY_INITIALIZER ROMDATA F10HyMsrRegisters[] = AMD_FAMILY_10, // CpuFamily AMD_F10_GT_B0 // CpuRevision }, - AMD_PF_ALL, // platformFeatures - { + {AMD_PF_ALL}, // platformFeatures + {{ MSR_BU_CFG, // MSR Address (1 << 21), // OR Mask (1 << 21), // NAND Mask - } + }} }, // MSR_BU_CFG2 (0xC001102A) @@ -120,12 +120,12 @@ STATIC CONST MSR_TYPE_ENTRY_INITIALIZER ROMDATA F10HyMsrRegisters[] = AMD_FAMILY_10, // CpuFamily AMD_F10_GT_C0 // CpuRevision }, - AMD_PF_ALL, // platformFeatures - { + {AMD_PF_ALL}, // platformFeatures + {{ MSR_BU_CFG2, // MSR Address 0x0004000000000000, // OR Mask 0x0004000000000000, // NAND Mask - } + }} } }; diff --git a/src/vendorcode/amd/agesa/f14/Proc/CPU/Family/0x10/RevE/F10RevEUtilities.c b/src/vendorcode/amd/agesa/f14/Proc/CPU/Family/0x10/RevE/F10RevEUtilities.c index 635c424131..7a080d548a 100644 --- a/src/vendorcode/amd/agesa/f14/Proc/CPU/Family/0x10/RevE/F10RevEUtilities.c +++ b/src/vendorcode/amd/agesa/f14/Proc/CPU/Family/0x10/RevE/F10RevEUtilities.c @@ -285,7 +285,7 @@ F10CommonRevEGetNbPstateInfo ( ) { UINT32 PciRegister; - UINT64 MsrRegister; + UINT64 MsrReg; BOOLEAN PstateIsValid; PstateIsValid = FALSE; @@ -295,8 +295,8 @@ F10CommonRevEGetNbPstateInfo ( LibAmdPciRead (AccessWidth32, *PciAddress, &PciRegister, StdHeader); *FreqNumeratorInMHz = ((((CLK_PWR_TIMING_CTRL_REGISTER *) &PciRegister)->NbFid + 4) * 200); *FreqDivisor = 1; - LibAmdMsrRead (MSR_COFVID_STS, &MsrRegister, StdHeader); - *VoltageInuV = (1550000 - (12500 * ((UINT32) ((COFVID_STS_MSR *) &MsrRegister)->CurNbVid))); + LibAmdMsrRead (MSR_COFVID_STS, &MsrReg, StdHeader); + *VoltageInuV = (1550000 - (12500 * ((UINT32) ((COFVID_STS_MSR *) &MsrReg)->CurNbVid))); PstateIsValid = TRUE; } return PstateIsValid; diff --git a/src/vendorcode/amd/agesa/f14/Proc/CPU/Family/0x10/cpuF10Dmi.c b/src/vendorcode/amd/agesa/f14/Proc/CPU/Family/0x10/cpuF10Dmi.c index b2df819e0a..79a922e51c 100644 --- a/src/vendorcode/amd/agesa/f14/Proc/CPU/Family/0x10/cpuF10Dmi.c +++ b/src/vendorcode/amd/agesa/f14/Proc/CPU/Family/0x10/cpuF10Dmi.c @@ -122,7 +122,7 @@ DmiF10GetInfo ( CpuInfoPtr->BrandId.Model = (UINT8) (CpuId.EBX_Reg >> 4) & 0x7F; // bit 10:4 CpuInfoPtr->BrandId.String2 = (UINT8) (CpuId.EBX_Reg & 0xF); // bit 3:0 - GetCpuServicesOfCurrentCore (&FamilySpecificServices, StdHeader); + GetCpuServicesOfCurrentCore ((const CPU_SPECIFIC_SERVICES **)&FamilySpecificServices, StdHeader); CpuInfoPtr->TotalCoreNumber = FamilySpecificServices->GetNumberOfCoresForBrandstring (FamilySpecificServices, StdHeader); CpuInfoPtr->TotalCoreNumber--; @@ -239,7 +239,7 @@ DmiF10GetMaxSpeed ( PSTATE_CPU_FAMILY_SERVICES *FamilyServices; FamilyServices = NULL; - GetFeatureServicesOfCurrentCore (&PstateFamilyServiceTable, &FamilyServices, StdHeader); + GetFeatureServicesOfCurrentCore (&PstateFamilyServiceTable, (const VOID **)&FamilyServices, StdHeader); ASSERT (FamilyServices != NULL); NumBoostStates = 0; LibAmdCpuidRead (AMD_CPUID_APM, &CpuidData, StdHeader); diff --git a/src/vendorcode/amd/agesa/f14/Proc/CPU/Family/0x10/cpuF10EarlyInit.c b/src/vendorcode/amd/agesa/f14/Proc/CPU/Family/0x10/cpuF10EarlyInit.c index 671af0e94c..d9639c228f 100644 --- a/src/vendorcode/amd/agesa/f14/Proc/CPU/Family/0x10/cpuF10EarlyInit.c +++ b/src/vendorcode/amd/agesa/f14/Proc/CPU/Family/0x10/cpuF10EarlyInit.c @@ -165,7 +165,7 @@ F10PmAfterReset ( UINT32 Core; UINT32 AndMask; UINT32 OrMask; - UINT64 MsrRegister; + UINT64 MsrReg; PCI_ADDR PciAddress; AP_TASK TaskPtr; AGESA_STATUS IgnoredSts; @@ -179,8 +179,8 @@ F10PmAfterReset ( // Step 1 Modify F3xDC[PstateMaxVal] to reflect the lowest performance // P-state supported, as indicated in MSRC001_00[68:64][PstateEn] for (MsrAddr = PS_MAX_REG; MsrAddr > PS_REG_BASE; --MsrAddr) { - LibAmdMsrRead (MsrAddr, &MsrRegister, StdHeader); - if (((PSTATE_MSR *) &MsrRegister)->PsEnable == 1) { + LibAmdMsrRead (MsrAddr, &MsrReg, StdHeader); + if (((PSTATE_MSR *) &MsrReg)->PsEnable == 1) { break; } } @@ -227,7 +227,7 @@ F10PmAfterResetCore ( UINT32 Ignored; UINT32 PsMaxVal; UINT32 PciRegister; - UINT64 MsrRegister; + UINT64 MsrReg; UINT64 SavedMsr; UINT64 CurrentLimitMsr; PCI_ADDR PciAddress; @@ -238,13 +238,13 @@ F10PmAfterResetCore ( // Step 2 If MSR C001_0071[CurNbDid] = 0, set MSR C001_001F[GfxNbPstateDis] GetLogicalIdOfCurrentCore (&LogicalId, StdHeader); - GetCpuServicesFromLogicalId (&LogicalId, &FamilySpecificServices, StdHeader); + GetCpuServicesFromLogicalId (&LogicalId, (const CPU_SPECIFIC_SERVICES **)&FamilySpecificServices, StdHeader); if ((LogicalId.Revision & (AMD_F10_C3 | AMD_F10_DA_C2)) != 0) { - LibAmdMsrRead (MSR_COFVID_STS, &MsrRegister, StdHeader); - if (((COFVID_STS_MSR *) &MsrRegister)->CurNbDid == 0) { - LibAmdMsrRead (NB_CFG, &MsrRegister, StdHeader); - MsrRegister |= BIT62; - LibAmdMsrWrite (NB_CFG, &MsrRegister, StdHeader); + LibAmdMsrRead (MSR_COFVID_STS, &MsrReg, StdHeader); + if (((COFVID_STS_MSR *) &MsrReg)->CurNbDid == 0) { + LibAmdMsrRead (NB_CFG, &MsrReg, StdHeader); + MsrReg |= BIT62; + LibAmdMsrWrite (NB_CFG, &MsrReg, StdHeader); } } @@ -254,8 +254,8 @@ F10PmAfterResetCore ( PsMaxVal = (UINT32) (((PSTATE_CURLIM_MSR *) &CurrentLimitMsr)->PstateMaxVal); // Step 3 If MSRC001_0071[CurPstate] != F3xDC[PstateMaxVal], go to step 20 - LibAmdMsrRead (MSR_COFVID_STS, &MsrRegister, StdHeader); - if (((COFVID_STS_MSR *) &MsrRegister)->CurPstate != + LibAmdMsrRead (MSR_COFVID_STS, &MsrReg, StdHeader); + if (((COFVID_STS_MSR *) &MsrReg)->CurPstate != ((PSTATE_CURLIM_MSR *) &CurrentLimitMsr)->PstateMaxVal) { GoToStep = STEP20; } else { @@ -282,8 +282,8 @@ F10PmAfterResetCore ( // Step 7 Copy the P-state register pointed to by F3xDC[PstateMaxVal] to the P-state // register pointed to by F3xDC[PstateMaxVal]+1 - LibAmdMsrRead ((MSR_PSTATE_0 + PsMaxVal), &MsrRegister, StdHeader); - LibAmdMsrWrite ((MSR_PSTATE_0 + (PsMaxVal + 1)), &MsrRegister, StdHeader); + LibAmdMsrRead ((MSR_PSTATE_0 + PsMaxVal), &MsrReg, StdHeader); + LibAmdMsrWrite ((MSR_PSTATE_0 + (PsMaxVal + 1)), &MsrReg, StdHeader); // Step 8 Write F3xDC[PstateMaxVal]+1 to F3xDC[PstateMaxVal] IdentifyCore (StdHeader, &Socket, &Module, &Ignored, &IgnoredSts); @@ -310,11 +310,11 @@ F10PmAfterResetCore ( // Step 13 If MSRC001_0071[CurNbDid] = 1, set MSRC001_001F[GfxNbPstateDis] if ((LogicalId.Revision & (AMD_F10_C3 | AMD_F10_DA_C2)) != 0) { - LibAmdMsrRead (MSR_COFVID_STS, &MsrRegister, StdHeader); - if (((COFVID_STS_MSR *) &MsrRegister)->CurNbDid == 1) { - LibAmdMsrRead (NB_CFG, &MsrRegister, StdHeader); - MsrRegister |= BIT62; - LibAmdMsrWrite (NB_CFG, &MsrRegister, StdHeader); + LibAmdMsrRead (MSR_COFVID_STS, &MsrReg, StdHeader); + if (((COFVID_STS_MSR *) &MsrReg)->CurNbDid == 1) { + LibAmdMsrRead (NB_CFG, &MsrReg, StdHeader); + MsrReg |= BIT62; + LibAmdMsrWrite (NB_CFG, &MsrReg, StdHeader); } } @@ -343,11 +343,11 @@ F10PmAfterResetCore ( // Step 19 If MSR C001_0071[CurNbDid] = 0, set MSR C001_001F[GfxNbPstateDis] if ((LogicalId.Revision & (AMD_F10_C3 | AMD_F10_DA_C2)) != 0) { - LibAmdMsrRead (MSR_COFVID_STS, &MsrRegister, StdHeader); - if (((COFVID_STS_MSR *) &MsrRegister)->CurNbDid == 0) { - LibAmdMsrRead (NB_CFG, &MsrRegister, StdHeader); - MsrRegister |= BIT62; - LibAmdMsrWrite (NB_CFG, &MsrRegister, StdHeader); + LibAmdMsrRead (MSR_COFVID_STS, &MsrReg, StdHeader); + if (((COFVID_STS_MSR *) &MsrReg)->CurNbDid == 0) { + LibAmdMsrRead (NB_CFG, &MsrReg, StdHeader); + MsrReg |= BIT62; + LibAmdMsrWrite (NB_CFG, &MsrReg, StdHeader); } } @@ -363,11 +363,11 @@ F10PmAfterResetCore ( // Step 22 If MSR C001_0071[CurNbDid] = 1, set MSR C001_001F[GfxNbPstateDis] and exit // the sequence if ((LogicalId.Revision & (AMD_F10_C3 | AMD_F10_DA_C2)) != 0) { - LibAmdMsrRead (MSR_COFVID_STS, &MsrRegister, StdHeader); - if (((COFVID_STS_MSR *) &MsrRegister)->CurNbDid == 1) { - LibAmdMsrRead (NB_CFG, &MsrRegister, StdHeader); - MsrRegister |= BIT62; - LibAmdMsrWrite (NB_CFG, &MsrRegister, StdHeader); + LibAmdMsrRead (MSR_COFVID_STS, &MsrReg, StdHeader); + if (((COFVID_STS_MSR *) &MsrReg)->CurNbDid == 1) { + LibAmdMsrRead (NB_CFG, &MsrReg, StdHeader); + MsrReg |= BIT62; + LibAmdMsrWrite (NB_CFG, &MsrReg, StdHeader); break; } } diff --git a/src/vendorcode/amd/agesa/f14/Proc/CPU/Family/0x10/cpuF10PowerCheck.c b/src/vendorcode/amd/agesa/f14/Proc/CPU/Family/0x10/cpuF10PowerCheck.c index 031a9a4d62..877a12260c 100644 --- a/src/vendorcode/amd/agesa/f14/Proc/CPU/Family/0x10/cpuF10PowerCheck.c +++ b/src/vendorcode/amd/agesa/f14/Proc/CPU/Family/0x10/cpuF10PowerCheck.c @@ -168,7 +168,7 @@ F10PmPwrCheck ( UINT32 OrMask; UINT32 PstateLimit; PCI_ADDR PciAddress; - UINT64 MsrRegister; + UINT64 MsrReg; AP_TASK TaskPtr; CPUID_DATA CpuidData; AGESA_STATUS IgnoredSts; @@ -182,8 +182,8 @@ F10PmPwrCheck ( // get the Max P-state value for (PsMaxVal = NM_PS_REG - 1; PsMaxVal != 0; --PsMaxVal) { - LibAmdMsrRead (PS_REG_BASE + PsMaxVal, &MsrRegister, StdHeader); - if (((PSTATE_MSR *) &MsrRegister)->PsEnable == 1) { + LibAmdMsrRead (PS_REG_BASE + PsMaxVal, &MsrReg, StdHeader); + if (((PSTATE_MSR *) &MsrReg)->PsEnable == 1) { break; } } @@ -331,17 +331,17 @@ F10PmPwrCheckCore ( UINT8 DisPsNum; UINT8 CurrentPs; UINT8 EnBsNum; - UINT64 MsrRegister; + UINT64 MsrReg; CPU_SPECIFIC_SERVICES *FamilySpecificServices; - GetCpuServicesOfCurrentCore (&FamilySpecificServices, StdHeader); + GetCpuServicesOfCurrentCore ((const CPU_SPECIFIC_SERVICES **)&FamilySpecificServices, StdHeader); PsMaxVal = (((PWRCHK_ERROR_DATA *) ErrorData)->HwPstateNumber - 1); DisPsNum = (((PWRCHK_ERROR_DATA *) ErrorData)->HwPstateNumber - ((PWRCHK_ERROR_DATA *) ErrorData)->AllowablePstateNumber); EnBsNum = ((PWRCHK_ERROR_DATA *) ErrorData)->NumberofBoostStates; - LibAmdMsrRead (MSR_PSTATE_STS, &MsrRegister, StdHeader); - CurrentPs = (UINT8) (((PSTATE_STS_MSR *) &MsrRegister)->CurPstate); + LibAmdMsrRead (MSR_PSTATE_STS, &MsrReg, StdHeader); + CurrentPs = (UINT8) (((PSTATE_STS_MSR *) &MsrReg)->CurPstate); if (((PWRCHK_ERROR_DATA *) ErrorData)->AllowablePstateNumber == 0) { @@ -413,9 +413,9 @@ F10PmPwrChkCopyPstate ( IN AMD_CONFIG_PARAMS *StdHeader ) { - UINT64 MsrRegister; + UINT64 MsrReg; - LibAmdMsrRead ((UINT32) (PS_REG_BASE + Src), &MsrRegister, StdHeader); - LibAmdMsrWrite ((UINT32) (PS_REG_BASE + Dest), &MsrRegister, StdHeader); + LibAmdMsrRead ((UINT32) (PS_REG_BASE + Src), &MsrReg, StdHeader); + LibAmdMsrWrite ((UINT32) (PS_REG_BASE + Dest), &MsrReg, StdHeader); } diff --git a/src/vendorcode/amd/agesa/f14/Proc/CPU/Family/0x10/cpuF10PowerPlane.c b/src/vendorcode/amd/agesa/f14/Proc/CPU/Family/0x10/cpuF10PowerPlane.c index 4011971498..6f6c2d0b12 100644 --- a/src/vendorcode/amd/agesa/f14/Proc/CPU/Family/0x10/cpuF10PowerPlane.c +++ b/src/vendorcode/amd/agesa/f14/Proc/CPU/Family/0x10/cpuF10PowerPlane.c @@ -183,7 +183,7 @@ F10CpuAmdPmPwrPlaneInit ( UINT32 AndMask; UINT32 OrMask; UINT32 ProcessorPackageType; - UINT64 MsrRegister; + UINT64 MsrReg; AP_TASK TaskPtr; AGESA_STATUS IgnoredSts; PLATFORM_FEATS Features; @@ -266,10 +266,10 @@ F10CpuAmdPmPwrPlaneInit ( OrMask = 0x00000000; ((POPUP_PSTATE_REGISTER *) &OrMask)->PopupEn = 0; ((POPUP_PSTATE_REGISTER *) &OrMask)->PopupPstate = ((CLK_PWR_TIMING_CTRL2_REGISTER *) &PciRegister)->PstateMaxVal; - LibAmdMsrRead ((((CLK_PWR_TIMING_CTRL2_REGISTER *) &PciRegister)->PstateMaxVal + PS_REG_BASE), &MsrRegister, StdHeader); - ((POPUP_PSTATE_REGISTER *) &OrMask)->PopupCpuVid = (UINT32) ((PSTATE_MSR *) &MsrRegister)->CpuVid; - ((POPUP_PSTATE_REGISTER *) &OrMask)->PopupCpuFid = (UINT32) ((PSTATE_MSR *) &MsrRegister)->CpuFid; - ((POPUP_PSTATE_REGISTER *) &OrMask)->PopupCpuDid = (UINT32) ((PSTATE_MSR *) &MsrRegister)->CpuDid; + LibAmdMsrRead ((((CLK_PWR_TIMING_CTRL2_REGISTER *) &PciRegister)->PstateMaxVal + PS_REG_BASE), &MsrReg, StdHeader); + ((POPUP_PSTATE_REGISTER *) &OrMask)->PopupCpuVid = (UINT32) ((PSTATE_MSR *) &MsrReg)->CpuVid; + ((POPUP_PSTATE_REGISTER *) &OrMask)->PopupCpuFid = (UINT32) ((PSTATE_MSR *) &MsrReg)->CpuFid; + ((POPUP_PSTATE_REGISTER *) &OrMask)->PopupCpuDid = (UINT32) ((PSTATE_MSR *) &MsrReg)->CpuDid; PciAddress.Address.Register = POPUP_PSTATE_REG; ModifyCurrentSocketPci (&PciAddress, AndMask, OrMask, StdHeader); @@ -278,7 +278,7 @@ F10CpuAmdPmPwrPlaneInit ( AndMask = 0xFFFFFFFF; ((CLK_PWR_TIMING_CTRL1_REGISTER *) &AndMask)->AltVidStart = 0; OrMask = 0x00000000; - ((CLK_PWR_TIMING_CTRL1_REGISTER *) &OrMask)->AltVidStart = (UINT32) ((PSTATE_MSR *) &MsrRegister)->CpuVid; + ((CLK_PWR_TIMING_CTRL1_REGISTER *) &OrMask)->AltVidStart = (UINT32) ((PSTATE_MSR *) &MsrReg)->CpuVid; ModifyCurrentSocketPci (&PciAddress, AndMask, OrMask, StdHeader); // Set up Altvid slam time @@ -323,20 +323,20 @@ F10PmPwrPlaneInitPviCore ( UINT32 MsrAddr; UINT32 NbVid; UINT32 CpuVid; - UINT64 MsrRegister; + UINT64 MsrReg; for (MsrAddr = PS_REG_BASE; MsrAddr <= PS_MAX_REG; MsrAddr++) { - LibAmdMsrRead (MsrAddr, &MsrRegister, StdHeader); - if (((PSTATE_MSR *) &MsrRegister)->PsEnable == (UINT64) 1) { - NbVid = (UINT32) (((PSTATE_MSR *) &MsrRegister)->NbVid); - CpuVid = (UINT32) (((PSTATE_MSR *) &MsrRegister)->CpuVid); + LibAmdMsrRead (MsrAddr, &MsrReg, StdHeader); + if (((PSTATE_MSR *) &MsrReg)->PsEnable == (UINT64) 1) { + NbVid = (UINT32) (((PSTATE_MSR *) &MsrReg)->NbVid); + CpuVid = (UINT32) (((PSTATE_MSR *) &MsrReg)->CpuVid); if (NbVid != CpuVid) { if (NbVid > CpuVid) { NbVid = CpuVid; } - ((PSTATE_MSR *) &MsrRegister)->NbVid = NbVid; - ((PSTATE_MSR *) &MsrRegister)->CpuVid = NbVid; - LibAmdMsrWrite (MsrAddr, &MsrRegister, StdHeader); + ((PSTATE_MSR *) &MsrReg)->NbVid = NbVid; + ((PSTATE_MSR *) &MsrReg)->CpuVid = NbVid; + LibAmdMsrWrite (MsrAddr, &MsrReg, StdHeader); } } } @@ -375,7 +375,7 @@ F10CalculateAltvidVSSlamTimeOnCore ( UINT8 PminVidCode; UINT32 MsrAddr; UINT32 PciRegister; - UINT64 MsrRegister; + UINT64 MsrReg; PCI_ADDR LocalPciAddress; // Calculate Slam Time @@ -384,17 +384,17 @@ F10CalculateAltvidVSSlamTimeOnCore ( // decimals. // Get Pmin's index - LibAmdMsrRead (MSR_PSTATE_CURRENT_LIMIT, &MsrRegister, StdHeader); - MsrAddr = (UINT32) ((((PSTATE_CURLIM_MSR *) &MsrRegister)->PstateMaxVal) + PS_REG_BASE); + LibAmdMsrRead (MSR_PSTATE_CURRENT_LIMIT, &MsrReg, StdHeader); + MsrAddr = (UINT32) ((((PSTATE_CURLIM_MSR *) &MsrReg)->PstateMaxVal) + PS_REG_BASE); // Get Pmin's VID - LibAmdMsrRead (MsrAddr, &MsrRegister, StdHeader); - PminVidCode = (UINT8) (((PSTATE_MSR *) &MsrRegister)->CpuVid); + LibAmdMsrRead (MsrAddr, &MsrReg, StdHeader); + PminVidCode = (UINT8) (((PSTATE_MSR *) &MsrReg)->CpuVid); // If SVI, we only care about CPU VID. // If PVI, determine the higher voltage b/t NB and CPU if (PviModeFlag) { - NbVid = (UINT8) (((PSTATE_MSR *) &MsrRegister)->NbVid); + NbVid = (UINT8) (((PSTATE_MSR *) &MsrReg)->NbVid); if (PminVidCode > NbVid) { PminVidCode = NbVid; } diff --git a/src/vendorcode/amd/agesa/f14/Proc/CPU/Family/0x10/cpuF10Pstate.c b/src/vendorcode/amd/agesa/f14/Proc/CPU/Family/0x10/cpuF10Pstate.c index ed476a166d..8a2a381510 100644 --- a/src/vendorcode/amd/agesa/f14/Proc/CPU/Family/0x10/cpuF10Pstate.c +++ b/src/vendorcode/amd/agesa/f14/Proc/CPU/Family/0x10/cpuF10Pstate.c @@ -308,13 +308,13 @@ F10GetPstateFrequency ( UINT8 TempValue; UINT32 CpuDid; UINT32 CpuFid; - UINT64 MsrRegister; + UINT64 MsrReg; ASSERT (StateNumber < NM_PS_REG); - LibAmdMsrRead (PS_REG_BASE + (UINT32) StateNumber, &MsrRegister, StdHeader); - ASSERT (((PSTATE_MSR *) &MsrRegister)->PsEnable == 1); - CpuDid = (UINT32) (((PSTATE_MSR *) &MsrRegister)->CpuDid); - CpuFid = (UINT32) (((PSTATE_MSR *) &MsrRegister)->CpuFid); + LibAmdMsrRead (PS_REG_BASE + (UINT32) StateNumber, &MsrReg, StdHeader); + ASSERT (((PSTATE_MSR *) &MsrReg)->PsEnable == 1); + CpuDid = (UINT32) (((PSTATE_MSR *) &MsrReg)->CpuDid); + CpuFid = (UINT32) (((PSTATE_MSR *) &MsrReg)->CpuFid); switch (CpuDid) { case 0: @@ -380,7 +380,7 @@ F10PstateLevelingCoreMsrModify ( PCI_ADDR PciAddress; CPU_SPECIFIC_SERVICES *FamilySpecificServices; - GetCpuServicesOfCurrentCore (&FamilySpecificServices, StdHeader); + GetCpuServicesOfCurrentCore ((const CPU_SPECIFIC_SERVICES **)&FamilySpecificServices, StdHeader); ASSERT (FamilySpecificServices != NULL); Ignored = 0; @@ -521,15 +521,15 @@ F10GetPstatePower ( UINT32 Power; PCI_ADDR PciAddress; UINT32 TempVar_a; - UINT64 MsrRegister; + UINT64 MsrReg; AGESA_STATUS IgnoredSts; ASSERT (StateNumber < NM_PS_REG); - LibAmdMsrRead (PS_REG_BASE + (UINT32) StateNumber, &MsrRegister, StdHeader); - ASSERT (((PSTATE_MSR *) &MsrRegister)->PsEnable == 1); - CpuVid = (UINT32) (((PSTATE_MSR *) &MsrRegister)->CpuVid); - IddValue = (UINT32) (((PSTATE_MSR *) &MsrRegister)->IddValue); - IddDiv = (UINT32) (((PSTATE_MSR *) &MsrRegister)->IddDiv); + LibAmdMsrRead (PS_REG_BASE + (UINT32) StateNumber, &MsrReg, StdHeader); + ASSERT (((PSTATE_MSR *) &MsrReg)->PsEnable == 1); + CpuVid = (UINT32) (((PSTATE_MSR *) &MsrReg)->CpuVid); + IddValue = (UINT32) (((PSTATE_MSR *) &MsrReg)->IddValue); + IddDiv = (UINT32) (((PSTATE_MSR *) &MsrReg)->IddDiv); IdentifyCore (StdHeader, &Socket, &Module, &Ignored, &IgnoredSts); GetPciAddress (StdHeader, Socket, Module, &PciAddress, &IgnoredSts); @@ -654,7 +654,7 @@ F10GetPstateRegisterInfo ( IN AMD_CONFIG_PARAMS *StdHeader ) { - UINT64 MsrRegister; + UINT64 MsrReg; UINT32 PciRegister; PCI_ADDR PciAddress; CPUID_DATA CpuidData; @@ -672,9 +672,9 @@ F10GetPstateRegisterInfo ( *SwPstateNumber = PState; // Read PSTATE MSRs - LibAmdMsrRead (PS_REG_BASE + (UINT32) PState, &MsrRegister, StdHeader); + LibAmdMsrRead (PS_REG_BASE + (UINT32) PState, &MsrReg, StdHeader); - if (((PSTATE_MSR *) &MsrRegister)->PsEnable == 1) { + if (((PSTATE_MSR *) &MsrReg)->PsEnable == 1) { // PState enable = bit 63 *PStateEnabled = TRUE; // Check input pstate belongs to Boosted-Pstate, if yes, return *PStateEnabled = FALSE. @@ -688,9 +688,9 @@ F10GetPstateRegisterInfo ( } // Bits 39:32 (high 32 bits [7:0]) - *IddVal = (UINT32) ((PSTATE_MSR *) &MsrRegister)->IddValue; + *IddVal = (UINT32) ((PSTATE_MSR *) &MsrReg)->IddValue; // Bits 41:40 (high 32 bits [9:8]) - *IddDiv = (UINT32) ((PSTATE_MSR *) &MsrRegister)->IddDiv; + *IddDiv = (UINT32) ((PSTATE_MSR *) &MsrReg)->IddDiv; return (AGESA_SUCCESS); } diff --git a/src/vendorcode/amd/agesa/f14/Proc/CPU/Family/0x10/cpuF10Utilities.c b/src/vendorcode/amd/agesa/f14/Proc/CPU/Family/0x10/cpuF10Utilities.c index df6e58b3a4..d07084a060 100644 --- a/src/vendorcode/amd/agesa/f14/Proc/CPU/Family/0x10/cpuF10Utilities.c +++ b/src/vendorcode/amd/agesa/f14/Proc/CPU/Family/0x10/cpuF10Utilities.c @@ -119,7 +119,7 @@ F10PmSwVoltageTransition ( UINT32 Socket; UINT32 Module; UINT32 Ignored; - UINT64 MsrRegister; + UINT64 MsrReg; PCI_ADDR PciAddress; AGESA_STATUS IgnoredSts; @@ -130,9 +130,9 @@ F10PmSwVoltageTransition ( PciAddress.Address.Register = PW_CTL_MISC_REG; LibAmdPciRead (AccessWidth32, PciAddress, &PciRegister, StdHeader); if (((POWER_CTRL_MISC_REGISTER *) &PciRegister)->SlamVidMode == 1) { - LibAmdMsrRead (MSR_COFVID_CTL, &MsrRegister, StdHeader); - ((COFVID_CTRL_MSR *) &MsrRegister)->CpuVid = VidCode; - LibAmdMsrWrite (MSR_COFVID_CTL, &MsrRegister, StdHeader); + LibAmdMsrRead (MSR_COFVID_CTL, &MsrReg, StdHeader); + ((COFVID_CTRL_MSR *) &MsrReg)->CpuVid = VidCode; + LibAmdMsrWrite (MSR_COFVID_CTL, &MsrReg, StdHeader); F10WaitOutVoltageTransition (TRUE, StdHeader); } else return; @@ -270,22 +270,22 @@ F10SwVoltageTransitionServerNbCore ( ) { UINT32 VidCode; - UINT64 MsrRegister; + UINT64 MsrReg; if (((SW_VOLT_TRANS_NB *) InputData)->SlamMode) { VidCode = ((SW_VOLT_TRANS_NB *) InputData)->VidCode; } else { - LibAmdMsrRead (MSR_COFVID_STS, &MsrRegister, StdHeader); - VidCode = (UINT32) (((COFVID_STS_MSR *) &MsrRegister)->CurNbVid); + LibAmdMsrRead (MSR_COFVID_STS, &MsrReg, StdHeader); + VidCode = (UINT32) (((COFVID_STS_MSR *) &MsrReg)->CurNbVid); if (VidCode > ((SW_VOLT_TRANS_NB *) InputData)->VidCode) { --VidCode; } else if (VidCode < ((SW_VOLT_TRANS_NB *) InputData)->VidCode) { ++VidCode; } } - LibAmdMsrRead (MSR_COFVID_CTL, &MsrRegister, StdHeader); - ((COFVID_CTRL_MSR *) &MsrRegister)->NbVid = VidCode; - LibAmdMsrWrite (MSR_COFVID_CTL, &MsrRegister, StdHeader); + LibAmdMsrRead (MSR_COFVID_CTL, &MsrReg, StdHeader); + ((COFVID_CTRL_MSR *) &MsrReg)->NbVid = VidCode; + LibAmdMsrWrite (MSR_COFVID_CTL, &MsrReg, StdHeader); if (VidCode == ((SW_VOLT_TRANS_NB *) InputData)->VidCode) { return 0; @@ -323,7 +323,7 @@ F10ProgramVSSlamTimeOnSocket ( UINT32 MsrAddr; UINT32 OrMask; UINT32 PciRegister; - UINT64 MsrRegister; + UINT64 MsrReg; BOOLEAN IsPviMode; PCI_ADDR LocalPciAddress; @@ -339,30 +339,30 @@ F10ProgramVSSlamTimeOnSocket ( } // Get P0's voltage - LibAmdMsrRead (PS_REG_BASE, &MsrRegister, StdHeader); - P0VidCode = (UINT8) (((PSTATE_MSR *) &MsrRegister)->CpuVid); + LibAmdMsrRead (PS_REG_BASE, &MsrReg, StdHeader); + P0VidCode = (UINT8) (((PSTATE_MSR *) &MsrReg)->CpuVid); // If SVI, we only care about CPU VID. // If PVI, determine the higher voltage between NB and CPU if (IsPviMode) { - NbVid = (UINT8) (((PSTATE_MSR *) &MsrRegister)->NbVid); + NbVid = (UINT8) (((PSTATE_MSR *) &MsrReg)->NbVid); if (P0VidCode > NbVid) { P0VidCode = NbVid; } } // Get Pmin's index - LibAmdMsrRead (MSR_PSTATE_CURRENT_LIMIT, &MsrRegister, StdHeader); - MsrAddr = (UINT32) ((((PSTATE_CURLIM_MSR *) &MsrRegister)->PstateMaxVal) + PS_REG_BASE); + LibAmdMsrRead (MSR_PSTATE_CURRENT_LIMIT, &MsrReg, StdHeader); + MsrAddr = (UINT32) ((((PSTATE_CURLIM_MSR *) &MsrReg)->PstateMaxVal) + PS_REG_BASE); // Get Pmin's VID - LibAmdMsrRead (MsrAddr, &MsrRegister, StdHeader); - PminVidCode = (UINT8) (((PSTATE_MSR *) &MsrRegister)->CpuVid); + LibAmdMsrRead (MsrAddr, &MsrReg, StdHeader); + PminVidCode = (UINT8) (((PSTATE_MSR *) &MsrReg)->CpuVid); // If SVI, we only care about CPU VID. // If PVI, determine the higher voltage b/t NB and CPU if (IsPviMode) { - NbVid = (UINT8) (((PSTATE_MSR *) &MsrRegister)->NbVid); + NbVid = (UINT8) (((PSTATE_MSR *) &MsrReg)->NbVid); if (PminVidCode > NbVid) { PminVidCode = NbVid; } @@ -459,12 +459,12 @@ F10DisablePstate ( IN AMD_CONFIG_PARAMS *StdHeader ) { - UINT64 MsrRegister; + UINT64 MsrReg; ASSERT (StateNumber < NM_PS_REG); - LibAmdMsrRead (PS_REG_BASE + (UINT32) StateNumber, &MsrRegister, StdHeader); - ((PSTATE_MSR *) &MsrRegister)->PsEnable = 0; - LibAmdMsrWrite (PS_REG_BASE + (UINT32) StateNumber, &MsrRegister, StdHeader); + LibAmdMsrRead (PS_REG_BASE + (UINT32) StateNumber, &MsrReg, StdHeader); + ((PSTATE_MSR *) &MsrReg)->PsEnable = 0; + LibAmdMsrWrite (PS_REG_BASE + (UINT32) StateNumber, &MsrReg, StdHeader); return (AGESA_SUCCESS); } @@ -489,18 +489,18 @@ F10TransitionPstate ( IN AMD_CONFIG_PARAMS *StdHeader ) { - UINT64 MsrRegister; + UINT64 MsrReg; ASSERT (StateNumber < NM_PS_REG); - LibAmdMsrRead (PS_REG_BASE + (UINT32) StateNumber, &MsrRegister, StdHeader); - ASSERT (((PSTATE_MSR *) &MsrRegister)->PsEnable == 1); - LibAmdMsrRead (MSR_PSTATE_CTL, &MsrRegister, StdHeader); - ((PSTATE_CTRL_MSR *) &MsrRegister)->PstateCmd = (UINT64) StateNumber; - LibAmdMsrWrite (MSR_PSTATE_CTL, &MsrRegister, StdHeader); + LibAmdMsrRead (PS_REG_BASE + (UINT32) StateNumber, &MsrReg, StdHeader); + ASSERT (((PSTATE_MSR *) &MsrReg)->PsEnable == 1); + LibAmdMsrRead (MSR_PSTATE_CTL, &MsrReg, StdHeader); + ((PSTATE_CTRL_MSR *) &MsrReg)->PstateCmd = (UINT64) StateNumber; + LibAmdMsrWrite (MSR_PSTATE_CTL, &MsrReg, StdHeader); if (WaitForTransition) { do { - LibAmdMsrRead (MSR_PSTATE_STS, &MsrRegister, StdHeader); - } while (((PSTATE_STS_MSR *) &MsrRegister)->CurPstate != (UINT64) StateNumber); + LibAmdMsrRead (MSR_PSTATE_STS, &MsrReg, StdHeader); + } while (((PSTATE_STS_MSR *) &MsrReg)->CurPstate != (UINT64) StateNumber); } return (AGESA_SUCCESS); } @@ -525,15 +525,15 @@ F10GetTscRate ( IN AMD_CONFIG_PARAMS *StdHeader ) { - UINT64 MsrRegister; + UINT64 MsrReg; PSTATE_CPU_FAMILY_SERVICES *FamilyServices; FamilyServices = NULL; - GetFeatureServicesOfCurrentCore (&PstateFamilyServiceTable, &FamilyServices, StdHeader); + GetFeatureServicesOfCurrentCore (&PstateFamilyServiceTable, (const VOID **)&FamilyServices, StdHeader); ASSERT (FamilyServices != NULL); - LibAmdMsrRead (0xC0010015, &MsrRegister, StdHeader); - if ((MsrRegister & 0x01000000) != 0) { + LibAmdMsrRead (0xC0010015, &MsrReg, StdHeader); + if ((MsrReg & 0x01000000) != 0) { return (FamilyServices->GetPstateFrequency (FamilyServices, 0, FrequencyInMHz, StdHeader)); } else { return (FamilySpecificServices->GetCurrentNbFrequency (FamilySpecificServices, FrequencyInMHz, StdHeader)); @@ -564,7 +564,7 @@ F10GetCurrentNbFrequency ( UINT32 Core; UINT32 NbFid; UINT32 PciRegister; - UINT64 MsrRegister; + UINT64 MsrReg; PCI_ADDR PciAddress; AGESA_STATUS ReturnCode; @@ -577,8 +577,8 @@ F10GetCurrentNbFrequency ( PciAddress.Address.Register = CPTC0_REG; LibAmdPciRead (AccessWidth32, PciAddress, &PciRegister, StdHeader); NbFid = ((CLK_PWR_TIMING_CTRL_REGISTER *) &PciRegister)->NbFid; - LibAmdMsrRead (MSR_COFVID_STS, &MsrRegister, StdHeader); - if (((COFVID_STS_MSR *) &MsrRegister)->CurNbDid == 0) { + LibAmdMsrRead (MSR_COFVID_STS, &MsrReg, StdHeader); + if (((COFVID_STS_MSR *) &MsrReg)->CurNbDid == 0) { *FrequencyInMHz = ((NbFid + 4) * 200); } else { *FrequencyInMHz = (((NbFid + 4) * 200) / 2); diff --git a/src/vendorcode/amd/agesa/f14/Proc/CPU/Family/0x14/F14C6State.c b/src/vendorcode/amd/agesa/f14/Proc/CPU/Family/0x14/F14C6State.c index 48823ec080..2b7be5dcad 100644 --- a/src/vendorcode/amd/agesa/f14/Proc/CPU/Family/0x14/F14C6State.c +++ b/src/vendorcode/amd/agesa/f14/Proc/CPU/Family/0x14/F14C6State.c @@ -144,12 +144,12 @@ F14InitializeC6 ( UINT32 i; UINT32 MaxEnabledPstate; UINT32 PciRegister; - UINT64 MsrRegister; + UINT64 MsrReg; PCI_ADDR PciAddress; for (i = MSR_PSTATE_7; i > MSR_PSTATE_0; i--) { - LibAmdMsrRead (i, &MsrRegister, StdHeader); - if (((PSTATE_MSR *) &MsrRegister)->PsEnable == 1) { + LibAmdMsrRead (i, &MsrReg, StdHeader); + if (((PSTATE_MSR *) &MsrReg)->PsEnable == 1) { break; } } diff --git a/src/vendorcode/amd/agesa/f14/Proc/CPU/Family/0x14/F14IoCstate.c b/src/vendorcode/amd/agesa/f14/Proc/CPU/Family/0x14/F14IoCstate.c index 43f0c68bbb..c2536eda0d 100644 --- a/src/vendorcode/amd/agesa/f14/Proc/CPU/Family/0x14/F14IoCstate.c +++ b/src/vendorcode/amd/agesa/f14/Proc/CPU/Family/0x14/F14IoCstate.c @@ -115,28 +115,28 @@ F14InitializeIoCstate ( UINT32 i; UINT32 MaxEnabledPstate; UINT32 PciRegister; - UINT64 MsrRegister; + UINT64 MsrReg; AP_TASK TaskPtr; PCI_ADDR PciAddress; if ((EntryPoint & CPU_FEAT_AFTER_PM_INIT) != 0) { for (i = MSR_PSTATE_7; i > MSR_PSTATE_0; i--) { - LibAmdMsrRead (i, &MsrRegister, StdHeader); - if (((PSTATE_MSR *) &MsrRegister)->PsEnable == 1) { + LibAmdMsrRead (i, &MsrReg, StdHeader); + if (((PSTATE_MSR *) &MsrReg)->PsEnable == 1) { break; } } MaxEnabledPstate = i - MSR_PSTATE_0; // Initialize MSRC001_0073[CstateAddr] on each core to a region of // the IO address map with 8 consecutive available addresses. - MsrRegister = 0; - ((CSTATE_ADDRESS_MSR *) &MsrRegister)->CstateAddr = PlatformConfig->CStateIoBaseAddress; - ASSERT ((((CSTATE_ADDRESS_MSR *) &MsrRegister)->CstateAddr != 0) && - (((CSTATE_ADDRESS_MSR *) &MsrRegister)->CstateAddr <= 0xFFF8)); + MsrReg = 0; + ((CSTATE_ADDRESS_MSR *) &MsrReg)->CstateAddr = PlatformConfig->CStateIoBaseAddress; + ASSERT ((((CSTATE_ADDRESS_MSR *) &MsrReg)->CstateAddr != 0) && + (((CSTATE_ADDRESS_MSR *) &MsrReg)->CstateAddr <= 0xFFF8)); TaskPtr.FuncAddress.PfApTaskI = F14InitializeIoCstateOnCore; TaskPtr.DataTransfer.DataSizeInDwords = 2; - TaskPtr.DataTransfer.DataPtr = &MsrRegister; + TaskPtr.DataTransfer.DataPtr = &MsrReg; TaskPtr.DataTransfer.DataTransferFlags = 0; TaskPtr.ExeFlags = WAIT_FOR_CORE; ApUtilRunCodeOnAllLocalCoresAtEarly (&TaskPtr, StdHeader, NULL); diff --git a/src/vendorcode/amd/agesa/f14/Proc/CPU/Family/0x14/F14MicrocodePatch0500000B.c b/src/vendorcode/amd/agesa/f14/Proc/CPU/Family/0x14/F14MicrocodePatch0500000B.c index 1b1c6fb03b..37203f3a8b 100644 --- a/src/vendorcode/amd/agesa/f14/Proc/CPU/Family/0x14/F14MicrocodePatch0500000B.c +++ b/src/vendorcode/amd/agesa/f14/Proc/CPU/Family/0x14/F14MicrocodePatch0500000B.c @@ -63,7 +63,7 @@ // Patch code 0500000B for 5000 and equivalent CONST MICROCODE_PATCHES ROMDATA CpuF14MicrocodePatch0500000B = -{ +{{ 0x10, 0x20, 0x01, @@ -1632,7 +1632,7 @@ CONST MICROCODE_PATCHES ROMDATA CpuF14MicrocodePatch0500000B = 0xe9, 0xb2, 0x6d -}; +}}; /*---------------------------------------------------------------------------------------- * P R O T O T Y P E S O F L O C A L F U N C T I O N S diff --git a/src/vendorcode/amd/agesa/f14/Proc/CPU/Family/0x14/F14MicrocodePatch0500001A.c b/src/vendorcode/amd/agesa/f14/Proc/CPU/Family/0x14/F14MicrocodePatch0500001A.c index 5bde1d9ff5..a6dbf48913 100644 --- a/src/vendorcode/amd/agesa/f14/Proc/CPU/Family/0x14/F14MicrocodePatch0500001A.c +++ b/src/vendorcode/amd/agesa/f14/Proc/CPU/Family/0x14/F14MicrocodePatch0500001A.c @@ -63,7 +63,7 @@ // Patch code 0500001A for 5001 and equivalent CONST MICROCODE_PATCHES ROMDATA CpuF14MicrocodePatch0500001A = -{ +{{ 0x10, 0x20, 0x08, @@ -1632,7 +1632,7 @@ CONST MICROCODE_PATCHES ROMDATA CpuF14MicrocodePatch0500001A = 0x73, 0x52, 0x3b -}; +}}; /*---------------------------------------------------------------------------------------- * P R O T O T Y P E S O F L O C A L F U N C T I O N S diff --git a/src/vendorcode/amd/agesa/f14/Proc/CPU/Family/0x14/F14MicrocodePatch05000028.c b/src/vendorcode/amd/agesa/f14/Proc/CPU/Family/0x14/F14MicrocodePatch05000028.c new file mode 100644 index 0000000000..bdc8abd2a9 --- /dev/null +++ b/src/vendorcode/amd/agesa/f14/Proc/CPU/Family/0x14/F14MicrocodePatch05000028.c @@ -0,0 +1,1900 @@ +/* $NoKeywords:$ */ +/** + * @file + * + * AMD Family_14 Microcode patch. + * + * Fam14 Microcode Patch rev 05000028 for 5010 or equivalent. + * + * @xrefitem bom "File Content Label" "Release Content" + * @e project: AGESA + * @e sub-project: CPU/FAMILY/0x14 + * @e \$Revision: 37850 $ @e \$Date: 2010-09-13 18:09:57 -0400 (Mon, 13 Sep 2010) $ + * + */ +/* + ****************************************************************************** + * + * Copyright (c) 2011, Advanced Micro Devices, Inc. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * * Neither the name of Advanced Micro Devices, Inc. nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY + * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND + * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************** + */ +/*---------------------------------------------------------------------------------------- + * M O D U L E S U S E D + *---------------------------------------------------------------------------------------- + */ +#include "AGESA.h" +#include "cpuRegisters.h" +#include "cpuEarlyInit.h" + +/*---------------------------------------------------------------------------------------- + * D E F I N I T I O N S A N D M A C R O S + *---------------------------------------------------------------------------------------- + */ + +/*---------------------------------------------------------------------------------------- + * T Y P E D E F S A N D S T R U C T U R E S + *---------------------------------------------------------------------------------------- + */ + +// Patch code 05000028 for 5010 and equivalent +CONST MICROCODE_PATCHES ROMDATA CpuF14MicrocodePatch05000028 = +{{ +0x10, +0x20, +0x24, +0x11, +0x28, +0x00, +0x00, +0x05, +0x01, +0x80, +0x00, +0x00, +0x00, +0x00, +0x00, +0x00, +0x00, +0x00, +0x00, +0x00, +0x00, +0x00, +0x00, +0x00, +0x10, +0x50, +0x00, +0x00, +0x00, +0xaa, +0xaa, +0xaa, +0x89, +0x66, +0x9f, +0x9a, +0x14, +0x8a, +0xcd, +0xbb, +0x71, +0x6b, +0x59, +0xe0, +0xf1, +0xec, +0x1d, +0xe2, +0xa1, +0xcb, +0xdd, +0x85, +0xd4, +0x54, +0x18, +0x05, +0x1f, +0x71, +0x70, +0x1f, +0xb5, +0x6b, +0x86, +0xa2, +0x37, +0x5e, +0x14, +0x1b, +0xdd, +0xf4, +0x40, +0x31, +0x90, +0x8a, +0xa3, +0xc1, +0x4a, +0x5c, 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b/src/vendorcode/amd/agesa/f14/Proc/CPU/Family/0x14/F14MicrocodePatch05000101.c @@ -0,0 +1,1645 @@ +/* $NoKeywords:$ */ +/** + * @file + * + * AMD Family_14 Microcode patch. + * + * Fam14 Microcode Patch rev 05000101 for 5020 or equivalent. + * + * @xrefitem bom "File Content Label" "Release Content" + * @e project: AGESA + * @e sub-project: CPU/FAMILY/0x14 + * @e \$Revision: 37850 $ @e \$Date: 2010-09-13 18:09:57 -0400 (Mon, 13 Sep 2010) $ + * + */ +/* + ****************************************************************************** + * + * Copyright (c) 2011, Advanced Micro Devices, Inc. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * * Neither the name of Advanced Micro Devices, Inc. nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY + * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND + * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************** + */ +/*---------------------------------------------------------------------------------------- + * M O D U L E S U S E D + *---------------------------------------------------------------------------------------- + */ +#include "AGESA.h" +#include "cpuRegisters.h" +#include "cpuEarlyInit.h" + +/*---------------------------------------------------------------------------------------- + * D E F I N I T I O N S A N D M A C R O S + *---------------------------------------------------------------------------------------- + */ + +/*---------------------------------------------------------------------------------------- + * T Y P E D E F S A N D S T R U C T U R E S + *---------------------------------------------------------------------------------------- + */ + +// Encrypt Patch code 05000101 for 5020 and equivalent + +CONST MICROCODE_PATCHES ROMDATA CpuF14MicrocodePatch05000101 = +{{ + 0x11, + 0x20, + 0x06, + 0x04, + 0x01, + 0x01, + 0x00, + 0x05, + 0x01, + 0x80, + 0x00, + 0x00, + 0x00, + 0x00, + 0x00, + 0x00, + 0x00, + 0x00, + 0x00, + 0x00, + 0x00, + 0x00, + 0x00, + 0x00, + 0x20, + 0x50, + 0x00, + 0x00, + 0x00, + 0xaa, + 0xaa, + 0xaa, + 0x01, + 0xe9, + 0xee, + 0x42, + 0x6b, + 0x45, + 0xbd, + 0xcf, + 0x76, + 0xf0, + 0x6d, + 0x38, + 0xf1, + 0x7e, + 0x5e, + 0xb7, + 0x22, + 0x7d, + 0xdb, + 0x04, + 0xff, + 0xa4, + 0xb6, + 0x6c, + 0x5d, + 0x03, + 0x3d, + 0x35, + 0x7d, + 0x41, + 0x02, + 0x97, + 0x28, + 0xc9, + 0x02, + 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0x00 +}}; + +/*---------------------------------------------------------------------------------------- + * P R O T O T Y P E S O F L O C A L F U N C T I O N S + *---------------------------------------------------------------------------------------- + */ + +/*---------------------------------------------------------------------------------------- + * E X P O R T E D F U N C T I O N S + *---------------------------------------------------------------------------------------- + */
\ No newline at end of file diff --git a/src/vendorcode/amd/agesa/f14/Proc/CPU/Family/0x14/ON/F14OnCpb.c b/src/vendorcode/amd/agesa/f14/Proc/CPU/Family/0x14/ON/F14OnCpb.c new file mode 100644 index 0000000000..ec97a8dc47 --- /dev/null +++ b/src/vendorcode/amd/agesa/f14/Proc/CPU/Family/0x14/ON/F14OnCpb.c @@ -0,0 +1,187 @@ +/* $NoKeywords:$ */ +/** + * @file + * + * AMD Family 14 Ontario CPB Initialization + * + * Enables core performance boost. + * + * @xrefitem bom "File Content Label" "Release Content" + * @e project: AGESA + * @e sub-project: CPU/Family/0x14/ON + * @e \$Revision: 46389 $ @e \$Date: 2011-01-31 22:22:49 -0500 (Mon, 31 Jan 2011) $ + * + */ +/* + ****************************************************************************** + * + * Copyright (c) 2011, Advanced Micro Devices, Inc. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * * Neither the name of Advanced Micro Devices, Inc. nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY + * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND + * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************** + */ + +/*---------------------------------------------------------------------------------------- + * M O D U L E S U S E D + *---------------------------------------------------------------------------------------- + */ +#include "AGESA.h" +#include "amdlib.h" +#include "cpuFamilyTranslation.h" +#include "cpuF14PowerMgmt.h" +#include "GnbRegistersON.h" +#include "NbSmuLib.h" +#include "NbSmuLib.h" +#include "cpuFeatures.h" +#include "cpuCpb.h" +#include "Filecode.h" +CODE_GROUP (G1_PEICC) +RDATA_GROUP (G1_PEICC) + +#define FILECODE PROC_CPU_FAMILY_0X14_ON_F14ONCPB_FILECODE + +/*---------------------------------------------------------------------------------------- + * D E F I N I T I O N S A N D M A C R O S + *---------------------------------------------------------------------------------------- + */ + +/*---------------------------------------------------------------------------------------- + * T Y P E D E F S A N D S T R U C T U R E S + *---------------------------------------------------------------------------------------- + */ + +/*---------------------------------------------------------------------------------------- + * P R O T O T Y P E S O F L O C A L F U N C T I O N S + *---------------------------------------------------------------------------------------- + */ + +/*---------------------------------------------------------------------------------------- + * E X P O R T E D F U N C T I O N S + *---------------------------------------------------------------------------------------- + */ + +/*---------------------------------------------------------------------------------------*/ +/** + * BSC entry point for checking whether or not CPB is supported. + * + * @param[in] CpbServices The current CPU's family services. + * @param[in] PlatformConfig Contains the runtime modifiable feature input data. + * @param[in] Socket Zero based socket number to check. + * @param[in] StdHeader Config handle for library and services. + * + * @retval TRUE CPB is supported. + * @retval FALSE CPB is not supported. + * + */ +BOOLEAN +STATIC +F14OnIsCpbSupported ( + IN CPB_FAMILY_SERVICES *CpbServices, + IN PLATFORM_CONFIGURATION *PlatformConfig, + IN UINT32 Socket, + IN AMD_CONFIG_PARAMS *StdHeader + ) +{ + PCI_ADDR PciAddress; + CPB_CTRL_REGISTER CpbControl; + CPU_LOGICAL_ID CpuFamilyRevision; + + GetLogicalIdOfCurrentCore (&CpuFamilyRevision, StdHeader); + if ((CpuFamilyRevision.Revision & (AMD_F14_ON_Ax | AMD_F14_ON_Bx)) != 0) { + return FALSE; + } else { + PciAddress.AddressValue = CPB_CTRL_PCI_ADDR; + LibAmdPciRead (AccessWidth32, PciAddress, &CpbControl, StdHeader); + return (BOOLEAN) (CpbControl.NumBoostStates != 0); + } +} + + +/*---------------------------------------------------------------------------------------*/ +/** + * BSC entry point for enabling Core Performance Boost. + * + * Set up D18F4x15C[BoostSrc] and start the PDMs according to the BKDG. + * + * @param[in] CpbServices The current CPU's family services. + * @param[in] PlatformConfig Contains the runtime modifiable feature input data. + * @param[in] EntryPoint Current CPU feature dispatch point. + * @param[in] Socket Zero based socket number to check. + * @param[in] StdHeader Config handle for library and services. + * + * @retval AGESA_SUCCESS Always succeeds. + * + */ +AGESA_STATUS +STATIC +F14OnInitializeCpb ( + IN CPB_FAMILY_SERVICES *CpbServices, + IN PLATFORM_CONFIGURATION *PlatformConfig, + IN UINT64 EntryPoint, + IN UINT32 Socket, + IN AMD_CONFIG_PARAMS *StdHeader + ) +{ + PCI_ADDR PciAddress; + CPB_CTRL_REGISTER CpbControl; + LPMV_SCALAR2_REGISTER LpmvScalar2; + SMUx0B_x8580_STRUCT SMUx0Bx8580; + + if ((EntryPoint & CPU_FEAT_BEFORE_PM_INIT) != 0) { + // F4x14C [25:24] ApmCstExtPol = 1 + PciAddress.AddressValue = LPMV_SCALAR2_PCI_ADDR; + LibAmdPciRead (AccessWidth32, PciAddress, &LpmvScalar2, StdHeader); + LpmvScalar2.ApmCstExtPol = 1; + LibAmdPciWrite (AccessWidth32, PciAddress, &LpmvScalar2, StdHeader); + // F4x15C [1:0] BoostSrc = 1 + // F4x15C [29] BoostEnAllCores = 1 + PciAddress.AddressValue = CPB_CTRL_PCI_ADDR; + LibAmdPciRead (AccessWidth32, PciAddress, &CpbControl, StdHeader); + CpbControl.BoostSrc = 1; + CpbControl.BoostEnAllCores = 1; + IDS_OPTION_HOOK (IDS_CPB_CTRL, &CpbControl, StdHeader); + LibAmdPciWrite (AccessWidth32, PciAddress, &CpbControl, StdHeader); + } else if ((EntryPoint & CPU_FEAT_INIT_LATE_END) != 0) { + // Ensure that the recommended settings have been programmed into SMUx0B_x8580, then + // interrupt the SMU with service index 12h. + NbSmuRcuRegisterRead (SMUx0B_x8580_ADDRESS, &SMUx0Bx8580.Value, 1, StdHeader); + SMUx0Bx8580.Field.PdmPeriod = 0x1388; + SMUx0Bx8580.Field.PdmParamLoc = 0; + SMUx0Bx8580.Field.PdmCacEn = 1; + SMUx0Bx8580.Field.PdmUnit = 1; + SMUx0Bx8580.Field.PdmEn = 1; + NbSmuRcuRegisterWrite (SMUx0B_x8580_ADDRESS, &SMUx0Bx8580.Value, 1, TRUE, StdHeader); + NbSmuServiceRequest (0x12, TRUE, StdHeader); + } + + return AGESA_SUCCESS; +} + +CONST CPB_FAMILY_SERVICES ROMDATA F14OnCpbSupport = +{ + 0, + F14OnIsCpbSupported, + F14OnInitializeCpb +}; diff --git a/src/vendorcode/amd/agesa/f14/Proc/CPU/Family/0x14/ON/F14OnEquivalenceTable.c b/src/vendorcode/amd/agesa/f14/Proc/CPU/Family/0x14/ON/F14OnEquivalenceTable.c index 3cadf73fc8..1e295889e2 100644 --- a/src/vendorcode/amd/agesa/f14/Proc/CPU/Family/0x14/ON/F14OnEquivalenceTable.c +++ b/src/vendorcode/amd/agesa/f14/Proc/CPU/Family/0x14/ON/F14OnEquivalenceTable.c @@ -7,7 +7,7 @@ * @xrefitem bom "File Content Label" "Release Content" * @e project: AGESA * @e sub-project: CPU/Family/0x14 - * @e \$Revision: 36418 $ @e \$Date: 2010-08-18 17:00:58 +0800 (Wed, 18 Aug 2010) $ + * @e \$Revision: 48589 $ @e \$Date: 2011-03-10 09:27:00 -0700 (Thu, 10 Mar 2011) $ * */ /* @@ -68,6 +68,14 @@ *---------------------------------------------------------------------------------------- */ +VOID +GetF14OnMicrocodeEquivalenceTable ( + IN CPU_SPECIFIC_SERVICES *FamilySpecificServices, + OUT CONST VOID **OnEquivalenceTablePtr, + OUT UINT8 *NumberOfElements, + IN AMD_CONFIG_PARAMS *StdHeader + ); + /*---------------------------------------------------------------------------------------- * E X P O R T E D F U N C T I O N S *---------------------------------------------------------------------------------------- @@ -77,7 +85,8 @@ STATIC CONST UINT16 ROMDATA CpuF14MicrocodeEquivalenceTable[] = { 0x5000, 0x5000, 0x5001, 0x5001, - 0x5010, 0x5010 + 0x5010, 0x5010, + 0x5020, 0x5020 }; // Unencrypted equivalent @@ -85,7 +94,8 @@ STATIC CONST UINT16 ROMDATA CpuF14UnEncryptedMicrocodeEquivalenceTable[] = { 0x5000, 0x5800, 0x5001, 0x5801, - 0x5010, 0x5810 + 0x5010, 0x5810, + 0x5020, 0x5820 }; diff --git a/src/vendorcode/amd/agesa/f14/Proc/CPU/Family/0x14/ON/F14OnInitEarlyTable.c b/src/vendorcode/amd/agesa/f14/Proc/CPU/Family/0x14/ON/F14OnInitEarlyTable.c index f5f70bdfc7..620ed7d799 100644 --- a/src/vendorcode/amd/agesa/f14/Proc/CPU/Family/0x14/ON/F14OnInitEarlyTable.c +++ b/src/vendorcode/amd/agesa/f14/Proc/CPU/Family/0x14/ON/F14OnInitEarlyTable.c @@ -87,6 +87,14 @@ extern F14_ES_CORE_SUPPORT F14EarlySampleCoreSupport; *---------------------------------------------------------------------------------------- */ VOID +GetF14OnEarlyInitOnCoreTable ( + IN CPU_SPECIFIC_SERVICES *FamilyServices, + OUT CONST S_PERFORM_EARLY_INIT_ON_CORE **Table, + IN AMD_CPU_EARLY_PARAMS *EarlyParams, + IN AMD_CONFIG_PARAMS *StdHeader + ); + +VOID F14OnLoadMicrocodePatchAtEarly ( IN CPU_SPECIFIC_SERVICES *FamilyServices, IN AMD_CPU_EARLY_PARAMS *EarlyParams, @@ -144,7 +152,7 @@ GetF14OnEarlyInitOnCoreTable ( { *Table = F14OnEarlyInitOnCoreTable; - F14EarlySampleCoreSupport.F14GetEarlyInitTableHook (Table, StdHeader); + F14EarlySampleCoreSupport.F14GetEarlyInitTableHook ((const VOID **)Table, StdHeader); } /*---------------------------------------------------------------------------------------*/ diff --git a/src/vendorcode/amd/agesa/f14/Proc/CPU/Family/0x14/ON/F14OnLogicalIdTables.c b/src/vendorcode/amd/agesa/f14/Proc/CPU/Family/0x14/ON/F14OnLogicalIdTables.c index 82498c770b..ec502b0adb 100644 --- a/src/vendorcode/amd/agesa/f14/Proc/CPU/Family/0x14/ON/F14OnLogicalIdTables.c +++ b/src/vendorcode/amd/agesa/f14/Proc/CPU/Family/0x14/ON/F14OnLogicalIdTables.c @@ -66,6 +66,14 @@ *---------------------------------------------------------------------------------------- */ +VOID +GetF14OnLogicalIdAndRev ( + OUT CONST CPU_LOGICAL_ID_XLAT **OnIdPtr, + OUT UINT8 *NumberOfElements, + OUT UINT64 *LogicalFamily, + IN OUT AMD_CONFIG_PARAMS *StdHeader + ); + /*---------------------------------------------------------------------------------------- * E X P O R T E D F U N C T I O N S *---------------------------------------------------------------------------------------- @@ -84,6 +92,10 @@ STATIC CONST CPU_LOGICAL_ID_XLAT ROMDATA CpuF14OnLogicalIdAndRevArray[] = { 0x5010, AMD_F14_ON_B0 + }, + { + 0x5020, + AMD_F14_ON_C0 } }; diff --git a/src/vendorcode/amd/agesa/f14/Proc/CPU/Family/0x14/ON/F14OnMicrocodePatchTables.c b/src/vendorcode/amd/agesa/f14/Proc/CPU/Family/0x14/ON/F14OnMicrocodePatchTables.c index ba4b013d00..da445cc483 100644 --- a/src/vendorcode/amd/agesa/f14/Proc/CPU/Family/0x14/ON/F14OnMicrocodePatchTables.c +++ b/src/vendorcode/amd/agesa/f14/Proc/CPU/Family/0x14/ON/F14OnMicrocodePatchTables.c @@ -70,6 +70,14 @@ extern CONST UINT8 ROMDATA CpuF14OnNumberOfMicrocodePatches; *---------------------------------------------------------------------------------------- */ +VOID +GetF14OnMicroCodePatchesStruct ( + IN CPU_SPECIFIC_SERVICES *FamilySpecificServices, + OUT CONST VOID **OnUcodePtr, + OUT UINT8 *NumberOfElements, + IN AMD_CONFIG_PARAMS *StdHeader + ); + /*---------------------------------------------------------------------------------------- * E X P O R T E D F U N C T I O N S *---------------------------------------------------------------------------------------- diff --git a/src/vendorcode/amd/agesa/f14/Proc/CPU/Family/0x14/ON/F14OnPciTables.c b/src/vendorcode/amd/agesa/f14/Proc/CPU/Family/0x14/ON/F14OnPciTables.c new file mode 100644 index 0000000000..37a03e84b0 --- /dev/null +++ b/src/vendorcode/amd/agesa/f14/Proc/CPU/Family/0x14/ON/F14OnPciTables.c @@ -0,0 +1,105 @@ +/* $NoKeywords:$ */ +/** + * @file + * + * AMD Family_14 Ontario PCI tables with values as defined in BKDG + * + * @xrefitem bom "File Content Label" "Release Content" + * @e project: AGESA + * @e sub-project: CPU/FAMILY/0x14/ON + * @e \$Revision: 46389 $ @e \$Date: 2011-01-31 22:22:49 -0500 (Mon, 31 Jan 2011) $ + * + */ +/* + ****************************************************************************** + * + * Copyright (c) 2011, Advanced Micro Devices, Inc. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * * Neither the name of Advanced Micro Devices, Inc. nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY + * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND + * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************** + */ + +/*---------------------------------------------------------------------------------------- + * M O D U L E S U S E D + *---------------------------------------------------------------------------------------- + */ +#include "AGESA.h" +#include "cpuRegisters.h" +#include "Table.h" +#include "Filecode.h" +#define FILECODE PROC_CPU_FAMILY_0X14_ON_F14ONPCITABLES_FILECODE + +/*---------------------------------------------------------------------------------------- + * D E F I N I T I O N S A N D M A C R O S + *---------------------------------------------------------------------------------------- + */ + +/*---------------------------------------------------------------------------------------- + * T Y P E D E F S A N D S T R U C T U R E S + *---------------------------------------------------------------------------------------- + */ + +/*---------------------------------------------------------------------------------------- + * P R O T O T Y P E S O F L O C A L F U N C T I O N S + *---------------------------------------------------------------------------------------- + */ + +/*---------------------------------------------------------------------------------------- + * E X P O R T E D F U N C T I O N S + *---------------------------------------------------------------------------------------- + */ + +// P C I T a b l e s +// ---------------------- + +STATIC CONST TABLE_ENTRY_FIELDS ROMDATA F14OnPciRegisters[] = +{ +// Function 4 + +// D18F4x104 - TDP Lock Accumulator +// bits[1:0] TdpLockDivVal = 1 +// bits[13:2] TdpLockDivRate = 0x190 +// bits[16:15] TdpLockDivValCpu = 1 +// bits[28:17] TdpLockDivRateCpu = 0x190 + { + PciRegister, + { + AMD_FAMILY_14, // CpuFamily + AMD_F14_ON_Cx // CpuRevision + }, + {AMD_PF_ALL}, // platformFeatures + {{ + MAKE_SBDFO (0, 0, 24, FUNC_4, 0x104), // Address + 0x03208641, // regData + 0x1FFFBFFF, // regMask + }} + }, +}; + +CONST REGISTER_TABLE ROMDATA F14OnPciRegisterTable = { + PrimaryCores, + (sizeof (F14OnPciRegisters) / sizeof (TABLE_ENTRY_FIELDS)), + F14OnPciRegisters, +}; diff --git a/src/vendorcode/amd/agesa/f14/Proc/CPU/Family/0x14/cpuCommonF14Utilities.c b/src/vendorcode/amd/agesa/f14/Proc/CPU/Family/0x14/cpuCommonF14Utilities.c index 226e951ec3..de100a2a06 100644 --- a/src/vendorcode/amd/agesa/f14/Proc/CPU/Family/0x14/cpuCommonF14Utilities.c +++ b/src/vendorcode/amd/agesa/f14/Proc/CPU/Family/0x14/cpuCommonF14Utilities.c @@ -112,6 +112,18 @@ CONST UINT16 ROMDATA F14MaxNbFreqAtMinVidFreqTable[] = *---------------------------------------------------------------------------------------- */ UINT32 +F14GetApCoreNumber ( + IN CPU_SPECIFIC_SERVICES *FamilySpecificServices, + IN AMD_CONFIG_PARAMS *StdHeader + ); + +CORE_ID_POSITION +F14CpuAmdCoreIdPositionInInitialApicId ( + IN CPU_SPECIFIC_SERVICES *FamilySpecificServices, + IN AMD_CONFIG_PARAMS *StdHeader + ); + +UINT32 STATIC RoundedDivision ( IN UINT32 Dividend, @@ -300,6 +312,7 @@ F14NbPstateInit ( UINT32 TargetNumerator; UINT32 TargetDenominator; BOOLEAN ReturnStatus; + BOOLEAN WaitForTransition; PCI_ADDR PciAddress; D18F3xD4_STRUCT Cptc0; D18F3xDC_STRUCT Cptc2; @@ -313,6 +326,7 @@ F14NbPstateInit ( // F14 only supports NB P0 and NB P1 ASSERT (TargetNbPstate < 2); + WaitForTransition = FALSE; ReturnStatus = TRUE; // Get D18F3xD4[MainPllOpFreqId] frequency @@ -383,8 +397,11 @@ F14NbPstateInit ( // Apply the appropriate P0 frequency PciAddress.AddressValue = CPTC2_PCI_ADDR; LibAmdPciRead (AccessWidth32, PciAddress, &Cptc2.Value, StdHeader); + if (Cptc2.Field.NbPs0NclkDiv != EncodedNbPs0NclkDiv) { + WaitForTransition = TRUE; Cptc2.Field.NbPs0NclkDiv = EncodedNbPs0NclkDiv; LibAmdPciWrite (AccessWidth32, PciAddress, &Cptc2.Value, StdHeader); + } NbP0Cof = RoundedDivision (NbPstateNumerator, EncodedNbPs0NclkDiv); // Determine NB P1 settings if necessary @@ -434,6 +451,13 @@ F14NbPstateInit ( NbP1Cof = 0; } *CurrentNbFreq = NbP0Cof; + if (WaitForTransition) { + // Ensure that the frequency has settled before returning to memory code. + PciAddress.AddressValue = CPTC2_PCI_ADDR; + do { + LibAmdPciRead (AccessWidth32, PciAddress, &Cptc2.Value, StdHeader); + } while (Cptc2.Field.NclkFreqDone != 1); + } } else { // Get NB P0 COF PciAddress.AddressValue = CPTC2_PCI_ADDR; @@ -457,12 +481,7 @@ F14NbPstateInit ( NbPsCfgLow.Field.NbPsForceSel = 1; LibAmdPciWrite (AccessWidth32, PciAddress, &NbPsCfgLow.Value, StdHeader); - // Wait for the transition to complete. - PciAddress.AddressValue = NB_PSTATE_CTRL_STS_PCI_ADDR; - do { - LibAmdPciRead (AccessWidth32, PciAddress, &NbPsCtrlSts.Value, StdHeader); - } while (NbPsCtrlSts.Field.NbPs1Act != 1); - + WaitForTransition = TRUE; *CurrentNbFreq = RoundedDivision (NbPstateNumerator, NbPsCfgLow.Field.NbPs1NclkDiv); } else { // No NB P-states. Return FALSE, and set current frequency to P0. @@ -476,15 +495,17 @@ F14NbPstateInit ( // Request transition to P0 NbPsCfgLow.Field.NbPsForceSel = 0; LibAmdPciWrite (AccessWidth32, PciAddress, &NbPsCfgLow.Value, StdHeader); + WaitForTransition = TRUE; } } - } - + if (WaitForTransition) { // Ensure that the frequency has settled before returning to memory code. - PciAddress.AddressValue = CPTC2_PCI_ADDR; + PciAddress.AddressValue = NB_PSTATE_CTRL_STS_PCI_ADDR; do { - LibAmdPciRead (AccessWidth32, PciAddress, &Cptc2.Value, StdHeader); - } while (Cptc2.Field.NclkFreqDone != 1); + LibAmdPciRead (AccessWidth32, PciAddress, &NbPsCtrlSts.Value, StdHeader); + } while (NbPsCtrlSts.Field.NbPs1Act != TargetNbPstate); + } + } return ReturnStatus; } diff --git a/src/vendorcode/amd/agesa/f14/Proc/CPU/Family/0x14/cpuF14BrandId.c b/src/vendorcode/amd/agesa/f14/Proc/CPU/Family/0x14/cpuF14BrandId.c index db19787391..e873bb14b4 100644 --- a/src/vendorcode/amd/agesa/f14/Proc/CPU/Family/0x14/cpuF14BrandId.c +++ b/src/vendorcode/amd/agesa/f14/Proc/CPU/Family/0x14/cpuF14BrandId.c @@ -70,6 +70,22 @@ *---------------------------------------------------------------------------------------- */ +VOID +GetF14BrandIdString1 ( + IN CPU_SPECIFIC_SERVICES *FamilySpecificServices, + OUT CONST VOID **BrandString1Ptr, + OUT UINT8 *NumberOfElements, + IN AMD_CONFIG_PARAMS *StdHeader + ); + +VOID +GetF14BrandIdString2 ( + IN CPU_SPECIFIC_SERVICES *FamilySpecificServices, + OUT CONST VOID **BrandString2Ptr, + OUT UINT8 *NumberOfElements, + IN AMD_CONFIG_PARAMS *StdHeader + ); + /*---------------------------------------------------------------------------------------- * E X P O R T E D F U N C T I O N S *---------------------------------------------------------------------------------------- diff --git a/src/vendorcode/amd/agesa/f14/Proc/CPU/Family/0x14/cpuF14BrandIdFt1.c b/src/vendorcode/amd/agesa/f14/Proc/CPU/Family/0x14/cpuF14BrandIdFt1.c index 2d4e34d2d4..30ba2c1c18 100644 --- a/src/vendorcode/amd/agesa/f14/Proc/CPU/Family/0x14/cpuF14BrandIdFt1.c +++ b/src/vendorcode/amd/agesa/f14/Proc/CPU/Family/0x14/cpuF14BrandIdFt1.c @@ -9,7 +9,7 @@ * @xrefitem bom "File Content Label" "Release Content" * @e project: AGESA * @e sub-project: CPU - * @e \$Revision: 40034 $ @e \$Date: 2010-10-19 04:03:22 +0800 (Tue, 19 Oct 2010) $ + * @e \$Revision: 45203 $ @e \$Date: 2011-01-13 12:36:39 -0700 (Thu, 13 Jan 2011) $ * */ /* @@ -77,6 +77,7 @@ CONST CHAR8 ROMDATA str_AMD_C[] = "AMD C-"; CONST CHAR8 ROMDATA str_AMD_E[] = "AMD E-"; CONST CHAR8 ROMDATA str_AMD_G_T[] = "AMD G-T"; +CONST CHAR8 ROMDATA str_AMD_Z[] = "AMD Z-"; // String2 CONST CHAR8 ROMDATA str___Processor[] = " Processor"; @@ -88,6 +89,11 @@ CONST CHAR8 ROMDATA str_x_Processor[] = "x Processor"; CONST CHAR8 ROMDATA str_L_Processor[] = "L Processor"; CONST CHAR8 ROMDATA str_N_Processor[] = "N Processor"; CONST CHAR8 ROMDATA str_R_Processor[] = "R Processor"; +CONST CHAR8 ROMDATA str_E_Processor[] = "E Processor"; +CONST CHAR8 ROMDATA str_0D_APU[] = "0D APU with Radeon(tm) HD Graphics"; +CONST CHAR8 ROMDATA str_0_APU[] = "0 APU with Radeon(tm) HD Graphics"; +CONST CHAR8 ROMDATA str_5_APU[] = "5 APU with Radeon(tm) HD Graphics"; +CONST CHAR8 ROMDATA str_APU[] = " APU with Radeon(tm) HD Graphics"; /*--------------------------------------------------------------------------------------- * T Y P E D E F S, S T R U C T U R E S, E N U M S @@ -101,6 +107,7 @@ CONST AMD_CPU_BRAND ROMDATA CpuF14OnBrandIdString1ArrayFt1[] = {2, 0, 1, ON_SOCKET_FT1, str_AMD_C, sizeof (str_AMD_C)}, {1, 0, 2, ON_SOCKET_FT1, str_AMD_E, sizeof (str_AMD_E)}, {2, 0, 2, ON_SOCKET_FT1, str_AMD_E, sizeof (str_AMD_E)}, + {2, 0, 3, ON_SOCKET_FT1, str_AMD_Z, sizeof (str_AMD_Z)}, {1, 0, 4, ON_SOCKET_FT1, str_AMD_G_T, sizeof (str_AMD_G_T)}, {2, 0, 4, ON_SOCKET_FT1, str_AMD_G_T, sizeof (str_AMD_G_T)} }; //Cores, page, index, socket, stringstart, stringlength @@ -126,6 +133,15 @@ CONST AMD_CPU_BRAND ROMDATA CpuF14OnBrandIdString2ArrayFt1[] = {1, 0, 0x08, ON_SOCKET_FT1, str_N_Processor, sizeof (str_N_Processor)}, {2, 0, 0x08, ON_SOCKET_FT1, str_N_Processor, sizeof (str_N_Processor)}, {1, 0, 0x09, ON_SOCKET_FT1, str_R_Processor, sizeof (str_R_Processor)}, + {2, 0, 0x09, ON_SOCKET_FT1, str_0_APU, sizeof (str_0_APU)}, + {1, 0, 0x0A, ON_SOCKET_FT1, str_0_APU, sizeof (str_0_APU)}, + {2, 0, 0x0A, ON_SOCKET_FT1, str_5_APU, sizeof (str_5_APU)}, + {1, 0, 0x0B, ON_SOCKET_FT1, str_5_APU, sizeof (str_5_APU)}, + {2, 0, 0x0B, ON_SOCKET_FT1, str_APU, sizeof (str_APU)}, + {1, 0, 0x0C, ON_SOCKET_FT1, str_APU, sizeof (str_APU)}, + {2, 0, 0x0C, ON_SOCKET_FT1, str_E_Processor, sizeof (str_E_Processor)}, + {1, 0, 0x0D, ON_SOCKET_FT1, str_0D_APU, sizeof (str_0D_APU)}, + {2, 0, 0x0D, ON_SOCKET_FT1, str_0D_APU, sizeof (str_0D_APU)}, {1, 0, 0x0F, ON_SOCKET_FT1, 0, 0}, //Size 0 for no suffix {2, 0, 0x0F, ON_SOCKET_FT1, 0, 0}, //Size 0 for no suffix }; //Cores, page, index, socket, stringstart, stringlength diff --git a/src/vendorcode/amd/agesa/f14/Proc/CPU/Family/0x14/cpuF14CacheDefaults.c b/src/vendorcode/amd/agesa/f14/Proc/CPU/Family/0x14/cpuF14CacheDefaults.c index dbead6d19f..8b8d30e0f6 100644 --- a/src/vendorcode/amd/agesa/f14/Proc/CPU/Family/0x14/cpuF14CacheDefaults.c +++ b/src/vendorcode/amd/agesa/f14/Proc/CPU/Family/0x14/cpuF14CacheDefaults.c @@ -69,6 +69,14 @@ *---------------------------------------------------------------------------------------- */ +VOID +GetF14CacheInfo ( + IN CPU_SPECIFIC_SERVICES *FamilySpecificServices, + OUT CONST VOID **CacheInfoPtr, + OUT UINT8 *NumberOfElements, + IN AMD_CONFIG_PARAMS *StdHeader + ); + /*---------------------------------------------------------------------------------------- * E X P O R T E D F U N C T I O N S *---------------------------------------------------------------------------------------- diff --git a/src/vendorcode/amd/agesa/f14/Proc/CPU/Family/0x14/cpuF14Dmi.c b/src/vendorcode/amd/agesa/f14/Proc/CPU/Family/0x14/cpuF14Dmi.c index 50ce4d1cb8..aaf761f743 100644 --- a/src/vendorcode/amd/agesa/f14/Proc/CPU/Family/0x14/cpuF14Dmi.c +++ b/src/vendorcode/amd/agesa/f14/Proc/CPU/Family/0x14/cpuF14Dmi.c @@ -76,6 +76,33 @@ extern CPU_FAMILY_SUPPORT_TABLE PstateFamilyServiceTable; *---------------------------------------------------------------------------------------- */ +VOID +DmiF14GetInfo ( + IN OUT CPU_TYPE_INFO *CpuInfoPtr, + IN AMD_CONFIG_PARAMS *StdHeader + ); + +UINT8 +DmiF14GetVoltage ( + IN AMD_CONFIG_PARAMS *StdHeader + ); + +UINT16 +DmiF14GetMaxSpeed ( + IN AMD_CONFIG_PARAMS *StdHeader + ); + +UINT16 +DmiF14GetExtClock ( + IN AMD_CONFIG_PARAMS *StdHeader + ); + +VOID +DmiF14GetMemInfo ( + IN OUT CPU_GET_MEM_INFO *CpuGetMemInfoPtr, + IN AMD_CONFIG_PARAMS *StdHeader + ); + /*---------------------------------------------------------------------------------------- * E X P O R T E D F U N C T I O N S *---------------------------------------------------------------------------------------- @@ -147,16 +174,25 @@ DmiF14GetVoltage ( { UINT8 MaxVid; UINT8 Voltage; + UINT8 NumberBoostStates; UINT64 MsrData; + PCI_ADDR TempAddr; + CPU_LOGICAL_ID CpuFamilyRevision; + CPB_CTRL_REGISTER CpbCtrl; // Voltage = 0x80 + (voltage at boot time * 10) - LibAmdMsrRead (MSR_COFVID_STS, &MsrData, StdHeader); - MaxVid = (UINT8) (((COFVID_STS_MSR *)&MsrData)->MaxVid); - if (MaxVid == 0) { - LibAmdMsrRead (MSR_PSTATE_0, &MsrData, StdHeader); - MaxVid = (UINT8) (((PSTATE_MSR *)&MsrData)->CpuVid); + GetLogicalIdOfCurrentCore (&CpuFamilyRevision, StdHeader); + if ((CpuFamilyRevision.Revision & (AMD_F14_ON_Ax | AMD_F14_ON_Bx)) == 0) { + TempAddr.AddressValue = CPB_CTRL_PCI_ADDR; + LibAmdPciRead (AccessWidth32, TempAddr, &CpbCtrl, StdHeader); // F4x15C + NumberBoostStates = (UINT8) CpbCtrl.NumBoostStates; + } else { + NumberBoostStates = 0; } + LibAmdMsrRead ((MSR_PSTATE_0 + NumberBoostStates), &MsrData, StdHeader); + MaxVid = (UINT8) (((PSTATE_MSR *)&MsrData)->CpuVid); + if ((MaxVid >= 0x7C) && (MaxVid <= 0x7F)) { Voltage = 0; } else { @@ -184,14 +220,27 @@ DmiF14GetMaxSpeed ( IN AMD_CONFIG_PARAMS *StdHeader ) { + UINT8 NumBoostStates; UINT32 P0Frequency; + UINT32 PciData; + PCI_ADDR PciAddress; PSTATE_CPU_FAMILY_SERVICES *FamilyServices; + CPU_LOGICAL_ID CpuFamilyRevision; FamilyServices = NULL; - GetFeatureServicesOfCurrentCore (&PstateFamilyServiceTable, &FamilyServices, StdHeader); + GetFeatureServicesOfCurrentCore (&PstateFamilyServiceTable, (const VOID **)&FamilyServices, StdHeader); ASSERT (FamilyServices != NULL); - FamilyServices->GetPstateFrequency (FamilyServices, (UINT8) 0x00, &P0Frequency, StdHeader); + GetLogicalIdOfCurrentCore (&CpuFamilyRevision, StdHeader); + if ((CpuFamilyRevision.Revision & (AMD_F14_ON_Ax | AMD_F14_ON_Bx)) == 0) { + PciAddress.AddressValue = MAKE_SBDFO (0, 0 , PCI_DEV_BASE, FUNC_4, 0x15C); + LibAmdPciRead (AccessWidth32, PciAddress, &PciData, StdHeader); + NumBoostStates = (UINT8) ((PciData >> 2) & 7); + } else { + NumBoostStates = 0; + } + + FamilyServices->GetPstateFrequency (FamilyServices, NumBoostStates, &P0Frequency, StdHeader); return ((UINT16) P0Frequency); } @@ -242,6 +291,10 @@ DmiF14GetMemInfo ( * Processor Family Table * * Note: 'x' means we don't care this field + * 046h = "AMD C-Series Processor" + * 047h = "AMD E-Series Processor" + * 048h = "AMD S-Series Processor" + * 049h = "AMD G-Series Processor" * 002h = "Unknown" *-------------------------------------------------------------------------------------*/ CONST DMI_BRAND_ENTRY ROMDATA Family14BrandList[] = @@ -250,6 +303,7 @@ CONST DMI_BRAND_ENTRY ROMDATA Family14BrandList[] = // PackageType, PgOfBrandId, NumberOfCores, String1ofBrandId, ValueSetToDmiTable {0, 0, 'x', 1, 0x46}, {0, 0, 'x', 2, 0x47}, + {0, 0, 'x', 4, 0x49}, {'x', 'x', 'x', 'x', 0x02} }; diff --git a/src/vendorcode/amd/agesa/f14/Proc/CPU/Family/0x14/cpuF14LowPowerInit.c b/src/vendorcode/amd/agesa/f14/Proc/CPU/Family/0x14/cpuF14LowPowerInit.c new file mode 100644 index 0000000000..98fe9f1896 --- /dev/null +++ b/src/vendorcode/amd/agesa/f14/Proc/CPU/Family/0x14/cpuF14LowPowerInit.c @@ -0,0 +1,149 @@ +/* $NoKeywords:$ */ +/** + * @file + * + * AMD Family_14 Optimizations for lower power consumption + * + * Sets some registers for tablet parts at AmdInitEarly. + * + * @xrefitem bom "File Content Label" "Release Content" + * @e project: AGESA + * @e sub-project: CPU/Family/F14 + * @e \$Revision: 45578 $ @e \$Date: 2011-01-18 19:20:41 -0500 (Tue, 18 Jan 2011) $ + * + */ +/* + ****************************************************************************** + * + * Copyright (c) 2011, Advanced Micro Devices, Inc. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * * Neither the name of Advanced Micro Devices, Inc. nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY + * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND + * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************** + */ + +/*---------------------------------------------------------------------------------------- + * M O D U L E S U S E D + *---------------------------------------------------------------------------------------- + */ +#include "AGESA.h" +#include "amdlib.h" +#include "cpuFamilyTranslation.h" +#include "cpuF14PowerMgmt.h" +#include "cpuF14LowPowerInit.h" +#include "Filecode.h" + +#define FILECODE PROC_CPU_FAMILY_0X14_CPUF14LOWPOWERINIT_FILECODE + +/*---------------------------------------------------------------------------------------- + * D E F I N I T I O N S A N D M A C R O S + *---------------------------------------------------------------------------------------- + */ + +/*---------------------------------------------------------------------------------------- + * T Y P E D E F S A N D S T R U C T U R E S + *---------------------------------------------------------------------------------------- + */ + +/*---------------------------------------------------------------------------------------- + * P R O T O T Y P E S O F L O C A L F U N C T I O N S + *---------------------------------------------------------------------------------------- + */ + +/*---------------------------------------------------------------------------------------- + * E X P O R T E D F U N C T I O N S + *---------------------------------------------------------------------------------------- + */ + +/*---------------------------------------------------------------------------------------*/ +/** + * Family 14h model 0 - 0xF core 0 entry point for programming registers for lower + * power consumption. + * + * Set up D18F6x94[CpuPstateThrEn, CpuPstateThr], and D18F4x134[IntRateCC6DecrRate + * according to the BKDG. + * + * @param[in] FamilySpecificServices The current Family Specific Services. + * @param[in] CpuEarlyParams Service parameters + * @param[in] StdHeader Config handle for library and services. + * + */ +VOID +F14OptimizeForLowPowerInit ( + IN CPU_SPECIFIC_SERVICES *FamilySpecificServices, + IN AMD_CPU_EARLY_PARAMS *CpuEarlyParams, + IN AMD_CONFIG_PARAMS *StdHeader + ) +{ + UINT8 NumBoostStates; + UINT32 LocalPciRegister; + BOOLEAN OptimizeForLowPower; + BOOLEAN IsRevC; + PCI_ADDR PciAddress; + CPU_LOGICAL_ID CpuFamilyRevision; + + PciAddress.AddressValue = PRODUCT_INFO_PCI_ADDR; + LibAmdPciRead (AccessWidth32, PciAddress, &LocalPciRegister, StdHeader); + + if ((((PRODUCT_INFO_REGISTER *) &LocalPciRegister)->LowPowerDefault == 1) && + (CpuEarlyParams->PlatformConfig.PlatformProfile.PlatformPowerPolicy == BatteryLife)) { + OptimizeForLowPower = TRUE; + } else { + OptimizeForLowPower = FALSE; + } + + // Get F4x15C [4:2] NumBoostStates + // Get IsRevC + NumBoostStates = 0; + IsRevC = FALSE; + GetLogicalIdOfCurrentCore (&CpuFamilyRevision, StdHeader); + if ((CpuFamilyRevision.Revision & AMD_F14_ON_Cx) != 0) { + IsRevC = TRUE; + PciAddress.AddressValue = CPB_CTRL_PCI_ADDR; + LibAmdPciRead (AccessWidth32, PciAddress, &LocalPciRegister, StdHeader); + NumBoostStates = (UINT8) ((CPB_CTRL_REGISTER *) &LocalPciRegister)->NumBoostStates; + } + + // F6x94[2:0] CpuPstateThr + PciAddress.AddressValue = NB_PSTATE_CFG_HIGH_PCI_ADDR; + LibAmdPciRead (AccessWidth32, PciAddress, &LocalPciRegister, StdHeader); + if (OptimizeForLowPower) { + ((NB_PSTATE_CFG_HIGH_REGISTER *) &LocalPciRegister)->CpuPstateThr = 0; + } else { + if (NumBoostStates == 0) { + ((NB_PSTATE_CFG_HIGH_REGISTER *) &LocalPciRegister)->CpuPstateThr = 1; + } else { + ((NB_PSTATE_CFG_HIGH_REGISTER *) &LocalPciRegister)->CpuPstateThr = 2; + } + } + // F6x94[3] CpuPstateThrEn = 1 + ((NB_PSTATE_CFG_HIGH_REGISTER *) &LocalPciRegister)->CpuPstateThrEn = 1; + LibAmdPciWrite (AccessWidth32, PciAddress, &LocalPciRegister, StdHeader); + + // F4x134[31:27] IntRateCC6DecrRate + PciAddress.AddressValue = CSTATE_MON_CTRL3_PCI_ADDR; + LibAmdPciRead (AccessWidth32, PciAddress, &LocalPciRegister, StdHeader); + ((CSTATE_MON_CTRL3_REGISTER *) &LocalPciRegister)->IntRateCC6DecrRate = (OptimizeForLowPower || IsRevC) ? 0x18 : 0x8; + LibAmdPciWrite (AccessWidth32, PciAddress, &LocalPciRegister, StdHeader); +} diff --git a/src/vendorcode/amd/agesa/f14/Proc/CPU/Family/0x14/cpuF14LowPowerInit.h b/src/vendorcode/amd/agesa/f14/Proc/CPU/Family/0x14/cpuF14LowPowerInit.h new file mode 100644 index 0000000000..271036e16d --- /dev/null +++ b/src/vendorcode/amd/agesa/f14/Proc/CPU/Family/0x14/cpuF14LowPowerInit.h @@ -0,0 +1,77 @@ +/* $NoKeywords:$ */ +/** + * @file + * + * AMD Family_14 Optimizations for Low Power + * + * @xrefitem bom "File Content Label" "Release Content" + * @e project: AGESA + * @e sub-project: CPU/Family/F14 + * @e \$Revision: 45578 $ @e \$Date: 2011-01-18 19:20:41 -0500 (Tue, 18 Jan 2011) $ + * + */ +/* + ****************************************************************************** + * + * Copyright (c) 2011, Advanced Micro Devices, Inc. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * * Neither the name of Advanced Micro Devices, Inc. nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY + * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND + * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************** + */ + +#ifndef _F14_LOW_POWER_INIT_H_ +#define _F14_LOW_POWER_INIT_H_ + + +/*--------------------------------------------------------------------------------------- + * M I X E D (Definitions And Macros / Typedefs, Structures, Enums) + *--------------------------------------------------------------------------------------- + */ + + +/*--------------------------------------------------------------------------------------- + * D E F I N I T I O N S A N D M A C R O S + *--------------------------------------------------------------------------------------- + */ + + +/*--------------------------------------------------------------------------------------- + * T Y P E D E F S, S T R U C T U R E S, E N U M S + *--------------------------------------------------------------------------------------- + */ + + +/*--------------------------------------------------------------------------------------- + * F U N C T I O N P R O T O T Y P E + *--------------------------------------------------------------------------------------- + */ +VOID +F14OptimizeForLowPowerInit ( + IN CPU_SPECIFIC_SERVICES *FamilySpecificServices, + IN AMD_CPU_EARLY_PARAMS *CpuEarlyParams, + IN AMD_CONFIG_PARAMS *StdHeader + ); + +#endif // _F14_LOW_POWER_INIT_H_ diff --git a/src/vendorcode/amd/agesa/f14/Proc/CPU/Family/0x14/cpuF14MsrTables.c b/src/vendorcode/amd/agesa/f14/Proc/CPU/Family/0x14/cpuF14MsrTables.c index eeb417317d..6c5ce28410 100644 --- a/src/vendorcode/amd/agesa/f14/Proc/CPU/Family/0x14/cpuF14MsrTables.c +++ b/src/vendorcode/amd/agesa/f14/Proc/CPU/Family/0x14/cpuF14MsrTables.c @@ -7,7 +7,7 @@ * @xrefitem bom "File Content Label" "Release Content" * @e project: AGESA * @e sub-project: CPU - * @e \$Revision: 37263 $ @e \$Date: 2010-09-01 21:58:26 +0800 (Wed, 01 Sep 2010) $ + * @e \$Revision: 48588 $ @e \$Date: 2011-03-10 08:57:36 -0700 (Thu, 10 Mar 2011) $ * */ /* @@ -77,6 +77,21 @@ CONST MSR_TYPE_ENTRY_INITIALIZER ROMDATA F14MsrRegisters[] = // M S R T a b l e s // ---------------------- +// MC0_CTL_MASK (0xC0010044) +// bit[6] = 1, erratum #628 + { + MsrRegister, + { + AMD_FAMILY_14, // CpuFamily + AMD_F14_ON_ALL // CpuRevision + }, + {AMD_PF_ALL}, // platformFeatures + {{ + MSR_MC0_CTL_MASK, // MSR Address + 0x0000000000000040, // OR Mask + 0x0000000000000040, // NAND Mask + }} + }, // MSR_TOM2 (0xC001001D) // bits[63:0] - TOP_MEM2 = 0 { @@ -85,12 +100,12 @@ CONST MSR_TYPE_ENTRY_INITIALIZER ROMDATA F14MsrRegisters[] = AMD_FAMILY_14, // CpuFamily AMD_F14_ALL // CpuRevision }, - AMD_PF_ALL, // platformFeatures - { + {AMD_PF_ALL}, // platformFeatures + {{ MSR_TOM2, // MSR Address 0x0000000000000000, // OR Mask 0xFFFFFFFFFFFFFFFF, // NAND Mask - } + }} }, // MSR_SYS_CFG (0xC0010010) // bit[21] - MtrrTom2En = 1 @@ -100,12 +115,12 @@ CONST MSR_TYPE_ENTRY_INITIALIZER ROMDATA F14MsrRegisters[] = AMD_FAMILY_14, // CpuFamily AMD_F14_ALL // CpuRevision }, - AMD_PF_ALL, // platformFeatures - { + {AMD_PF_ALL}, // platformFeatures + {{ MSR_SYS_CFG, // MSR Address (1 << 21), // OR Mask (1 << 21), // NAND Mask - } + }} }, // MSR_CPUID_EXT_FEATS (0xC0011005) // bit[41] - OSVW = 0 @@ -115,12 +130,12 @@ CONST MSR_TYPE_ENTRY_INITIALIZER ROMDATA F14MsrRegisters[] = AMD_FAMILY_14, // CpuFamily AMD_F14_ALL // CpuRevision }, - AMD_PF_ALL, // platformFeatures - { + {AMD_PF_ALL}, // platformFeatures + {{ MSR_CPUID_EXT_FEATS, // MSR Address 0x0000000000000000, // OR Mask 0x0000020000000000, // NAND Mask - } + }} }, // MSR_OSVW_ID_Length (0xC0010140) // bit[15:0] = 4 @@ -130,12 +145,12 @@ CONST MSR_TYPE_ENTRY_INITIALIZER ROMDATA F14MsrRegisters[] = AMD_FAMILY_14, // CpuFamily AMD_F14_ALL // CpuRevision }, - AMD_PF_ALL, // platformFeatures - { + {AMD_PF_ALL}, // platformFeatures + {{ MSR_OSVW_ID_Length, // MSR Address 0x0000000000000004, // OR Mask 0x000000000000FFFF, // NAND Mask - } + }} }, // MSR_HWCR (0xC0010015) // Do not set bit[24] = 1, it will be set in AmdInitPost. @@ -149,12 +164,12 @@ CONST MSR_TYPE_ENTRY_INITIALIZER ROMDATA F14MsrRegisters[] = AMD_FAMILY_14, // CpuFamily AMD_F14_ALL // CpuRevision }, - AMD_PF_ALL, // platformFeatures - { + {AMD_PF_ALL}, // platformFeatures + {{ MSR_MC0_CTL, // MSR Address 0xFFFFFFFFFFFFFFFF, // OR Mask 0xFFFFFFFFFFFFFFFF, // NAND Mask - } + }} }, // MSR_LS_CFG (0xC0011020) // bit[36] Reserved = 1, workaround for erratum #530 @@ -165,12 +180,12 @@ CONST MSR_TYPE_ENTRY_INITIALIZER ROMDATA F14MsrRegisters[] = AMD_FAMILY_14, // CpuFamily AMD_F14_ALL // CpuRevision }, - AMD_PF_ALL, // platformFeatures - { + {AMD_PF_ALL}, // platformFeatures + {{ MSR_LS_CFG, // MSR Address 0x0000001002000000, // OR Mask 0x0000001002000000, // NAND Mask - } + }} }, // MSR_DC_CFG (0xC0011022) // bit[57:56] Reserved = 2 @@ -180,12 +195,12 @@ CONST MSR_TYPE_ENTRY_INITIALIZER ROMDATA F14MsrRegisters[] = AMD_FAMILY_14, // CpuFamily AMD_F14_ALL // CpuRevision }, - AMD_PF_ALL, // platformFeatures - { + {AMD_PF_ALL}, // platformFeatures + {{ MSR_DC_CFG, // MSR Address 0x0200000000000000, // OR Mask 0x0300000000000000, // NAND Mask - } + }} } }; diff --git a/src/vendorcode/amd/agesa/f14/Proc/CPU/Family/0x14/cpuF14PciTables.c b/src/vendorcode/amd/agesa/f14/Proc/CPU/Family/0x14/cpuF14PciTables.c index aab474a865..1673a6dc8c 100644 --- a/src/vendorcode/amd/agesa/f14/Proc/CPU/Family/0x14/cpuF14PciTables.c +++ b/src/vendorcode/amd/agesa/f14/Proc/CPU/Family/0x14/cpuF14PciTables.c @@ -89,12 +89,12 @@ STATIC CONST TABLE_ENTRY_FIELDS ROMDATA F14PciRegisters[] = AMD_FAMILY_14, // CpuFamily AMD_F14_ALL // CpuRevision }, - AMD_PF_ALL, // platformFeatures - { + {AMD_PF_ALL}, // platformFeatures + {{ MAKE_SBDFO (0, 0, 24, FUNC_0, 0x68), // Address 0x002E0800, // regData 0x006E0800, // regMask - } + }} }, // Function 2 - DRAM Controller @@ -106,12 +106,12 @@ STATIC CONST TABLE_ENTRY_FIELDS ROMDATA F14PciRegisters[] = AMD_FAMILY_14, // CpuFamily AMD_F14_ALL // CpuRevision }, - AMD_PF_ALL, // platformFeatures - { + {AMD_PF_ALL}, // platformFeatures + {{ MAKE_SBDFO (0, 0, 24, FUNC_2, 0xB8), // Address 0x00000000, // regData 0xF000F000, // regMask - } + }} }, // D18F2xBC { @@ -120,12 +120,12 @@ STATIC CONST TABLE_ENTRY_FIELDS ROMDATA F14PciRegisters[] = AMD_FAMILY_14, // CpuFamily AMD_F14_ALL // CpuRevision }, - AMD_PF_ALL, // platformFeatures - { + {AMD_PF_ALL}, // platformFeatures + {{ MAKE_SBDFO (0, 0, 24, FUNC_2, 0xBC), // Address 0x00000000, // regData 0xC0000000, // regMask - } + }} }, // D18F2x118 - Memory Controller Configuration Low // bits[7:6], MctPriHiWr = 10b @@ -135,12 +135,12 @@ STATIC CONST TABLE_ENTRY_FIELDS ROMDATA F14PciRegisters[] = AMD_FAMILY_14, // CpuFamily AMD_F14_ALL // CpuRevision }, - AMD_PF_ALL, // platformFeatures - { + {AMD_PF_ALL}, // platformFeatures + {{ MAKE_SBDFO (0, 0, 24, FUNC_2, 0x118), // Address 0x00000080, // regData 0x000000C0, // regMask - } + }} }, // D18F2x11C - Memory Controller Configuration High // bits[24:22], PrefConf = 1 @@ -150,12 +150,12 @@ STATIC CONST TABLE_ENTRY_FIELDS ROMDATA F14PciRegisters[] = AMD_FAMILY_14, // CpuFamily AMD_F14_ALL // CpuRevision }, - AMD_PF_ALL, // platformFeatures - { + {AMD_PF_ALL}, // platformFeatures + {{ MAKE_SBDFO (0, 0, 24, FUNC_2, 0x11C), // Address 0x00400000, // regData 0x01C00000, // regMask - } + }} }, // Function 3 - Misc. Control @@ -168,12 +168,12 @@ STATIC CONST TABLE_ENTRY_FIELDS ROMDATA F14PciRegisters[] = AMD_FAMILY_14, // CpuFamily AMD_F14_ALL // CpuRevision }, - AMD_PF_ALL, // platformFeatures - { + {AMD_PF_ALL}, // platformFeatures + {{ MAKE_SBDFO (0, 0, 24, FUNC_3, 0x40), // Address 0x00000100, // regData 0x00000100, // regMask - } + }} }, // D18F3x44 - MCA NB Configuration // bit[27] NbMcaToMstCpuEn = 1 @@ -189,12 +189,12 @@ STATIC CONST TABLE_ENTRY_FIELDS ROMDATA F14PciRegisters[] = AMD_FAMILY_14, // CpuFamily AMD_F14_ALL // CpuRevision }, - AMD_PF_ALL, // platformFeatures - { + {AMD_PF_ALL}, // platformFeatures + {{ MAKE_SBDFO (0, 0, 24, FUNC_3, 0x44), // Address 0x0A300040, // regData 0x0A303E40, // regMask - } + }} }, // D18F3x84 - ACPI Power State Control High // bit[18] Smaf6DramMemClkTri = 1 @@ -207,12 +207,12 @@ STATIC CONST TABLE_ENTRY_FIELDS ROMDATA F14PciRegisters[] = AMD_FAMILY_14, // CpuFamily AMD_F14_ALL // CpuRevision }, - AMD_PF_ALL, // platformFeatures - { + {AMD_PF_ALL}, // platformFeatures + {{ MAKE_SBDFO (0, 0, 24, FUNC_3, 0x84), // Address 0x00060006, // regData 0x00060006, // regMask - } + }} }, // D18F3x8C - NB Configuration High // bit[26] EnConvertToNonIsoc = 1 @@ -222,12 +222,12 @@ STATIC CONST TABLE_ENTRY_FIELDS ROMDATA F14PciRegisters[] = AMD_FAMILY_14, // CpuFamily AMD_F14_ALL // CpuRevision }, - AMD_PF_ALL, // platformFeatures - { + {AMD_PF_ALL}, // platformFeatures + {{ MAKE_SBDFO (0, 0, 24, FUNC_3, 0x8C), // Address 0x04000000, // regData 0x04000000, // regMask - } + }} }, // D18F3xA0 - Power Control Miscellaneous // bit[9] SviHighFreqSel = 1 @@ -237,12 +237,12 @@ STATIC CONST TABLE_ENTRY_FIELDS ROMDATA F14PciRegisters[] = AMD_FAMILY_14, // CpuFamily AMD_F14_ALL // CpuRevision }, - AMD_PF_ALL, // platformFeatures - { + {AMD_PF_ALL}, // platformFeatures + {{ MAKE_SBDFO (0, 0, 24, FUNC_3, 0xA0), // Address 0x00000200, // regData 0x00000200, // regMask - } + }} }, // D18F3xA4 - Reported Temperature Control // bits[12:8] PerStepTimeDn = 0xF @@ -256,12 +256,12 @@ STATIC CONST TABLE_ENTRY_FIELDS ROMDATA F14PciRegisters[] = AMD_FAMILY_14, // CpuFamily AMD_F14_ALL // CpuRevision }, - AMD_PF_ALL, // platformFeatures - { + {AMD_PF_ALL}, // platformFeatures + {{ MAKE_SBDFO (0, 0, 24, FUNC_3, 0xA4), // Address 0x00000FEF, // regData 0x00001FFF, // regMask - } + }} }, // D18F3xD4 - Clock Power Timing Control 0 // bits[11:8] ClkRampHystSel = 0xF @@ -273,16 +273,16 @@ STATIC CONST TABLE_ENTRY_FIELDS ROMDATA F14PciRegisters[] = AMD_FAMILY_14, // CpuFamily AMD_F14_ALL // CpuRevision }, - AMD_PF_ALL, // platformFeatures - { + {AMD_PF_ALL}, // platformFeatures + {{ MAKE_SBDFO (0, 0, 24, FUNC_3, 0xD4), // Address 0x00024F00, // regData 0x0002FF00, // regMask - } + }} }, // D18F3xDC - Clock Power Timing Control 2 // bits[29:27] NbClockGateHyst = 3 -// bit[30] NbClockGateEn = 1 +// bit[30] NbClockGateEn = 0 - erratum #596 // bit[31] CnbCifClockGateEn = 1 { PciRegister, @@ -290,12 +290,12 @@ STATIC CONST TABLE_ENTRY_FIELDS ROMDATA F14PciRegisters[] = AMD_FAMILY_14, // CpuFamily AMD_F14_ALL // CpuRevision }, - AMD_PF_ALL, // platformFeatures - { + {AMD_PF_ALL}, // platformFeatures + {{ MAKE_SBDFO (0, 0, 24, FUNC_3, 0xDC), // Address - 0xD8000000, // regData + 0x98000000, // regData 0xF8000000, // regMask - } + }} }, // D18F3x180 - Extended NB MCA Configuration // bit[2] WDTCntSel[3] = 0 @@ -307,12 +307,12 @@ STATIC CONST TABLE_ENTRY_FIELDS ROMDATA F14PciRegisters[] = AMD_FAMILY_14, // CpuFamily AMD_F14_ALL // CpuRevision }, - AMD_PF_ALL, // platformFeatures - { + {AMD_PF_ALL}, // platformFeatures + {{ MAKE_SBDFO (0, 0, 24, FUNC_3, 0x180), // Address 0x00200020, // regData 0x00200024, // regMask - } + }} }, // D18F3x188 - NB Extended Configuration // bit[21] EnCpuSerWrBehindIoRd = 0 @@ -325,12 +325,12 @@ STATIC CONST TABLE_ENTRY_FIELDS ROMDATA F14PciRegisters[] = AMD_FAMILY_14, // CpuFamily AMD_F14_ALL // CpuRevision }, - AMD_PF_ALL, // platformFeatures - { + {AMD_PF_ALL}, // platformFeatures + {{ MAKE_SBDFO (0, 0, 24, FUNC_3, 0x188), // Address 0x1B000000, // regData 0xFFA00000, // regMask - } + }} }, // Function 4 - Extended Misc. Control @@ -344,12 +344,12 @@ STATIC CONST TABLE_ENTRY_FIELDS ROMDATA F14PciRegisters[] = AMD_FAMILY_14, // CpuFamily AMD_F14_ALL // CpuRevision }, - AMD_PF_ALL, // platformFeatures - { + {AMD_PF_ALL}, // platformFeatures + {{ MAKE_SBDFO (0, 0, 24, FUNC_4, 0x118), // Address 0x00000000, // regData 0x00000707, // regMask - } + }} }, // D18F4x124 - C-state Monitor Control 1 // bit[15] TimerTickIntvlScale = 1 @@ -364,12 +364,12 @@ STATIC CONST TABLE_ENTRY_FIELDS ROMDATA F14PciRegisters[] = AMD_FAMILY_14, // CpuFamily AMD_F14_ALL // CpuRevision }, - AMD_PF_ALL, // platformFeatures - { + {AMD_PF_ALL}, // platformFeatures + {{ MAKE_SBDFO (0, 0, 24, FUNC_4, 0x124), // Address 0x05138000, // regData 0x07FF8000, // regMask - } + }} }, // D18F4x134 - C-state Monitor Control 3 // bits[3:0] IntRatePkgC6MaxDepth = 0 @@ -379,19 +379,18 @@ STATIC CONST TABLE_ENTRY_FIELDS ROMDATA F14PciRegisters[] = // bits[19:16] IntRateCC6MaxDepth = 5 // bits[23:20] IntRateCC6Threshold = 4 // bits[26:24] IntRateCC6BurstLen = 5 -// bits[31:27] IntRateCC6DecrRate = 0x08 { PciRegister, { AMD_FAMILY_14, // CpuFamily AMD_F14_ALL // CpuRevision }, - AMD_PF_ALL, // platformFeatures - { + {AMD_PF_ALL}, // platformFeatures + {{ MAKE_SBDFO (0, 0, 24, FUNC_4, 0x134), // Address - 0x45455100, // regData - 0xFFFFFFFF, // regMask - } + 0x05455100, // regData + 0x07FFFFFF, // regMask + }} }, // D18F4x13C - SMAF Code DID 1 // bits[4:0] Smaf4Did = 0x0F @@ -402,12 +401,12 @@ STATIC CONST TABLE_ENTRY_FIELDS ROMDATA F14PciRegisters[] = AMD_FAMILY_14, // CpuFamily AMD_F14_ALL // CpuRevision }, - AMD_PF_ALL, // platformFeatures - { + {AMD_PF_ALL}, // platformFeatures + {{ MAKE_SBDFO (0, 0, 24, FUNC_4, 0x13C), // Address 0x000F000F, // regData 0x001F001F, // regMask - } + }} }, // D18F4x1A4 - C-state Monitor Mask // bits[7:0] IntRateMonMask = 0xFC @@ -420,12 +419,12 @@ STATIC CONST TABLE_ENTRY_FIELDS ROMDATA F14PciRegisters[] = AMD_FAMILY_14, // CpuFamily AMD_F14_ALL // CpuRevision }, - AMD_PF_ALL, // platformFeatures - { + {AMD_PF_ALL}, // platformFeatures + {{ MAKE_SBDFO (0, 0, 24, FUNC_4, 0x1A4), // Address 0xFFFFFFFC, // regData 0xFFFFFFFF, // regMask - } + }} }, // D18F4x1A8 - CPU State Power Management Dynamic Control 0 // bits[4:0] SingleHaltCpuDid = 0x1E @@ -439,12 +438,12 @@ STATIC CONST TABLE_ENTRY_FIELDS ROMDATA F14PciRegisters[] = AMD_FAMILY_14, // CpuFamily AMD_F14_ALL // CpuRevision }, - AMD_PF_ALL, // platformFeatures - { + {AMD_PF_ALL}, // platformFeatures + {{ MAKE_SBDFO (0, 0, 24, FUNC_4, 0x1A8), // Address 0x009003FE, // regData 0x00F083FF, // regMask - } + }} }, // D18F4x1AC - CPU State Power Management Dynamic Control 1 // bits[9:5] C6Did = 0x1F @@ -456,12 +455,12 @@ STATIC CONST TABLE_ENTRY_FIELDS ROMDATA F14PciRegisters[] = AMD_FAMILY_14, // CpuFamily AMD_F14_ALL // CpuRevision }, - AMD_PF_ALL, // platformFeatures - { + {AMD_PF_ALL}, // platformFeatures + {{ MAKE_SBDFO (0, 0, 24, FUNC_4, 0x1AC), // Address 0x300003E0, // regData 0x300003E0, // regMask - } + }} }, // D18F6x50 - Configuration Register Access Control // bit[1] CfgAccAddrMode = 0 @@ -471,12 +470,12 @@ STATIC CONST TABLE_ENTRY_FIELDS ROMDATA F14PciRegisters[] = AMD_FAMILY_14, // CpuFamily AMD_F14_ALL // CpuRevision }, - AMD_PF_ALL, // platformFeatures - { + {AMD_PF_ALL}, // platformFeatures + {{ MAKE_SBDFO (0, 0, 24, FUNC_6, 0x50), // Address 0x00000000, // regData 0x00000002, // regMask - } + }} }, // D18F6x54 - DRAM Arbitration Control FEQ Collision // bits[7:0] FeqLoPrio = 0x20 @@ -489,12 +488,12 @@ STATIC CONST TABLE_ENTRY_FIELDS ROMDATA F14PciRegisters[] = AMD_FAMILY_14, // CpuFamily AMD_F14_ALL // CpuRevision }, - AMD_PF_ALL, // platformFeatures - { + {AMD_PF_ALL}, // platformFeatures + {{ MAKE_SBDFO (0, 0, 24, FUNC_6, 0x54), // Address 0x00081020, // regData 0x80FFFFFF, // regMask - } + }} }, // D18F6x58 - DRAM Arbitration Control Display Collision // bits[7:0] DispLoPrio = 0x40 @@ -507,12 +506,12 @@ STATIC CONST TABLE_ENTRY_FIELDS ROMDATA F14PciRegisters[] = AMD_FAMILY_14, // CpuFamily AMD_F14_ALL // CpuRevision }, - AMD_PF_ALL, // platformFeatures - { + {AMD_PF_ALL}, // platformFeatures + {{ MAKE_SBDFO (0, 0, 24, FUNC_6, 0x58), // Address 0x00102040, // regData 0xFFFFFFFF, // regMask - } + }} }, // D18F6x5C - DRAM Arbitration Control FEQ Write Protect // bits[7:0] FeqLoPrio = 0x20 @@ -525,12 +524,12 @@ STATIC CONST TABLE_ENTRY_FIELDS ROMDATA F14PciRegisters[] = AMD_FAMILY_14, // CpuFamily AMD_F14_ALL // CpuRevision }, - AMD_PF_ALL, // platformFeatures - { + {AMD_PF_ALL}, // platformFeatures + {{ MAKE_SBDFO (0, 0, 24, FUNC_6, 0x5C), // Address 0x00081020, // regData 0x80FFFFFF, // regMask - } + }} }, // D18F6x60 - DRAM Arbitration Control Display Write Protect // bits[7:0] DispLoPri = 0x20 @@ -543,12 +542,12 @@ STATIC CONST TABLE_ENTRY_FIELDS ROMDATA F14PciRegisters[] = AMD_FAMILY_14, // CpuFamily AMD_F14_ALL // CpuRevision }, - AMD_PF_ALL, // platformFeatures - { + {AMD_PF_ALL}, // platformFeatures + {{ MAKE_SBDFO (0, 0, 24, FUNC_6, 0x60), // Address 0x00081020, // regData 0xFFFFFFFF, // regMask - } + }} }, // D18F6x64 - DRAM Arbitration Control FEQ Read Protect // bits[7:0] FeqLoPrio = 0x10 @@ -561,12 +560,12 @@ STATIC CONST TABLE_ENTRY_FIELDS ROMDATA F14PciRegisters[] = AMD_FAMILY_14, // CpuFamily AMD_F14_ALL // CpuRevision }, - AMD_PF_ALL, // platformFeatures - { + {AMD_PF_ALL}, // platformFeatures + {{ MAKE_SBDFO (0, 0, 24, FUNC_6, 0x64), // Address 0x00040810, // regData 0x80FFFFFF, // regMask - } + }} }, // D18F6x68 - DRAM Arbitration Control Display Read Protect // bits[7:0] DispLoPrio = 0x10 @@ -579,12 +578,12 @@ STATIC CONST TABLE_ENTRY_FIELDS ROMDATA F14PciRegisters[] = AMD_FAMILY_14, // CpuFamily AMD_F14_ALL // CpuRevision }, - AMD_PF_ALL, // platformFeatures - { + {AMD_PF_ALL}, // platformFeatures + {{ MAKE_SBDFO (0, 0, 24, FUNC_6, 0x68), // Address 0x00040810, // regData 0xFFFFFFFF, // regMask - } + }} }, // D18F6x6C - DRAM Arbitration Control FEQ Fairness Timer // bits[7:0] FeqLoPrio = 0x80 @@ -596,12 +595,12 @@ STATIC CONST TABLE_ENTRY_FIELDS ROMDATA F14PciRegisters[] = AMD_FAMILY_14, // CpuFamily AMD_F14_ALL // CpuRevision }, - AMD_PF_ALL, // platformFeatures - { + {AMD_PF_ALL}, // platformFeatures + {{ MAKE_SBDFO (0, 0, 24, FUNC_6, 0x6C), // Address 0x00204080, // regData 0x00FFFFFF, // regMask - } + }} }, // D18F6x70 - DRAM Arbitration Control Display Fairness Timer // bits[7:0] DispLoPrio = 0x80 @@ -614,12 +613,12 @@ STATIC CONST TABLE_ENTRY_FIELDS ROMDATA F14PciRegisters[] = AMD_FAMILY_14, // CpuFamily AMD_F14_ALL // CpuRevision }, - AMD_PF_ALL, // platformFeatures - { + {AMD_PF_ALL}, // platformFeatures + {{ MAKE_SBDFO (0, 0, 24, FUNC_6, 0x70), // Address 0x00204080, // regData 0xFFFFFFFF, // regMask - } + }} }, // D18F6x74 - Dram Idle Page Close Limit // bits[40] IdleLimit = 0x1E @@ -629,12 +628,12 @@ STATIC CONST TABLE_ENTRY_FIELDS ROMDATA F14PciRegisters[] = AMD_FAMILY_14, // CpuFamily AMD_F14_ALL // CpuRevision }, - AMD_PF_ALL, // platformFeatures - { + {AMD_PF_ALL}, // platformFeatures + {{ MAKE_SBDFO (0, 0, 24, FUNC_6, 0x74), // Address 0x0000001E, // regData 0x0000001F, // regMask - } + }} }, // D18F6x78 - Dram Prioritization and Arbitration Control // bits[1:0] DispDbePrioEn = 3 @@ -648,12 +647,12 @@ STATIC CONST TABLE_ENTRY_FIELDS ROMDATA F14PciRegisters[] = AMD_FAMILY_14, // CpuFamily AMD_F14_ALL // CpuRevision }, - AMD_PF_ALL, // platformFeatures - { + {AMD_PF_ALL}, // platformFeatures + {{ MAKE_SBDFO (0, 0, 24, FUNC_6, 0x78), // Address 0x00000037, // regData 0x0000007F, // regMask - } + }} }, // D18F6x90 - NB P-state Config Low // As part of BIOS Requirements for NB P-state Initialization @@ -666,16 +665,14 @@ STATIC CONST TABLE_ENTRY_FIELDS ROMDATA F14PciRegisters[] = AMD_FAMILY_14, // CpuFamily AMD_F14_ALL // CpuRevision }, - AMD_PF_ALL, // platformFeatures - { + {AMD_PF_ALL}, // platformFeatures + {{ MAKE_SBDFO (0, 0, 24, FUNC_6, 0x90), // Address 0x50000000, // regData 0x70000000, // regMask - } + }} }, // D18F6x94 - NB P-state Config High -// bits[2:0] CpuPstateThr = 1 -// bit[3] CpuPstateThrEn = 1 // bits[25:23] NbPsC0Timer = 4 { PciRegister, @@ -683,12 +680,12 @@ STATIC CONST TABLE_ENTRY_FIELDS ROMDATA F14PciRegisters[] = AMD_FAMILY_14, // CpuFamily AMD_F14_ALL // CpuRevision }, - AMD_PF_ALL, // platformFeatures - { + {AMD_PF_ALL}, // platformFeatures + {{ MAKE_SBDFO (0, 0, 24, FUNC_6, 0x94), // Address - 0x02000009, // regData - 0x0380000F, // regMask - } + 0x02000000, // regData + 0x03800000, // regMask + }} }, // D18F6x9C - NCLK Reduction Control // bits[6:0] NclkRedDiv = 0x60 @@ -700,12 +697,12 @@ STATIC CONST TABLE_ENTRY_FIELDS ROMDATA F14PciRegisters[] = AMD_FAMILY_14, // CpuFamily AMD_F14_ALL // CpuRevision }, - AMD_PF_ALL, // platformFeatures - { + {AMD_PF_ALL}, // platformFeatures + {{ MAKE_SBDFO (0, 0, 24, FUNC_6, 0x9C), // Address 0x000001E0, // regData 0x000001FF, // regMask - } + }} } }; diff --git a/src/vendorcode/amd/agesa/f14/Proc/CPU/Family/0x14/cpuF14PerCorePciTables.c b/src/vendorcode/amd/agesa/f14/Proc/CPU/Family/0x14/cpuF14PerCorePciTables.c index b75e69fac5..8ca7bc524f 100644 --- a/src/vendorcode/amd/agesa/f14/Proc/CPU/Family/0x14/cpuF14PerCorePciTables.c +++ b/src/vendorcode/amd/agesa/f14/Proc/CPU/Family/0x14/cpuF14PerCorePciTables.c @@ -86,12 +86,12 @@ STATIC CONST TABLE_ENTRY_FIELDS ROMDATA F14PerCorePciRegisters[] = AMD_FAMILY_14, // CpuFamily AMD_F14_ALL // CpuRevision }, - AMD_PF_ALL, // platformFeatures - { + {AMD_PF_ALL}, // platformFeatures + {{ MAKE_SBDFO (0, 0, 24, FUNC_3, 0x1CC), // Address 0x00000100, // regData 0x0000010F, // regMask - } + }} } }; diff --git a/src/vendorcode/amd/agesa/f14/Proc/CPU/Family/0x14/cpuF14PowerCheck.c b/src/vendorcode/amd/agesa/f14/Proc/CPU/Family/0x14/cpuF14PowerCheck.c index 53e6df5163..6a1d15ab5c 100644 --- a/src/vendorcode/amd/agesa/f14/Proc/CPU/Family/0x14/cpuF14PowerCheck.c +++ b/src/vendorcode/amd/agesa/f14/Proc/CPU/Family/0x14/cpuF14PowerCheck.c @@ -10,7 +10,7 @@ * @xrefitem bom "File Content Label" "Release Content" * @e project: AGESA * @e sub-project: CPU/F14 - * @e \$Revision: 39744 $ @e \$Date: 2010-10-15 02:18:02 +0800 (Fri, 15 Oct 2010) $ + * @e \$Revision: 46951 $ @e \$Date: 2011-02-11 12:37:59 -0700 (Fri, 11 Feb 2011) $ * */ /* @@ -51,7 +51,6 @@ */ #include "AGESA.h" #include "amdlib.h" -#include "cpuCacheInit.h" #include "cpuF14PowerMgmt.h" #include "cpuRegisters.h" #include "cpuApicUtilities.h" @@ -60,7 +59,6 @@ #include "cpuEarlyInit.h" #include "cpuFamilyTranslation.h" #include "cpuF14PowerCheck.h" -#include "cpuF14Utilities.h" #include "Filecode.h" #define FILECODE PROC_CPU_FAMILY_0X14_CPUF14POWERCHECK_FILECODE @@ -100,18 +98,18 @@ F14PmPwrChkCopyPstate ( /*---------------------------------------------------------------------------------------*/ /** - * Family 14h core 0 entry point for performing the family 14h Processor- + * Family 14h Ontario core 0 entry point for performing the family 14h Ontario Processor- * Systemboard Power Delivery Check. * * The steps are as follows: - * 1. Starting with P0, loop through all P-states until a passing state is + * 1. Starting with hardware P0, loop through all P-states until a passing state is * found. A passing state is one in which the current required by the * CPU is less than the maximum amount of current that the system can * provide to the CPU. If P0 is under the limit, no further action is * necessary. * 2. If at least one P-State is under the limit & at least one P-State is * over the limit, the BIOS must: - * a. Clear both D18F4x15C[BoostSrc] and D18F4x15C[NumBoostStates] to 0. + * a. Program D18F4x15C[BoostSrc]=0. * b. If the processor's current P-State is disabled by the power check, * then the BIOS must request a transition to an enabled P-state * using MSRC001_0062[PstateCmd] and wait for MSRC001_0063[CurPstate] @@ -126,7 +124,7 @@ F14PmPwrChkCopyPstate ( * 1. D18F3x64[HtcPstateLimit] * 2. D18F3xDC[PstateMaxVal] * 3. If all P-States are over the limit, the BIOS must: - * a. Clear both D18F4x15C[BoostSrc] and D18F4x15C[NumBoostStates] to 0. + * a. Program D18F4x15C[BoostSrc]=0. * b. If the processor's current P-State is != D18F3xDC[PstateMaxVal], then * write D18F3xDC[PstateMaxVal] to MSRC001_0062[PstateCmd] and wait for * MSRC001_0063[CurPstate] to reflect the new value. @@ -151,17 +149,24 @@ F14PmPwrCheck ( IN AMD_CONFIG_PARAMS *StdHeader ) { - UINT8 DisPsNum; + UINT8 DisHwPsNum; + UINT8 DisSwPsNum; UINT8 PsMaxVal; UINT8 Pstate; + UINT8 PstateLimit; + UINT8 NumberBoostStates; UINT32 ProcIddMax; - UINT32 PciRegister; UINT32 Socket; UINT32 Module; UINT32 Core; - UINT32 PstateLimit; PCI_ADDR PciAddress; - UINT64 MsrRegister; + UINT64 LocalMsrRegister; + BOOLEAN ThermalPstateEn; + NB_CAPS_REGISTER NbCaps; + HTC_REGISTER HtcReg; + CLK_PWR_TIMING_CTRL2_REGISTER ClkPwrTimingCtrl2; + CPB_CTRL_REGISTER CpbCtrl; + CPU_LOGICAL_ID CpuFamilyRevision; AP_TASK TaskPtr; AGESA_STATUS IgnoredSts; PWRCHK_ERROR_DATA ErrorData; @@ -172,17 +177,53 @@ F14PmPwrCheck ( ASSERT (Core == 0); + // save ThermalPstateEn + // TRUE if the P-state indicated by D18F3x64[HtcPstateLimit] is enabled; + // FALSE otherwise. + PciAddress.AddressValue = HTC_PCI_ADDR; + LibAmdPciRead (AccessWidth32, PciAddress, &HtcReg, StdHeader); // D18F3x64 + LibAmdMsrRead (PS_REG_BASE + HtcReg.HtcPstateLimit, &LocalMsrRegister, StdHeader); + if (((PSTATE_MSR *) &LocalMsrRegister)->PsEnable == 1) { + ThermalPstateEn = TRUE; + } else { + ThermalPstateEn = FALSE; + } + // get the Max P-state value for (PsMaxVal = NM_PS_REG - 1; PsMaxVal != 0; --PsMaxVal) { - LibAmdMsrRead (PS_REG_BASE + PsMaxVal, &MsrRegister, StdHeader); - if (((PSTATE_MSR *) &MsrRegister)->PsEnable == 1) { + LibAmdMsrRead (PS_REG_BASE + PsMaxVal, &LocalMsrRegister, StdHeader); + if (((PSTATE_MSR *) &LocalMsrRegister)->PsEnable == 1) { break; } } ErrorData.HwPstateNumber = (UINT8) (PsMaxVal + 1); - DisPsNum = 0; + // get NumberBoostStates + GetLogicalIdOfCurrentCore (&CpuFamilyRevision, StdHeader); + if ((CpuFamilyRevision.Revision & (AMD_F14_ON_Ax | AMD_F14_ON_Bx)) != 0) { + NumberBoostStates = 0; + } else { + PciAddress.AddressValue = CPB_CTRL_PCI_ADDR; + LibAmdPciRead (AccessWidth32, PciAddress, &CpbCtrl, StdHeader); // D18F4x15C + NumberBoostStates = (UINT8) CpbCtrl.NumBoostStates; + } + + // update PstateMaxVal if warranted by HtcPstateLimit + PciAddress.AddressValue = NB_CAPS_PCI_ADDR; + LibAmdPciRead (AccessWidth32, PciAddress, &NbCaps, StdHeader); + if (NbCaps.HtcCapable == 1) { + if (HtcReg.HtcTmpLmt != 0) { + PciAddress.AddressValue = CPTC2_PCI_ADDR; + LibAmdPciRead (AccessWidth32, PciAddress, &ClkPwrTimingCtrl2, StdHeader); // D18F3xDC + if (HtcReg.HtcPstateLimit > ClkPwrTimingCtrl2.PstateMaxVal) { + ClkPwrTimingCtrl2.PstateMaxVal = HtcReg.HtcPstateLimit; + LibAmdPciWrite (AccessWidth32, PciAddress, &ClkPwrTimingCtrl2, StdHeader); // D18F3xDC + } + } + } + + DisHwPsNum = 0; for (Pstate = 0; Pstate < ErrorData.HwPstateNumber; Pstate++) { if (FamilySpecificServices->GetProcIddMax (FamilySpecificServices, Pstate, &ProcIddMax, StdHeader)) { if (ProcIddMax > CpuEarlyParams->PlatformConfig.VrmProperties[CoreVrm].CurrentLimit) { @@ -190,17 +231,23 @@ F14PmPwrCheck ( PutEventLog (AGESA_WARNING, CPU_EVENT_PM_PSTATE_OVERCURRENT, Socket, Pstate, 0, 0, StdHeader); - DisPsNum++; + DisHwPsNum++; } else { break; } } } + // get the number of software Pstate that is disabled by delivery check + if (NumberBoostStates < DisHwPsNum) { + DisSwPsNum = DisHwPsNum - NumberBoostStates; + } else { + DisSwPsNum = 0; + } // If all P-state registers are disabled, move P[PsMaxVal] to P0 // and transition to P0, then wait for CurPstate = 0 - ErrorData.AllowablePstateNumber = ((PsMaxVal + 1) - DisPsNum); + ErrorData.AllowablePstateNumber = ((PsMaxVal + 1) - DisHwPsNum); // We only need to log this event on the BSC if (ErrorData.AllowablePstateNumber == 0) { @@ -209,7 +256,15 @@ F14PmPwrCheck ( Socket, 0, 0, 0, StdHeader); } - if (DisPsNum != 0) { + if (DisHwPsNum != 0) { + // Program F4x15C[BoostSrc] = 0 + if ((CpuFamilyRevision.Revision & (AMD_F14_ON_Ax | AMD_F14_ON_Bx)) == 0) { + PciAddress.AddressValue = CPB_CTRL_PCI_ADDR; + LibAmdPciRead (AccessWidth32, PciAddress, &CpbCtrl, StdHeader); // D18F4x15C + CpbCtrl.BoostSrc = 0; + LibAmdPciWrite (AccessWidth32, PciAddress, &CpbCtrl, StdHeader); // D18F4x15C + } + TaskPtr.FuncAddress.PfApTaskI = F14PmPwrCheckCore; TaskPtr.DataTransfer.DataSizeInDwords = SIZE_IN_DWORDS (PWRCHK_ERROR_DATA); TaskPtr.DataTransfer.DataPtr = &ErrorData; @@ -220,28 +275,32 @@ F14PmPwrCheck ( // Final Step // D18F3x64[HtPstatelimit] -= disPsNum // D18F3xDC[PstateMaxVal]-= disPsNum - PciAddress.AddressValue = HTC_PCI_ADDR; - LibAmdPciRead (AccessWidth32, PciAddress, &PciRegister, StdHeader); // D18F3x64 - PstateLimit = ((HTC_REGISTER *) &PciRegister)->HtcPstateLimit; - if (PstateLimit > DisPsNum) { - PstateLimit -= DisPsNum; + LibAmdPciRead (AccessWidth32, PciAddress, &HtcReg, StdHeader); // D18F3x64 + PciAddress.AddressValue = NB_CAPS_PCI_ADDR; // D18F3xE8 + LibAmdPciRead (AccessWidth32, PciAddress, &NbCaps, StdHeader); + if (ThermalPstateEn || HtcReg.HtcTmpLmt == 0 || NbCaps.HtcCapable == 0) { + PstateLimit = (UINT8) HtcReg.HtcPstateLimit; + if (PstateLimit > DisHwPsNum) { + PstateLimit = (UINT8) (PstateLimit - DisSwPsNum); } else { - PstateLimit = 0; + PstateLimit = NumberBoostStates; } - ((HTC_REGISTER *) &PciRegister)->HtcPstateLimit = PstateLimit; - LibAmdPciWrite (AccessWidth32, PciAddress, &PciRegister, StdHeader); // D18F3x64 + HtcReg.HtcPstateLimit = PstateLimit; + PciAddress.AddressValue = HTC_PCI_ADDR; + LibAmdPciWrite (AccessWidth32, PciAddress, &HtcReg, StdHeader); // D18F3x64 PciAddress.AddressValue = CPTC2_PCI_ADDR; - LibAmdPciRead (AccessWidth32, PciAddress, &PciRegister, StdHeader); // D18F3xDC - PstateLimit = ((CLK_PWR_TIMING_CTRL2_REGISTER *) &PciRegister)->PstateMaxVal; - if (PstateLimit > DisPsNum) { - PstateLimit -= DisPsNum; + LibAmdPciRead (AccessWidth32, PciAddress, &ClkPwrTimingCtrl2, StdHeader); // D18F3xDC + PstateLimit = (UINT8) ClkPwrTimingCtrl2.PstateMaxVal; + if (PstateLimit > DisHwPsNum) { + PstateLimit = (UINT8) (PstateLimit - DisSwPsNum); } else { - PstateLimit = 0; + PstateLimit = NumberBoostStates; + } + ClkPwrTimingCtrl2.PstateMaxVal = PstateLimit; + LibAmdPciWrite (AccessWidth32, PciAddress, &ClkPwrTimingCtrl2, StdHeader); // D18F3xDC } - ((CLK_PWR_TIMING_CTRL2_REGISTER *) &PciRegister)->PstateMaxVal = PstateLimit; - LibAmdPciWrite (AccessWidth32, PciAddress, &PciRegister, StdHeader); // D18F3xDC } } @@ -265,37 +324,64 @@ F14PmPwrCheckCore ( ) { UINT8 i; - UINT8 PsMaxVal; - UINT8 DisPsNum; - UINT8 CurrentPs; - UINT64 MsrRegister; + UINT8 HardwarePsMaxVal; + UINT8 DisHwPsNum; + UINT8 DisSwPsNum; + UINT8 CurrentSoftwarePs; + UINT8 CurrentHardwarePs; + UINT8 NumberBoostStates; + UINT64 LocalMsrRegister; + CPU_LOGICAL_ID CpuFamilyRevision; + PCI_ADDR PciAddress; + CPB_CTRL_REGISTER CpbCtrl; CPU_SPECIFIC_SERVICES *FamilySpecificServices; - GetCpuServicesOfCurrentCore (&FamilySpecificServices, StdHeader); + GetCpuServicesOfCurrentCore ((const CPU_SPECIFIC_SERVICES **)&FamilySpecificServices, StdHeader); + GetLogicalIdOfCurrentCore (&CpuFamilyRevision, StdHeader); - PsMaxVal = (((PWRCHK_ERROR_DATA *) ErrorData)->HwPstateNumber - 1); - DisPsNum = (((PWRCHK_ERROR_DATA *) ErrorData)->HwPstateNumber - + HardwarePsMaxVal = (((PWRCHK_ERROR_DATA *) ErrorData)->HwPstateNumber - 1); + DisHwPsNum = (((PWRCHK_ERROR_DATA *) ErrorData)->HwPstateNumber - ((PWRCHK_ERROR_DATA *) ErrorData)->AllowablePstateNumber); - LibAmdMsrRead (MSR_PSTATE_STS, &MsrRegister, StdHeader); - CurrentPs = (UINT8) (((PSTATE_STS_MSR *) &MsrRegister)->CurPstate); + LibAmdMsrRead (MSR_PSTATE_STS, &LocalMsrRegister, StdHeader); + CurrentSoftwarePs = (UINT8) (((PSTATE_STS_MSR *) &LocalMsrRegister)->CurPstate); + + if ((CpuFamilyRevision.Revision & (AMD_F14_ON_Ax | AMD_F14_ON_Bx)) != 0) { + NumberBoostStates = 0; + } else { + PciAddress.AddressValue = CPB_CTRL_PCI_ADDR; + LibAmdPciRead (AccessWidth32, PciAddress, &CpbCtrl, StdHeader); // D18F4x15C + NumberBoostStates = (UINT8) CpbCtrl.NumBoostStates; + } + + CurrentHardwarePs = CurrentSoftwarePs + NumberBoostStates; + + if (NumberBoostStates < DisHwPsNum) { + DisSwPsNum = DisHwPsNum - NumberBoostStates; + } else { + DisSwPsNum = 0; + } if (((PWRCHK_ERROR_DATA *) ErrorData)->AllowablePstateNumber == 0) { // Step 1 // Transition to Pstate Max if not there already - if (CurrentPs != PsMaxVal) { - FamilySpecificServices->TransitionPstate (FamilySpecificServices, PsMaxVal, (BOOLEAN) TRUE, StdHeader); + if (CurrentHardwarePs != HardwarePsMaxVal) { + FamilySpecificServices->TransitionPstate (FamilySpecificServices, (HardwarePsMaxVal - NumberBoostStates), (BOOLEAN) TRUE, StdHeader); + CurrentSoftwarePs = HardwarePsMaxVal - NumberBoostStates; } // Step 2 - // If Pstate Max is not P0, copy Pstate max contents to P0 and switch + // If CurrentSoftwarePs is not P0, copy CurrentSoftwarePs contents to Software P0 and switch // to P0. - if (PsMaxVal != 0) { - F14PmPwrChkCopyPstate (0, PsMaxVal, StdHeader); + if (CurrentSoftwarePs != 0) { + F14PmPwrChkCopyPstate (NumberBoostStates, CurrentSoftwarePs, StdHeader); + LibAmdMsrRead ((PS_REG_BASE + NumberBoostStates), &LocalMsrRegister, StdHeader); + ((PSTATE_MSR *) &LocalMsrRegister)->PsEnable = 1; + LibAmdMsrWrite ((PS_REG_BASE + NumberBoostStates), &LocalMsrRegister, StdHeader); FamilySpecificServices->TransitionPstate (FamilySpecificServices, (UINT8) 0, (BOOLEAN) TRUE, StdHeader); } } else { @@ -304,29 +390,39 @@ F14PmPwrCheckCore ( // Step 1 // Transition to a valid Pstate if current Pstate has been disabled - if (CurrentPs < DisPsNum) { - FamilySpecificServices->TransitionPstate (FamilySpecificServices, DisPsNum, (BOOLEAN) TRUE, StdHeader); - CurrentPs = DisPsNum; + if (CurrentHardwarePs < DisHwPsNum) { + FamilySpecificServices->TransitionPstate (FamilySpecificServices, (HardwarePsMaxVal - NumberBoostStates), (BOOLEAN) TRUE, StdHeader); + CurrentSoftwarePs = HardwarePsMaxVal - NumberBoostStates; } + if (DisSwPsNum != 0) { // Step 2 // Move enabled Pstates up and disable the remainder - for (i = 0; (i + DisPsNum) <= PsMaxVal; ++i) { - F14PmPwrChkCopyPstate (i, (i + DisPsNum), StdHeader); + for (i = 0; (i + DisHwPsNum) <= HardwarePsMaxVal; ++i) { + F14PmPwrChkCopyPstate ((i + NumberBoostStates), (i + DisHwPsNum), StdHeader); } - // Step 3 // Transition to current COF/VID at shifted location - CurrentPs = (CurrentPs - DisPsNum); - FamilySpecificServices->TransitionPstate (FamilySpecificServices, CurrentPs, (BOOLEAN) TRUE, StdHeader); + CurrentSoftwarePs = (CurrentSoftwarePs - DisSwPsNum); + FamilySpecificServices->TransitionPstate (FamilySpecificServices, CurrentSoftwarePs, (BOOLEAN) TRUE, StdHeader); + } + } + + if (((PWRCHK_ERROR_DATA *) ErrorData)->AllowablePstateNumber == 0) { + // only software P0 should be enabled. + i = NumberBoostStates + 1; + } else { + if (DisSwPsNum == 0) { + // No software Pstate is disabed, set i = HardwarePsMaxVal + 1 to skip below 'while loop'. + i = HardwarePsMaxVal + 1; + } else { + // get the first software Pstate that should be disabled. + i = HardwarePsMaxVal - DisSwPsNum + 1; } - i = ((PWRCHK_ERROR_DATA *) ErrorData)->AllowablePstateNumber; - if (i == 0) { - i++; } - while (i <= PsMaxVal) { + while (i <= HardwarePsMaxVal) { FamilySpecificServices->DisablePstate (FamilySpecificServices, i, StdHeader); i++; } @@ -350,9 +446,9 @@ F14PmPwrChkCopyPstate ( IN AMD_CONFIG_PARAMS *StdHeader ) { - UINT64 MsrRegister; + UINT64 LocalMsrRegister; - LibAmdMsrRead ((UINT32) (PS_REG_BASE + Src), &MsrRegister, StdHeader); - LibAmdMsrWrite ((UINT32) (PS_REG_BASE + Dest), &MsrRegister, StdHeader); + LibAmdMsrRead ((UINT32) (PS_REG_BASE + Src), &LocalMsrRegister, StdHeader); + LibAmdMsrWrite ((UINT32) (PS_REG_BASE + Dest), &LocalMsrRegister, StdHeader); } diff --git a/src/vendorcode/amd/agesa/f14/Proc/CPU/Family/0x14/cpuF14PowerMgmt.h b/src/vendorcode/amd/agesa/f14/Proc/CPU/Family/0x14/cpuF14PowerMgmt.h index 72cf02f5c4..f0d8198ec1 100644 --- a/src/vendorcode/amd/agesa/f14/Proc/CPU/Family/0x14/cpuF14PowerMgmt.h +++ b/src/vendorcode/amd/agesa/f14/Proc/CPU/Family/0x14/cpuF14PowerMgmt.h @@ -7,7 +7,7 @@ * @xrefitem bom "File Content Label" "Release Content" * @e project: AGESA * @e sub-project: CPU/F14 - * @e \$Revision: 34897 $ @e \$Date: 2010-07-14 10:07:10 +0800 (Wed, 14 Jul 2010) $ + * @e \$Revision: 46836 $ @e \$Date: 2011-02-10 12:22:59 -0700 (Thu, 10 Feb 2011) $ * */ /* @@ -110,6 +110,20 @@ typedef struct { } PSTATE_MSR; +/* COFVID Control Register 0xC0010070 */ +#define MSR_COFVID_CTL 0xC0010070 + +/// COFVID Control MSR Register +typedef struct { + UINT64 CpuDid:4; ///< CPU core divisor identifier + UINT64 CpuDidMSD:5; ///< CPU core frequency identifier + UINT64 CpuVid:7; ///< CPU core VID + UINT64 PstateId:3; ///< P-state identifier + UINT64 IgnoreFidVidDid:1; ///< Ignore FID, VID, and DID + UINT64 :44; ///< Reserved +} COFVID_CTRL_MSR; + + /* COFVID Status Register 0xC0010071 */ #define MSR_COFVID_STS 0xC0010071 @@ -301,6 +315,36 @@ typedef struct { UINT32 :16; ///< Reserved } CLK_PWR_TIMING_CTRL3_REGISTER; +/* Local hardware thermal control register D18F3x138 */ +#define LHTC_REG 0x138 +#define LHTC_PCI_ADDR (MAKE_SBDFO (0, 0, 0x18, FUNC_3, LHTC_REG)) + +/// Local Hardware Thermal Control PCI Register +typedef struct { + UINT32 LHtcEn:1; ///< Local HTC Enable + UINT32 :7; ///< Reserved + UINT32 LHtcAct:2; ///< Local HTC Active State + UINT32 :2; ///< Reserved + UINT32 LHtcActSts:2; ///< Local HTC Active Status + UINT32 :2; ///< Reserved + UINT32 LHtcTmpLmt:7; ///< Local HTC temperature limit + UINT32 LHtcSlewSel:1; ///< Local HTC slew-controlled temp select + UINT32 LHtcHystLmt:4; ///< Local HTC hysteresis + UINT32 LHtcPstateLimit:3; ///< Local HTC P-state limit select + UINT32 LHtcLock:1; ///< HTC lock +} LHTC_REGISTER; + +/* Product Information Register D18F3x1FC */ +#define PRODUCT_INFO_REG 0x1FC +#define PRODUCT_INFO_PCI_ADDR (MAKE_SBDFO (0, 0, 0x18, FUNC_3, PRODUCT_INFO_REG)) + +/// Product Information PCI Register +typedef struct { + UINT32 :2; ///< Reserved + UINT32 LowPowerDefault:1; ///< Low Power Default + UINT32 :29; ///< Reserved +} PRODUCT_INFO_REGISTER; + /* C-state Control 1 Register D18F4x118 */ #define CSTATE_CTRL1_REG 0x118 @@ -336,6 +380,33 @@ typedef struct { } CSTATE_CTRL2_REGISTER; +/* C-state Monitor Control 3 Register D18F4x134 */ +#define CSTATE_MON_CTRL3_REG 0x134 +#define CSTATE_MON_CTRL3_PCI_ADDR (MAKE_SBDFO (0, 0, 0x18, FUNC_4, CSTATE_MON_CTRL3_REG)) + +/// C-state Monitor Control 3 Register +typedef struct { + UINT32 IntRatePkgC6MaxDepth:4; ///< Interrupt rate monitor PC6 maximum counter depth + UINT32 IntRatePkgC6Threshold:4; ///< Interrupt rate monitor PC6 threshold + UINT32 IntRatePkgC6BurstLen:3; ///< Interrupt rate monitor PC6 burst length + UINT32 IntRatePkgC6DecrRate:5; ///< Interrupt rate monitor PC6 decrement rate + UINT32 IntRateCC6MaxDepth:4; ///< Interrupt rate monitor CC6 maximum counter depth + UINT32 IntRateCC6Threshold:4; ///< Interrupt rate monitor CC6 threshold + UINT32 IntRateCC6BurstLen:3; ///< Interrupt rate monitor CC6 burst length + UINT32 IntRateCC6DecrRate:5; ///< Interrupt rate monitor CC6 decrement rate +} CSTATE_MON_CTRL3_REGISTER; + +/* LPMV Scalar 2 Register D18F4x14C */ +#define LPMV_SCALAR2_REG 0x14C +#define LPMV_SCALAR2_PCI_ADDR (MAKE_SBDFO (0, 0, 0x18, FUNC_4, LPMV_SCALAR2_REG)) + +/// LPMV Scalar 2 Register +typedef struct { + UINT32 :24; ///< Reserved + UINT32 ApmCstExtPol:2; ///< Number of boosted states + UINT32 :6; ///< Reserved +} LPMV_SCALAR2_REGISTER; + /* Core Performance Boost Control Register D18F4x15C */ #define CPB_CTRL_REG 0x15C #define CPB_CTRL_PCI_ADDR (MAKE_SBDFO (0, 0, 0x18, FUNC_4, CPB_CTRL_REG)) diff --git a/src/vendorcode/amd/agesa/f14/Proc/CPU/Family/0x14/cpuF14PowerMgmtSystemTables.c b/src/vendorcode/amd/agesa/f14/Proc/CPU/Family/0x14/cpuF14PowerMgmtSystemTables.c index 44e31d7e8c..b234541959 100644 --- a/src/vendorcode/amd/agesa/f14/Proc/CPU/Family/0x14/cpuF14PowerMgmtSystemTables.c +++ b/src/vendorcode/amd/agesa/f14/Proc/CPU/Family/0x14/cpuF14PowerMgmtSystemTables.c @@ -7,7 +7,7 @@ * @xrefitem bom "File Content Label" "Release Content" * @e project: AGESA * @e sub-project: CPU - * @e \$Revision: 37018 $ @e \$Date: 2010-08-28 05:46:16 +0800 (Sat, 28 Aug 2010) $ + * @e \$Revision: 45626 $ @e \$Date: 2011-01-19 09:58:02 -0700 (Wed, 19 Jan 2011) $ * */ /* @@ -55,6 +55,7 @@ #include "cpuF14SoftwareThermal.h" #include "cpuF14PowerPlane.h" #include "cpuF14PowerCheck.h" +#include "cpuF14LowPowerInit.h" #include "Filecode.h" #define FILECODE PROC_CPU_FAMILY_0X14_CPUF14POWERMGMTSYSTEMTABLES_FILECODE @@ -73,6 +74,14 @@ *---------------------------------------------------------------------------------------- */ +VOID +GetF14SysPmTable ( + IN CPU_SPECIFIC_SERVICES *FamilySpecificServices, + OUT CONST VOID **SysPmTblPtr, + OUT UINT8 *NumberOfElements, + IN AMD_CONFIG_PARAMS *StdHeader + ); + /*---------------------------------------------------------------------------------------- * E X P O R T E D F U N C T I O N S *---------------------------------------------------------------------------------------- @@ -91,6 +100,13 @@ CONST SYS_PM_TBL_STEP ROMDATA CpuF14SysPmTableArray[] = F14PmPwrPlaneInit // Function Pointer }, + // Step x - Optimizations for lower power + // Execute both cold & warm + { + 0, // ExeFlags + F14OptimizeForLowPowerInit // Function Pointer + }, + // Step 2 - Current Delivery Check // Execute both cold & warm { @@ -103,7 +119,7 @@ CONST SYS_PM_TBL_STEP ROMDATA CpuF14SysPmTableArray[] = { 0, // ExeFlags F14PmThermalInit // Function Pointer - }, + } }; diff --git a/src/vendorcode/amd/agesa/f14/Proc/CPU/Family/0x14/cpuF14PowerPlane.c b/src/vendorcode/amd/agesa/f14/Proc/CPU/Family/0x14/cpuF14PowerPlane.c index 6464954051..048116020f 100644 --- a/src/vendorcode/amd/agesa/f14/Proc/CPU/Family/0x14/cpuF14PowerPlane.c +++ b/src/vendorcode/amd/agesa/f14/Proc/CPU/Family/0x14/cpuF14PowerPlane.c @@ -57,6 +57,7 @@ #include "cpuFamilyTranslation.h" #include "cpuServices.h" #include "cpuF14PowerMgmt.h" +#include "cpuF14PowerPlane.h" #include "OptionFamily14hEarlySample.h" #include "NbSmuLib.h" #include "GnbRegistersON.h" @@ -129,7 +130,7 @@ F14PmPwrPlaneInit ( ) { UINT32 SystemSlewRate; - UINT32 PciRegister; + UINT32 PciReg; UINT32 WaitTime; UINT32 VSRampSlamTime; PCI_ADDR PciAddress; @@ -166,9 +167,9 @@ F14PmPwrPlaneInit ( // Lastly, program D18F3xD8[VSRampSlamTime] with the appropriate encoded value. PciAddress.AddressValue = CPTC1_PCI_ADDR; - LibAmdPciRead (AccessWidth32, PciAddress, &PciRegister, StdHeader); - ((CLK_PWR_TIMING_CTRL1_REGISTER *) &PciRegister)->VSRampSlamTime = VSRampSlamTime; - LibAmdPciWrite (AccessWidth32, PciAddress, &PciRegister, StdHeader); + LibAmdPciRead (AccessWidth32, PciAddress, &PciReg, StdHeader); + ((CLK_PWR_TIMING_CTRL1_REGISTER *) &PciReg)->VSRampSlamTime = VSRampSlamTime; + LibAmdPciWrite (AccessWidth32, PciAddress, &PciReg, StdHeader); // Step 2 - Configure D18F3xA0[PsiVidEn & PsiVid] and D18F3x128[NbPsiVidEn & NbPsiVid]. F14PmVrmLowPowerModeEnable (FamilySpecificServices, CpuEarlyParams, StdHeader); @@ -180,11 +181,11 @@ F14PmPwrPlaneInit ( F14EarlySampleCoreSupport.F14PowerPlaneInitHook (&FCRxFE00_6000, StdHeader); PciAddress.AddressValue = CPTC2_PCI_ADDR; - LibAmdPciRead (AccessWidth32, PciAddress, &PciRegister, StdHeader); - ((CLK_PWR_TIMING_CTRL2_REGISTER *) &PciRegister)->NbPs0Vid = FCRxFE00_6000.Field.NbPs0Vid - 1; - LibAmdPciWrite (AccessWidth32, PciAddress, &PciRegister, StdHeader); - ((CLK_PWR_TIMING_CTRL2_REGISTER *) &PciRegister)->NbPs0Vid = FCRxFE00_6000.Field.NbPs0Vid; - LibAmdPciWrite (AccessWidth32, PciAddress, &PciRegister, StdHeader); + LibAmdPciRead (AccessWidth32, PciAddress, &PciReg, StdHeader); + ((CLK_PWR_TIMING_CTRL2_REGISTER *) &PciReg)->NbPs0Vid = FCRxFE00_6000.Field.NbPs0Vid - 1; + LibAmdPciWrite (AccessWidth32, PciAddress, &PciReg, StdHeader); + ((CLK_PWR_TIMING_CTRL2_REGISTER *) &PciReg)->NbPs0Vid = FCRxFE00_6000.Field.NbPs0Vid; + LibAmdPciWrite (AccessWidth32, PciAddress, &PciReg, StdHeader); } /*---------------------------------------------------------------------------------------*/ @@ -211,7 +212,7 @@ F14PmVrmLowPowerModeEnable ( UINT32 PstateCurrent; UINT32 NextPstateCurrent; UINT32 NextPstateCurrentRaw; - UINT32 PciRegister; + UINT32 PciReg; UINT32 PreviousVid; UINT32 CurrentVid; UINT64 PstateMsr; @@ -249,24 +250,24 @@ F14PmVrmLowPowerModeEnable ( } } PciAddress.AddressValue = PW_CTL_MISC_PCI_ADDR; - LibAmdPciRead (AccessWidth32, PciAddress, &PciRegister, StdHeader); + LibAmdPciRead (AccessWidth32, PciAddress, &PciReg, StdHeader); if (IsPsiEnabled) { - ((POWER_CTRL_MISC_REGISTER *) &PciRegister)->PsiVid = CurrentVid; - ((POWER_CTRL_MISC_REGISTER *) &PciRegister)->PsiVidEn = 1; + ((POWER_CTRL_MISC_REGISTER *) &PciReg)->PsiVid = CurrentVid; + ((POWER_CTRL_MISC_REGISTER *) &PciReg)->PsiVidEn = 1; } else { - ((POWER_CTRL_MISC_REGISTER *) &PciRegister)->PsiVidEn = 0; + ((POWER_CTRL_MISC_REGISTER *) &PciReg)->PsiVidEn = 0; } - LibAmdPciWrite (AccessWidth32, PciAddress, &PciRegister, StdHeader); + LibAmdPciWrite (AccessWidth32, PciAddress, &PciReg, StdHeader); // Set up NBPSI_L for VDDNB PciAddress.AddressValue = CPTC3_PCI_ADDR; - LibAmdPciRead (AccessWidth32, PciAddress, &PciRegister, StdHeader); + LibAmdPciRead (AccessWidth32, PciAddress, &PciReg, StdHeader); if (CpuEarlyParams->PlatformConfig.VrmProperties[NbVrm].LowPowerThreshold != 0) { - ((CLK_PWR_TIMING_CTRL3_REGISTER *) &PciRegister)->NbPsiVid = 0; - ((CLK_PWR_TIMING_CTRL3_REGISTER *) &PciRegister)->NbPsiVidEn = 1; + ((CLK_PWR_TIMING_CTRL3_REGISTER *) &PciReg)->NbPsiVid = 0; + ((CLK_PWR_TIMING_CTRL3_REGISTER *) &PciReg)->NbPsiVidEn = 1; } else { - ((CLK_PWR_TIMING_CTRL3_REGISTER *) &PciRegister)->NbPsiVidEn = 0; + ((CLK_PWR_TIMING_CTRL3_REGISTER *) &PciReg)->NbPsiVidEn = 0; } - LibAmdPciWrite (AccessWidth32, PciAddress, &PciRegister, StdHeader); + LibAmdPciWrite (AccessWidth32, PciAddress, &PciReg, StdHeader); } diff --git a/src/vendorcode/amd/agesa/f14/Proc/CPU/Family/0x14/cpuF14Pstate.c b/src/vendorcode/amd/agesa/f14/Proc/CPU/Family/0x14/cpuF14Pstate.c index d37f3fd32a..64bcf95697 100644 --- a/src/vendorcode/amd/agesa/f14/Proc/CPU/Family/0x14/cpuF14Pstate.c +++ b/src/vendorcode/amd/agesa/f14/Proc/CPU/Family/0x14/cpuF14Pstate.c @@ -9,7 +9,7 @@ * @xrefitem bom "File Content Label" "Release Content" * @e project: AGESA * @e sub-project: CPU/F14 - * @e \$Revision: 37010 $ @e \$Date: 2010-08-28 03:10:12 +0800 (Sat, 28 Aug 2010) $ + * @e \$Revision: 44325 $ @e \$Date: 2010-12-22 03:29:53 -0700 (Wed, 22 Dec 2010) $ * */ /* @@ -75,6 +75,49 @@ *---------------------------------------------------------------------------------------- */ +AGESA_STATUS +F14GetPstateTransLatency ( + IN PSTATE_CPU_FAMILY_SERVICES *PstateCpuServices, + IN PSTATE_LEVELING *PStateLevelingBufferStructPtr, + IN PCI_ADDR *PciAddress, + OUT UINT32 *TransitionLatency, + IN AMD_CONFIG_PARAMS *StdHeader + ); + +AGESA_STATUS +F14GetPstateFrequency ( + IN PSTATE_CPU_FAMILY_SERVICES *PstateCpuServices, + IN UINT8 StateNumber, + OUT UINT32 *FrequencyInMHz, + IN AMD_CONFIG_PARAMS *StdHeader + ); + +AGESA_STATUS +F14GetPstatePower ( + IN PSTATE_CPU_FAMILY_SERVICES *PstateCpuServices, + IN UINT8 StateNumber, + OUT UINT32 *PowerInMw, + IN AMD_CONFIG_PARAMS *StdHeader + ); + +AGESA_STATUS +F14GetPstateMaxState ( + IN PSTATE_CPU_FAMILY_SERVICES *PstateCpuServices, + OUT UINT32 *MaxPStateNumber, + IN AMD_CONFIG_PARAMS *StdHeader + ); + +AGESA_STATUS +F14GetPstateRegisterInfo ( + IN PSTATE_CPU_FAMILY_SERVICES *PstateCpuServices, + IN UINT32 PState, + OUT BOOLEAN *PStateEnabled, + IN OUT UINT32 *IddVal, + IN OUT UINT32 *IddDiv, + OUT UINT32 *SwPstateNumber, + IN AMD_CONFIG_PARAMS *StdHeader + ); + /*---------------------------------------------------------------------------------------- * E X P O R T E D F U N C T I O N S *---------------------------------------------------------------------------------------- @@ -154,8 +197,8 @@ F14GetPstateFrequency ( UINT32 CpuDidLSD; UINT32 CpuDidMSD; UINT32 CoreClkDivisor; - UINT32 PciRegister; - UINT64 MsrRegister; + UINT32 PciReg; + UINT64 MsrReg; BOOLEAN FrequencyCalculated; BOOLEAN ClockDivisorCalculated; PCI_ADDR PciAddress; @@ -164,11 +207,11 @@ F14GetPstateFrequency ( ASSERT (StateNumber < NM_PS_REG); - LibAmdMsrRead (PS_REG_BASE + (UINT32) StateNumber, &MsrRegister, StdHeader); - ASSERT (((PSTATE_MSR *) &MsrRegister)->PsEnable == 1); + LibAmdMsrRead (PS_REG_BASE + (UINT32) StateNumber, &MsrReg, StdHeader); + ASSERT (((PSTATE_MSR *) &MsrReg)->PsEnable == 1); - CpuDidLSD = (UINT32) (((PSTATE_MSR *) &MsrRegister)->CpuDidLSD); - CpuDidMSD = (UINT32) (((PSTATE_MSR *) &MsrRegister)->CpuDidMSD); + CpuDidLSD = (UINT32) (((PSTATE_MSR *) &MsrReg)->CpuDidLSD); + CpuDidMSD = (UINT32) (((PSTATE_MSR *) &MsrReg)->CpuDidMSD); FrequencyCalculated = FALSE; ClockDivisorCalculated = FALSE; @@ -194,10 +237,10 @@ F14GetPstateFrequency ( if (!FrequencyCalculated) { // Get D18F3xD4[MainPllOpFreqId] frequency PciAddress.AddressValue = CPTC0_PCI_ADDR; - LibAmdPciRead (AccessWidth32, PciAddress, &PciRegister, StdHeader); + LibAmdPciRead (AccessWidth32, PciAddress, &PciReg, StdHeader); - if (((CLK_PWR_TIMING_CTRL_REGISTER *) &PciRegister)->MainPllOpFreqIdEn == 1) { - MainPllFid = ((CLK_PWR_TIMING_CTRL_REGISTER *) &PciRegister)->MainPllOpFreqId; + if (((CLK_PWR_TIMING_CTRL_REGISTER *) &PciReg)->MainPllOpFreqIdEn == 1) { + MainPllFid = ((CLK_PWR_TIMING_CTRL_REGISTER *) &PciReg)->MainPllOpFreqId; } else { MainPllFid = 0; } @@ -234,14 +277,14 @@ F14GetPstatePower ( UINT32 IddDiv; UINT32 V_x10000; UINT32 Power; - UINT64 MsrRegister; + UINT64 MsrReg; ASSERT (StateNumber < NM_PS_REG); - LibAmdMsrRead (PS_REG_BASE + (UINT32) StateNumber, &MsrRegister, StdHeader); - ASSERT (((PSTATE_MSR *) &MsrRegister)->PsEnable == 1); - CpuVid = (UINT32) (((PSTATE_MSR *) &MsrRegister)->CpuVid); - IddValue = (UINT32) (((PSTATE_MSR *) &MsrRegister)->IddValue); - IddDiv = (UINT32) (((PSTATE_MSR *) &MsrRegister)->IddDiv); + LibAmdMsrRead (PS_REG_BASE + (UINT32) StateNumber, &MsrReg, StdHeader); + ASSERT (((PSTATE_MSR *) &MsrReg)->PsEnable == 1); + CpuVid = (UINT32) (((PSTATE_MSR *) &MsrReg)->CpuVid); + IddValue = (UINT32) (((PSTATE_MSR *) &MsrReg)->IddValue); + IddDiv = (UINT32) (((PSTATE_MSR *) &MsrReg)->IddDiv); if (CpuVid >= 0x7C) { V_x10000 = 0; @@ -289,13 +332,19 @@ F14GetPstateMaxState ( ) { UINT64 MsrValue; + UINT32 PciReg; + PCI_ADDR PciAddress; + + // For F14 CPU, skip boosted p-state. The boosted p-state number = D18F4x15C[NumBoostStates]. + PciAddress.AddressValue = CPB_CTRL_PCI_ADDR; + LibAmdPciRead (AccessWidth32, PciAddress, &PciReg, StdHeader); // D18F4x15C // // Read PstateMaxVal [6:4] from MSR C001_0061 // So, we will know the max pstate state in this socket. // LibAmdMsrRead (MSR_PSTATE_CURRENT_LIMIT, &MsrValue, StdHeader); - *MaxPStateNumber = (UINT32) (((PSTATE_CURLIM_MSR *) &MsrValue)->PstateMaxVal); + *MaxPStateNumber = (UINT32) (((PSTATE_CURLIM_MSR *) &MsrValue)->PstateMaxVal) + (UINT32) (((CPB_CTRL_REGISTER *) &PciReg)->NumBoostStates); return (AGESA_SUCCESS); } @@ -325,25 +374,44 @@ F14GetPstateRegisterInfo ( IN AMD_CONFIG_PARAMS *StdHeader ) { - UINT64 MsrRegister; + UINT64 LocalMsrReg; + UINT32 LocalPciReg; + PCI_ADDR PciAddress; + CPU_LOGICAL_ID CpuFamilyRevision; ASSERT (PState < NM_PS_REG); // Read PSTATE MSRs - LibAmdMsrRead (PS_REG_BASE + (UINT32) PState, &MsrRegister, StdHeader); + LibAmdMsrRead (PS_REG_BASE + (UINT32) PState, &LocalMsrReg, StdHeader); + + *SwPstateNumber = PState; - if (((PSTATE_MSR *) &MsrRegister)->PsEnable == 1) { + if (((PSTATE_MSR *) &LocalMsrReg)->PsEnable == 1) { // PState enable = bit 63 *PStateEnabled = TRUE; + // For F14 CPU, skip boosted p-state. The boosted p-state number = D18F4x15C[NumBoostStates]. + GetLogicalIdOfCurrentCore (&CpuFamilyRevision, StdHeader); + if ((CpuFamilyRevision.Revision & (AMD_F14_ON_Ax | AMD_F14_ON_Bx)) == 0) { + // ON_Ax & ON_Bx don't have boosted p-state function + PciAddress.AddressValue = CPB_CTRL_PCI_ADDR; + LibAmdPciRead (AccessWidth32, PciAddress, &LocalPciReg, StdHeader); // D18F4x15C + // + // Check input pstate belongs to Boosted-Pstate, if yes, return *PStateEnabled = FALSE. + // + if (PState < ((CPB_CTRL_REGISTER *) &LocalPciReg)->NumBoostStates) { + *PStateEnabled = FALSE; + } else { + *SwPstateNumber = PState - ((CPB_CTRL_REGISTER *) &LocalPciReg)->NumBoostStates; + } + } } else { *PStateEnabled = FALSE; } - *SwPstateNumber = PState; // Bits 39:32 (high 32 bits [7:0]) - *IddVal = (UINT32) ((PSTATE_MSR *) &MsrRegister)->IddValue; + *IddVal = (UINT32) ((PSTATE_MSR *) &LocalMsrReg)->IddValue; // Bits 41:40 (high 32 bits [9:8]) - *IddDiv = (UINT32) ((PSTATE_MSR *) &MsrRegister)->IddDiv; + *IddDiv = (UINT32) ((PSTATE_MSR *) &LocalMsrReg)->IddDiv; return (AGESA_SUCCESS); } diff --git a/src/vendorcode/amd/agesa/f14/Proc/CPU/Family/0x14/cpuF14SoftwareThermal.c b/src/vendorcode/amd/agesa/f14/Proc/CPU/Family/0x14/cpuF14SoftwareThermal.c index 249a3bcc80..6eec83f63d 100644 --- a/src/vendorcode/amd/agesa/f14/Proc/CPU/Family/0x14/cpuF14SoftwareThermal.c +++ b/src/vendorcode/amd/agesa/f14/Proc/CPU/Family/0x14/cpuF14SoftwareThermal.c @@ -9,7 +9,7 @@ * @xrefitem bom "File Content Label" "Release Content" * @e project: AGESA * @e sub-project: CPU/F14 - * @e \$Revision: 34897 $ @e \$Date: 2010-07-14 10:07:10 +0800 (Wed, 14 Jul 2010) $ + * @e \$Revision: 46836 $ @e \$Date: 2011-02-10 12:22:59 -0700 (Thu, 10 Feb 2011) $ * */ /* @@ -50,10 +50,10 @@ */ #include "AGESA.h" #include "amdlib.h" -#include "cpuCacheInit.h" #include "cpuRegisters.h" #include "cpuFamilyTranslation.h" #include "cpuF14PowerMgmt.h" +#include "cpuF14SoftwareThermal.h" #include "Filecode.h" #define FILECODE PROC_CPU_FAMILY_0X14_CPUF14SOFTWARETHERMAL_FILECODE @@ -95,18 +95,33 @@ F14PmThermalInit ( IN AMD_CONFIG_PARAMS *StdHeader ) { - UINT32 PciRegister; + UINT32 NbCaps; + UINT32 LocalPciRegister; PCI_ADDR PciAddress; + CPU_LOGICAL_ID CpuFamilyRevision; PciAddress.AddressValue = NB_CAPS_PCI_ADDR; - LibAmdPciRead (AccessWidth32, PciAddress, &PciRegister, StdHeader); - if (((NB_CAPS_REGISTER *) &PciRegister)->HtcCapable == 1) { + LibAmdPciRead (AccessWidth32, PciAddress, &NbCaps, StdHeader); + if (((NB_CAPS_REGISTER *) &NbCaps)->HtcCapable == 1) { PciAddress.AddressValue = HTC_PCI_ADDR; - LibAmdPciRead (AccessWidth32, PciAddress, &PciRegister, StdHeader); - if (((HTC_REGISTER *) &PciRegister)->HtcTmpLmt != 0) { + LibAmdPciRead (AccessWidth32, PciAddress, &LocalPciRegister, StdHeader); + if (((HTC_REGISTER *) &LocalPciRegister)->HtcTmpLmt != 0) { // Enable HTC - ((HTC_REGISTER *) &PciRegister)->HtcEn = 1; - LibAmdPciWrite (AccessWidth32, PciAddress, &PciRegister, StdHeader); + ((HTC_REGISTER *) &LocalPciRegister)->HtcEn = 1; + LibAmdPciWrite (AccessWidth32, PciAddress, &LocalPciRegister, StdHeader); } } + + GetLogicalIdOfCurrentCore (&CpuFamilyRevision, StdHeader); + if ((CpuFamilyRevision.Revision & AMD_F14_ON_Cx) != 0) { + PciAddress.AddressValue = LHTC_PCI_ADDR; + LibAmdPciRead (AccessWidth32, PciAddress, &LocalPciRegister, StdHeader); + if (((NB_CAPS_REGISTER *) &NbCaps)->LHtcCapable == 1) { + if (((LHTC_REGISTER *) &LocalPciRegister)->LHtcTmpLmt != 0) { + // Enable local HTC + ((LHTC_REGISTER *) &LocalPciRegister)->LHtcEn = 1; + } + } + LibAmdPciWrite (AccessWidth32, PciAddress, &LocalPciRegister, StdHeader); + } } diff --git a/src/vendorcode/amd/agesa/f14/Proc/CPU/Family/0x14/cpuF14Utilities.c b/src/vendorcode/amd/agesa/f14/Proc/CPU/Family/0x14/cpuF14Utilities.c index f6a13e59fe..1ddcb15c96 100644 --- a/src/vendorcode/amd/agesa/f14/Proc/CPU/Family/0x14/cpuF14Utilities.c +++ b/src/vendorcode/amd/agesa/f14/Proc/CPU/Family/0x14/cpuF14Utilities.c @@ -84,6 +84,38 @@ F14ConvertEnabledBitsIntoCount ( IN UINT8 EnabledCores ); +BOOLEAN +F14GetNbPstateInfo ( + IN CPU_SPECIFIC_SERVICES *FamilySpecificServices, + IN PLATFORM_CONFIGURATION *PlatformConfig, + IN PCI_ADDR *PciAddress, + IN UINT32 NbPstate, + OUT UINT32 *FreqNumeratorInMHz, + OUT UINT32 *FreqDivisor, + OUT UINT32 *VoltageInuV, + IN AMD_CONFIG_PARAMS *StdHeader + ); + +BOOLEAN +F14IsNbPstateEnabled ( + IN CPU_SPECIFIC_SERVICES *FamilySpecificServices, + IN PLATFORM_CONFIGURATION *PlatformConfig, + IN AMD_CONFIG_PARAMS *StdHeader + ); + +BOOLEAN +F14GetProcIddMax ( + IN CPU_SPECIFIC_SERVICES *FamilySpecificServices, + IN UINT8 Pstate, + OUT UINT32 *ProcIddMax, + IN AMD_CONFIG_PARAMS *StdHeader + ); + +UINT8 +F14GetNumberOfCoresForBrandstring ( + IN CPU_SPECIFIC_SERVICES *FamilySpecificServices, + IN AMD_CONFIG_PARAMS *StdHeader + ); /*---------------------------------------------------------------------------------------- * E X P O R T E D F U N C T I O N S @@ -132,12 +164,12 @@ F14DisablePstate ( IN AMD_CONFIG_PARAMS *StdHeader ) { - UINT64 MsrRegister; + UINT64 MsrReg; ASSERT (StateNumber < NM_PS_REG); - LibAmdMsrRead (PS_REG_BASE + (UINT32) StateNumber, &MsrRegister, StdHeader); - ((PSTATE_MSR *) &MsrRegister)->PsEnable = 0; - LibAmdMsrWrite (PS_REG_BASE + (UINT32) StateNumber, &MsrRegister, StdHeader); + LibAmdMsrRead (PS_REG_BASE + (UINT32) StateNumber, &MsrReg, StdHeader); + ((PSTATE_MSR *) &MsrReg)->PsEnable = 0; + LibAmdMsrWrite (PS_REG_BASE + (UINT32) StateNumber, &MsrReg, StdHeader); return (AGESA_SUCCESS); } @@ -162,18 +194,18 @@ F14TransitionPstate ( IN AMD_CONFIG_PARAMS *StdHeader ) { - UINT64 MsrRegister; + UINT64 MsrReg; ASSERT (StateNumber < NM_PS_REG); - LibAmdMsrRead (PS_REG_BASE + (UINT32) StateNumber, &MsrRegister, StdHeader); - ASSERT (((PSTATE_MSR *) &MsrRegister)->PsEnable == 1); - LibAmdMsrRead (MSR_PSTATE_CTL, &MsrRegister, StdHeader); - ((PSTATE_CTRL_MSR *) &MsrRegister)->PstateCmd = (UINT64) StateNumber; - LibAmdMsrWrite (MSR_PSTATE_CTL, &MsrRegister, StdHeader); + LibAmdMsrRead (PS_REG_BASE + (UINT32) StateNumber, &MsrReg, StdHeader); + ASSERT (((PSTATE_MSR *) &MsrReg)->PsEnable == 1); + LibAmdMsrRead (MSR_PSTATE_CTL, &MsrReg, StdHeader); + ((PSTATE_CTRL_MSR *) &MsrReg)->PstateCmd = (UINT64) StateNumber; + LibAmdMsrWrite (MSR_PSTATE_CTL, &MsrReg, StdHeader); if (WaitForTransition) { do { - LibAmdMsrRead (MSR_PSTATE_STS, &MsrRegister, StdHeader); - } while (((PSTATE_STS_MSR *) &MsrRegister)->CurPstate != (UINT64) StateNumber); + LibAmdMsrRead (MSR_PSTATE_STS, &MsrReg, StdHeader); + } while (((PSTATE_STS_MSR *) &MsrReg)->CurPstate != (UINT64) StateNumber); } return (AGESA_SUCCESS); } @@ -198,15 +230,15 @@ F14GetTscRate ( IN AMD_CONFIG_PARAMS *StdHeader ) { - UINT64 MsrRegister; + UINT64 MsrReg; PSTATE_CPU_FAMILY_SERVICES *FamilyServices; FamilyServices = NULL; - GetFeatureServicesOfCurrentCore (&PstateFamilyServiceTable, &FamilyServices, StdHeader); + GetFeatureServicesOfCurrentCore (&PstateFamilyServiceTable, (const VOID **)&FamilyServices, StdHeader); ASSERT (FamilyServices != NULL); - LibAmdMsrRead (0xC0010015, &MsrRegister, StdHeader); - if ((MsrRegister & 0x01000000) != 0) { + LibAmdMsrRead (0xC0010015, &MsrReg, StdHeader); + if ((MsrReg & 0x01000000) != 0) { return (FamilyServices->GetPstateFrequency (FamilyServices, 0, FrequencyInMHz, StdHeader)); } else { return (FamilySpecificServices->GetCurrentNbFrequency (FamilySpecificServices, FrequencyInMHz, StdHeader)); @@ -232,15 +264,15 @@ F14GetCurrentNbFrequency ( IN AMD_CONFIG_PARAMS *StdHeader ) { - UINT32 PciRegister; + UINT32 PciReg; UINT32 MainPllFid; PCI_ADDR PciAddress; PciAddress.AddressValue = CPTC0_PCI_ADDR; - LibAmdPciRead (AccessWidth32, PciAddress, &PciRegister, StdHeader); + LibAmdPciRead (AccessWidth32, PciAddress, &PciReg, StdHeader); - if (((CLK_PWR_TIMING_CTRL_REGISTER *) &PciRegister)->MainPllOpFreqIdEn == 1) { - MainPllFid = ((CLK_PWR_TIMING_CTRL_REGISTER *) &PciRegister)->MainPllOpFreqId; + if (((CLK_PWR_TIMING_CTRL_REGISTER *) &PciReg)->MainPllOpFreqIdEn == 1) { + MainPllFid = ((CLK_PWR_TIMING_CTRL_REGISTER *) &PciReg)->MainPllOpFreqId; } else { MainPllFid = 0; } @@ -283,7 +315,7 @@ F14GetNbPstateInfo ( ) { UINT32 NbVid; - UINT32 PciRegister; + UINT32 PciReg; UINT32 MainPllFreq; BOOLEAN PstateIsValid; @@ -294,15 +326,15 @@ F14GetNbPstateInfo ( if (NbPstate == 0) { PciAddress->Address.Function = FUNC_3; PciAddress->Address.Register = CPTC2_REG; - LibAmdPciRead (AccessWidth32, *PciAddress, &PciRegister, StdHeader); - *FreqDivisor = ((CLK_PWR_TIMING_CTRL2_REGISTER *) &PciRegister)->NbPs0NclkDiv; - NbVid = ((CLK_PWR_TIMING_CTRL2_REGISTER *) &PciRegister)->NbPs0Vid; + LibAmdPciRead (AccessWidth32, *PciAddress, &PciReg, StdHeader); + *FreqDivisor = ((CLK_PWR_TIMING_CTRL2_REGISTER *) &PciReg)->NbPs0NclkDiv; + NbVid = ((CLK_PWR_TIMING_CTRL2_REGISTER *) &PciReg)->NbPs0Vid; } else { PciAddress->Address.Function = FUNC_6; PciAddress->Address.Register = NB_PSTATE_CFG_LOW_REG; - LibAmdPciRead (AccessWidth32, *PciAddress, &PciRegister, StdHeader); - *FreqDivisor = ((NB_PSTATE_CFG_LOW_REGISTER *) &PciRegister)->NbPs1NclkDiv; - NbVid = ((NB_PSTATE_CFG_LOW_REGISTER *) &PciRegister)->NbPs1Vid; + LibAmdPciRead (AccessWidth32, *PciAddress, &PciReg, StdHeader); + *FreqDivisor = ((NB_PSTATE_CFG_LOW_REGISTER *) &PciReg)->NbPs1NclkDiv; + NbVid = ((NB_PSTATE_CFG_LOW_REGISTER *) &PciReg)->NbPs1Vid; } *VoltageInuV = (1550000 - (12500 * NbVid)); PstateIsValid = TRUE; @@ -330,12 +362,12 @@ F14IsNbPstateEnabled ( IN AMD_CONFIG_PARAMS *StdHeader ) { - UINT32 PciRegister; + UINT32 PciReg; PCI_ADDR PciAddress; PciAddress.AddressValue = NB_PSTATE_CFG_LOW_PCI_ADDR; - LibAmdPciRead (AccessWidth32, PciAddress, &PciRegister, StdHeader); - return ((BOOLEAN) (((NB_PSTATE_CFG_LOW_REGISTER *) &PciRegister)->NbPsCap == 1)); + LibAmdPciRead (AccessWidth32, PciAddress, &PciReg, StdHeader); + return ((BOOLEAN) (((NB_PSTATE_CFG_LOW_REGISTER *) &PciReg)->NbPsCap == 1)); } /*---------------------------------------------------------------------------------------*/ @@ -391,7 +423,7 @@ F14LaunchApCore ( ) { UINT32 NodeRelativeCoreNum; - UINT32 PciRegister; + UINT32 PciReg; PCI_ADDR PciAddress; BOOLEAN LaunchFlag; @@ -403,10 +435,10 @@ F14LaunchApCore ( switch (NodeRelativeCoreNum) { case 1: PciAddress.Address.Register = HT_TRANS_CTRL; - LibAmdPciRead (AccessWidth32, PciAddress, &PciRegister, StdHeader); - if ((PciRegister & HT_TRANS_CTRL_CPU1_EN) == 0) { - PciRegister |= HT_TRANS_CTRL_CPU1_EN; - LibAmdPciWrite (AccessWidth32, PciAddress, &PciRegister, StdHeader); + LibAmdPciRead (AccessWidth32, PciAddress, &PciReg, StdHeader); + if ((PciReg & HT_TRANS_CTRL_CPU1_EN) == 0) { + PciReg |= HT_TRANS_CTRL_CPU1_EN; + LibAmdPciWrite (AccessWidth32, PciAddress, &PciReg, StdHeader); LaunchFlag = TRUE; } else { LaunchFlag = FALSE; @@ -471,7 +503,7 @@ F14GetProcIddMax ( { UINT32 IddDiv; UINT32 CmpCap; - UINT32 PciRegister; + UINT32 PciReg; UINT32 MsrAddress; UINT64 PstateMsr; BOOLEAN IsPstateEnabled; @@ -486,8 +518,8 @@ F14GetProcIddMax ( LibAmdMsrRead (MsrAddress, &PstateMsr, StdHeader); if (((PSTATE_MSR *) &PstateMsr)->PsEnable == 1) { PciAddress.AddressValue = NB_CAPS_PCI_ADDR; - LibAmdPciRead (AccessWidth32, PciAddress, &PciRegister, StdHeader); // F3xE8 - CmpCap = (UINT32) (((NB_CAPS_REGISTER *) &PciRegister)->CmpCap); + LibAmdPciRead (AccessWidth32, PciAddress, &PciReg, StdHeader); // F3xE8 + CmpCap = (UINT32) (((NB_CAPS_REGISTER *) &PciReg)->CmpCap); CmpCap++; switch (((PSTATE_MSR *) &PstateMsr)->IddDiv) { diff --git a/src/vendorcode/amd/agesa/f14/Proc/CPU/Family/0x14/cpuF14WheaInitDataTables.c b/src/vendorcode/amd/agesa/f14/Proc/CPU/Family/0x14/cpuF14WheaInitDataTables.c index 50c773516a..8fe1080176 100644 --- a/src/vendorcode/amd/agesa/f14/Proc/CPU/Family/0x14/cpuF14WheaInitDataTables.c +++ b/src/vendorcode/amd/agesa/f14/Proc/CPU/Family/0x14/cpuF14WheaInitDataTables.c @@ -67,6 +67,14 @@ *---------------------------------------------------------------------------------------- */ +VOID +GetF14WheaInitData ( + IN CPU_SPECIFIC_SERVICES *FamilySpecificServices, + OUT CONST VOID **F14WheaInitDataPtr, + OUT UINT8 *NumberOfElements, + IN AMD_CONFIG_PARAMS *StdHeader + ); + /*---------------------------------------------------------------------------------------- * E X P O R T E D F U N C T I O N S *---------------------------------------------------------------------------------------- diff --git a/src/vendorcode/amd/agesa/f14/Proc/CPU/Family/cpuFamRegisters.h b/src/vendorcode/amd/agesa/f14/Proc/CPU/Family/cpuFamRegisters.h index bfbbf9b770..677cd79a20 100644 --- a/src/vendorcode/amd/agesa/f14/Proc/CPU/Family/cpuFamRegisters.h +++ b/src/vendorcode/amd/agesa/f14/Proc/CPU/Family/cpuFamRegisters.h @@ -70,37 +70,37 @@ // CPU_LOGICAL_ID.Family equates // Family 10h equates -#define AMD_FAMILY_10_RB 0x0000000000000001 -#define AMD_FAMILY_10_BL 0x0000000000000002 -#define AMD_FAMILY_10_DA 0x0000000000000004 -#define AMD_FAMILY_10_HY 0x0000000000000008 -#define AMD_FAMILY_10_PH 0x0000000000000010 +#define AMD_FAMILY_10_RB 0x0000000000000001ull +#define AMD_FAMILY_10_BL 0x0000000000000002ull +#define AMD_FAMILY_10_DA 0x0000000000000004ull +#define AMD_FAMILY_10_HY 0x0000000000000008ull +#define AMD_FAMILY_10_PH 0x0000000000000010ull #define AMD_FAMILY_10_C32 AMD_FAMILY_10_HY #define AMD_FAMILY_10 (AMD_FAMILY_10_RB | AMD_FAMILY_10_BL | AMD_FAMILY_10_DA | AMD_FAMILY_10_HY | AMD_FAMILY_10_PH) #define AMD_FAMILY_GH (AMD_FAMILY_10) // Family 12h equates -#define AMD_FAMILY_12_LN 0x0000000000000020 +#define AMD_FAMILY_12_LN 0x0000000000000020ull #define AMD_FAMILY_12 (AMD_FAMILY_12_LN) #define AMD_FAMILY_LN (AMD_FAMILY_12_LN) // Family 14h equates -#define AMD_FAMILY_14_ON 0x0000000000000040 +#define AMD_FAMILY_14_ON 0x0000000000000040ull #define AMD_FAMILY_14 (AMD_FAMILY_14_ON) #define AMD_FAMILY_ON (AMD_FAMILY_14_ON) // Family 15h equates -#define AMD_FAMILY_15_OR 0x0000000000000080 +#define AMD_FAMILY_15_OR 0x0000000000000100ull #define AMD_FAMILY_15 (AMD_FAMILY_15_OR) #define AMD_FAMILY_OR (AMD_FAMILY_15_OR) // Family 16h equates -#define AMD_FAMILY_16 0x0000000000000100 -#define AMD_FAMILY_WF (AMD_FAMILY_16) +#define AMD_FAMILY_16 0x0000000000000800ull +#define AMD_FAMILY_WF (AMD_FAMILY_16) // Family Unknown -#define AMD_FAMILY_UNKNOWN 0x8000000000000000 +#define AMD_FAMILY_UNKNOWN 0x8000000000000000ull // Family Group equates #define AMD_FAMILY_GE_12 (AMD_FAMILY_12 | AMD_FAMILY_14 | AMD_FAMILY_15 | AMD_FAMILY_16) @@ -108,27 +108,27 @@ // Family 10h CPU_LOGICAL_ID.Revision equates // ------------------------------------- // Family 10h RB steppings -#define AMD_F10_RB_C0 0x0000000000000001 -#define AMD_F10_RB_C1 0x0000000000000002 -#define AMD_F10_RB_C2 0x0000000000000004 -#define AMD_F10_RB_C3 0x0000000000000008 +#define AMD_F10_RB_C0 0x0000000000000001ull +#define AMD_F10_RB_C1 0x0000000000000002ull +#define AMD_F10_RB_C2 0x0000000000000004ull +#define AMD_F10_RB_C3 0x0000000000000008ull // Family 10h BL steppings -#define AMD_F10_BL_C2 0x0000000000000010 -#define AMD_F10_BL_C3 0x0000000000000020 +#define AMD_F10_BL_C2 0x0000000000000010ull +#define AMD_F10_BL_C3 0x0000000000000020ull // Family 10h DA steppings -#define AMD_F10_DA_C2 0x0000000000000040 -#define AMD_F10_DA_C3 0x0000000000000080 +#define AMD_F10_DA_C2 0x0000000000000040ull +#define AMD_F10_DA_C3 0x0000000000000080ull // Family 10h HY SCM steppings -#define AMD_F10_HY_SCM_D0 0x0000000000000100 -#define AMD_F10_HY_SCM_D1 0x0000000000000400 +#define AMD_F10_HY_SCM_D0 0x0000000000000100ull +#define AMD_F10_HY_SCM_D1 0x0000000000000400ull // Family 10h HY MCM steppings -#define AMD_F10_HY_MCM_D0 0x0000000000000200 -#define AMD_F10_HY_MCM_D1 0x0000000000000800 +#define AMD_F10_HY_MCM_D0 0x0000000000000200ull +#define AMD_F10_HY_MCM_D1 0x0000000000000800ull // Family 10h PH steppings -#define AMD_F10_PH_E0 0x0000000000001000 +#define AMD_F10_PH_E0 0x0000000000001000ull // Family 10h Unknown stepping -#define AMD_F10_UNKNOWN 0x8000000000000000 +#define AMD_F10_UNKNOWN 0x8000000000000000ull // Family 10h Miscellaneous equates #define AMD_F10_C0 (AMD_F10_RB_C0) @@ -168,43 +168,58 @@ // ------------------------------------- // Family 12h LN steppings -#define AMD_F12_LN_A0 0x0000000000000001 -#define AMD_F12_LN_A1 0x0000000000000002 -#define AMD_F12_LN_B0 0x0000000000000004 +#define AMD_F12_LN_A0 0x0000000000000001ull +#define AMD_F12_LN_A1 0x0000000000000002ull +#define AMD_F12_LN_B0 0x0000000000000004ull // Family 12h Unknown stepping -#define AMD_F12_UNKNOWN 0x8000000000000000 +#define AMD_F12_UNKNOWN 0x8000000000000000ull #define AMD_F12_LN_Ax (AMD_F12_LN_A0 | AMD_F12_LN_A1) #define AMD_F12_LN_Bx (AMD_F12_LN_B0) -#define AMD_F12_ALL (AMD_F12_LN_Ax | AMD_F12_LN_Bx | AMD_F12_UNKNOWN) +#define AMD_F12_ALL (AMD_F12_LN_Ax | AMD_F12_LN_Bx | AMD_F12_UNKNOWN) // Family 14h CPU_LOGICAL_ID.Revision equates // ------------------------------------- // Family 14h ON steppings -#define AMD_F14_ON_A0 0x0000000000000001 -#define AMD_F14_ON_A1 0x0000000000000002 -#define AMD_F14_ON_B0 0x0000000000000004 +#define AMD_F14_ON_A0 0x0000000000000001ull +#define AMD_F14_ON_A1 0x0000000000000002ull +#define AMD_F14_ON_B0 0x0000000000000004ull +#define AMD_F14_ON_C0 0x0000000000000008ull + // Family 14h KR steppings +#define AMD_F14_KR_A0 0x0000000000000100ull +#define AMD_F14_KR_A1 0x0000000000000200ull +#define AMD_F14_KR_B0 0x0000000000000400ull // Family 14h Unknown stepping -#define AMD_F14_UNKNOWN 0x8000000000000000 +#define AMD_F14_UNKNOWN 0x8000000000000000ull #define AMD_F14_ON_Ax (AMD_F14_ON_A0 | AMD_F14_ON_A1) #define AMD_F14_ON_Bx (AMD_F14_ON_B0) +#define AMD_F14_ON_Cx (AMD_F14_ON_C0) +#define AMD_F14_ON_ALL (AMD_F14_ON_Ax | AMD_F14_ON_Bx | AMD_F14_ON_Cx) -#define AMD_F14_ALL (AMD_F14_ON_Ax | AMD_F14_ON_Bx | AMD_F14_UNKNOWN) +#define AMD_F14_ALL (AMD_F14_ON_ALL | AMD_F14_UNKNOWN) // Family 15h CPU_LOGICAL_ID.Revision equates // ------------------------------------- // Family 15h OROCHI steppings -#define AMD_F15_OR_A0 0x0000000000000001 +#define AMD_F15_OR_A0 0x0000000000000001ull +#define AMD_F15_OR_A1 0x0000000000000002ull +#define AMD_F15_OR_B0 0x0000000000000004ull + // Family 15h TN steppings +#define AMD_F15_TN_A0 0x0000000000000100ull // Family 15h Unknown stepping -#define AMD_F15_UNKNOWN 0x8000000000000000 +#define AMD_F15_UNKNOWN 0x8000000000000000ull -#define AMD_F15_OR_Ax (AMD_F15_OR_A0) +#define AMD_F15_OR_Ax (AMD_F15_OR_A0 | AMD_F15_OR_A1) +#define AMD_F15_OR_Bx AMD_F15_OR_B0 +#define AMD_F15_OR_GT_Ax (AMD_F15_OR_Bx) +#define AMD_F15_OR_LT_B1 (AMD_F15_OR_Ax | AMD_F15_OR_B0) +#define AMD_F15_OR_ALL (AMD_F15_OR_Ax | AMD_F15_OR_Bx) -#define AMD_F15_ALL (AMD_F15_OR_Ax | AMD_F15_UNKNOWN) +#define AMD_F15_ALL (AMD_F15_OR_ALL | AMD_F15_UNKNOWN) // Family 16h CPU_LOGICAL_ID.Revision equates // TBD diff --git a/src/vendorcode/amd/agesa/f14/Proc/CPU/Feature/PreserveMailbox.c b/src/vendorcode/amd/agesa/f14/Proc/CPU/Feature/PreserveMailbox.c index a68535774e..2f7a931e4d 100644 --- a/src/vendorcode/amd/agesa/f14/Proc/CPU/Feature/PreserveMailbox.c +++ b/src/vendorcode/amd/agesa/f14/Proc/CPU/Feature/PreserveMailbox.c @@ -157,7 +157,7 @@ PreserveMailboxes ( for (Socket = 0; Socket < GetPlatformNumberOfSockets (); Socket++) { for (Module = 0; Module < GetPlatformNumberOfModules (); Module++) { if (GetPciAddress (StdHeader, Socket, Module, &BaseAddress, &IgnoredStatus)) { - GetFeatureServicesOfSocket (&PreserveMailboxFamilyServiceTable, Socket, &FamilySpecificServices, StdHeader); + GetFeatureServicesOfSocket (&PreserveMailboxFamilyServiceTable, Socket, (const VOID **)&FamilySpecificServices, StdHeader); ASSERT (FamilySpecificServices != NULL); NextRegister = FamilySpecificServices->RegisterList; while (NextRegister->AddressValue != ILLEGAL_SBDFO) { @@ -187,7 +187,7 @@ PreserveMailboxes ( for (Socket = 0; Socket < GetPlatformNumberOfSockets (); Socket++) { for (Module = 0; Module < GetPlatformNumberOfModules (); Module++) { if (GetPciAddress (StdHeader, Socket, Module, &BaseAddress, &IgnoredStatus)) { - GetFeatureServicesOfSocket (&PreserveMailboxFamilyServiceTable, Socket, &FamilySpecificServices, StdHeader); + GetFeatureServicesOfSocket (&PreserveMailboxFamilyServiceTable, Socket, (const VOID **)&FamilySpecificServices, StdHeader); NextRegister = FamilySpecificServices->RegisterList; while (NextRegister->AddressValue != ILLEGAL_SBDFO) { ASSERT (RegisterEntryIndex < diff --git a/src/vendorcode/amd/agesa/f14/Proc/CPU/Feature/cpuC6State.c b/src/vendorcode/amd/agesa/f14/Proc/CPU/Feature/cpuC6State.c index bcc3bd87d6..010162f727 100644 --- a/src/vendorcode/amd/agesa/f14/Proc/CPU/Feature/cpuC6State.c +++ b/src/vendorcode/amd/agesa/f14/Proc/CPU/Feature/cpuC6State.c @@ -122,7 +122,7 @@ IsC6FeatureEnabled ( IsEnabled = TRUE; for (Socket = 0; Socket < GetPlatformNumberOfSockets (); Socket++) { if (IsProcessorPresent (Socket, StdHeader)) { - GetFeatureServicesOfSocket (&C6FamilyServiceTable, Socket, &FamilyServices, StdHeader); + GetFeatureServicesOfSocket (&C6FamilyServiceTable, Socket, (const VOID **)&FamilyServices, StdHeader); if ((FamilyServices == NULL) || !FamilyServices->IsC6Supported (FamilyServices, Socket, StdHeader)) { IsEnabled = FALSE; break; @@ -154,7 +154,7 @@ InitializeC6Feature ( { UINT32 BscSocket; UINT32 Ignored; - UINT32 BscCore; + UINT32 BscCoreNum; UINT32 Core; UINT32 Socket; UINT32 NumberOfSockets; @@ -175,8 +175,8 @@ InitializeC6Feature ( if ((EntryPoint & (CPU_FEAT_AFTER_POST_MTRR_SYNC | CPU_FEAT_AFTER_RESUME_MTRR_SYNC)) != 0) { // Load any required microcode patches on both normal boot and resume from S3. - IdentifyCore (StdHeader, &BscSocket, &Ignored, &BscCore, &IgnoredSts); - GetFeatureServicesOfSocket (&C6FamilyServiceTable, BscSocket, &C6FamilyServices, StdHeader); + IdentifyCore (StdHeader, &BscSocket, &Ignored, &BscCoreNum, &IgnoredSts); + GetFeatureServicesOfSocket (&C6FamilyServiceTable, BscSocket, (const VOID **)&C6FamilyServices, StdHeader); if (C6FamilyServices != NULL) { C6FamilyServices->ReloadMicrocodePatchAfterMemInit (StdHeader); } @@ -189,13 +189,13 @@ InitializeC6Feature ( for (Socket = 0; Socket < NumberOfSockets; Socket++) { if (IsProcessorPresent (Socket, StdHeader)) { - GetFeatureServicesOfSocket (&C6FamilyServiceTable, Socket, &C6FamilyServices, StdHeader); + GetFeatureServicesOfSocket (&C6FamilyServiceTable, Socket, (const VOID **)&C6FamilyServices, StdHeader); if (C6FamilyServices != NULL) { // run code on all APs TaskPtr.FuncAddress.PfApTask = C6FamilyServices->ReloadMicrocodePatchAfterMemInit; if (GetActiveCoresInGivenSocket (Socket, &NumberOfCores, StdHeader)) { for (Core = 0; Core < NumberOfCores; Core++) { - if ((Socket != BscSocket) || (Core != BscCore)) { + if ((Socket != BscSocket) || (Core != BscCoreNum)) { ApUtilRunCodeOnSocketCore ((UINT8) Socket, (UINT8) Core, &TaskPtr, StdHeader); } } @@ -230,7 +230,7 @@ EnableC6OnSocket ( IDS_HDT_CONSOLE (CPU_TRACE, " C6 is enabled\n"); - GetFeatureServicesOfCurrentCore (&C6FamilyServiceTable, &FamilyServices, StdHeader); + GetFeatureServicesOfCurrentCore (&C6FamilyServiceTable, (const VOID **)&FamilyServices, StdHeader); FamilyServices->InitializeC6 (FamilyServices, *((UINT64 *) EntryPoint), &CpuEarlyParams->PlatformConfig, diff --git a/src/vendorcode/amd/agesa/f14/Proc/CPU/Feature/cpuCacheFlushOnHalt.c b/src/vendorcode/amd/agesa/f14/Proc/CPU/Feature/cpuCacheFlushOnHalt.c index 3187212fdd..0f40155921 100644 --- a/src/vendorcode/amd/agesa/f14/Proc/CPU/Feature/cpuCacheFlushOnHalt.c +++ b/src/vendorcode/amd/agesa/f14/Proc/CPU/Feature/cpuCacheFlushOnHalt.c @@ -97,6 +97,14 @@ EnableCacheFlushOnHaltOnSocket ( IN AMD_CONFIG_PARAMS *StdHeader, IN AMD_CPU_EARLY_PARAMS *CpuEarlyParams ); + +AGESA_STATUS +InitializeCacheFlushOnHaltFeature ( + IN UINT64 EntryPoint, + IN PLATFORM_CONFIGURATION *PlatformConfig, + IN OUT AMD_CONFIG_PARAMS *StdHeader + ); + /*---------------------------------------------------------------------------------------- * P U B L I C F U N C T I O N S *---------------------------------------------------------------------------------------- @@ -178,7 +186,7 @@ EnableCacheFlushOnHaltOnSocket ( { CPU_CFOH_FAMILY_SERVICES *FamilyServices; - GetFeatureServicesOfCurrentCore (&CacheFlushOnHaltFamilyServiceTable, &FamilyServices, StdHeader); + GetFeatureServicesOfCurrentCore (&CacheFlushOnHaltFamilyServiceTable, (const VOID **)&FamilyServices, StdHeader); if (FamilyServices != NULL) { FamilyServices->SetCacheFlushOnHaltRegister (FamilyServices, *((UINT64 *) EntryPoint), &CpuEarlyParams->PlatformConfig, StdHeader); } diff --git a/src/vendorcode/amd/agesa/f14/Proc/CPU/Feature/cpuCacheInit.c b/src/vendorcode/amd/agesa/f14/Proc/CPU/Feature/cpuCacheInit.c index a38434a1cb..6d067456f3 100644 --- a/src/vendorcode/amd/agesa/f14/Proc/CPU/Feature/cpuCacheInit.c +++ b/src/vendorcode/amd/agesa/f14/Proc/CPU/Feature/cpuCacheInit.c @@ -220,8 +220,8 @@ AllocateExecutionCache ( IDS_HDT_CONSOLE (CPU_TRACE, " Cache size available for execution cache: 0x%x\n", AmdGetExeSize.AvailableExeCacheSize); RemainingExecutionCacheSize = AmdGetExeSize.AvailableExeCacheSize - CurrentAllocatedExeCacheSize; - GetCpuServicesOfCurrentCore (&FamilySpecificServices, StdHeader); - FamilySpecificServices->GetCacheInfo (FamilySpecificServices, &CacheInfoPtr, &Ignored, StdHeader); + GetCpuServicesOfCurrentCore ((const CPU_SPECIFIC_SERVICES **)&FamilySpecificServices, StdHeader); + FamilySpecificServices->GetCacheInfo (FamilySpecificServices, (const VOID **)&CacheInfoPtr, &Ignored, StdHeader); // Process each request entry 0 to 2 for (i = 0; i < 3; i++) { @@ -451,8 +451,8 @@ AmdGetAvailableExeCacheSize ( AGESA_STATUS IgnoredStatus; CPU_SPECIFIC_SERVICES *FamilySpecificServices; - GetCpuServicesOfCurrentCore (&FamilySpecificServices, &AmdGetExeSizeParams->StdHeader); - FamilySpecificServices->GetCacheInfo (FamilySpecificServices, &CacheInfoPtr, &Ignored, &AmdGetExeSizeParams->StdHeader); + GetCpuServicesOfCurrentCore ((const CPU_SPECIFIC_SERVICES **)&FamilySpecificServices, &AmdGetExeSizeParams->StdHeader); + FamilySpecificServices->GetCacheInfo (FamilySpecificServices, (const VOID **)&CacheInfoPtr, &Ignored, &AmdGetExeSizeParams->StdHeader); // CAR_EXE mode is either "Limited by L2 size" or "Infinite Execution space" ASSERT (CacheInfoPtr->CarExeType < MaxCarExeMode); if (CacheInfoPtr->CarExeType == InfiniteExe) { diff --git a/src/vendorcode/amd/agesa/f14/Proc/CPU/Feature/cpuCoreLeveling.c b/src/vendorcode/amd/agesa/f14/Proc/CPU/Feature/cpuCoreLeveling.c index c6d902c1d2..700f9aeec8 100644 --- a/src/vendorcode/amd/agesa/f14/Proc/CPU/Feature/cpuCoreLeveling.c +++ b/src/vendorcode/amd/agesa/f14/Proc/CPU/Feature/cpuCoreLeveling.c @@ -318,7 +318,7 @@ CoreLevelingAtEarly ( // Set down core register for (Socket = 0; Socket < NumberOfSockets; Socket++) { if (IsProcessorPresent (Socket, StdHeader)) { - GetFeatureServicesOfSocket (&CoreLevelingFamilyServiceTable, Socket, &FamilySpecificServices, StdHeader); + GetFeatureServicesOfSocket (&CoreLevelingFamilyServiceTable, Socket, (const VOID **)&FamilySpecificServices, StdHeader); if (FamilySpecificServices != NULL) { for (Module = 0; Module < NumberOfModules; Module++) { RegUpdated = FamilySpecificServices->SetDownCoreRegister (FamilySpecificServices, &Socket, &Module, &LeveledCores, CoreLevelMode, StdHeader); diff --git a/src/vendorcode/amd/agesa/f14/Proc/CPU/Feature/cpuCpb.c b/src/vendorcode/amd/agesa/f14/Proc/CPU/Feature/cpuCpb.c index 50264f0f21..e31c6b80b2 100644 --- a/src/vendorcode/amd/agesa/f14/Proc/CPU/Feature/cpuCpb.c +++ b/src/vendorcode/amd/agesa/f14/Proc/CPU/Feature/cpuCpb.c @@ -108,7 +108,7 @@ IsCpbFeatureEnabled ( if (PlatformConfig->CpbMode == CpbModeAuto) { for (Socket = 0; Socket < GetPlatformNumberOfSockets (); Socket++) { if (IsProcessorPresent (Socket, StdHeader)) { - GetFeatureServicesOfSocket (&CpbFamilyServiceTable, Socket, &FamilyServices, StdHeader); + GetFeatureServicesOfSocket (&CpbFamilyServiceTable, Socket, (const VOID **)&FamilyServices, StdHeader); if (FamilyServices != NULL) { if (FamilyServices->IsCpbSupported (FamilyServices, PlatformConfig, Socket, StdHeader)) { IsEnabled = TRUE; @@ -152,7 +152,7 @@ InitializeCpbFeature ( for (Socket = 0; Socket < GetPlatformNumberOfSockets (); Socket++) { if (IsProcessorPresent (Socket, StdHeader)) { - GetFeatureServicesOfSocket (&CpbFamilyServiceTable, Socket, &FamilyServices, StdHeader); + GetFeatureServicesOfSocket (&CpbFamilyServiceTable, Socket, (const VOID **)&FamilyServices, StdHeader); if (FamilyServices != NULL) { if (FamilyServices->IsCpbSupported (FamilyServices, PlatformConfig, Socket, StdHeader)) { CalledStatus = FamilyServices->EnableCpbOnSocket (FamilyServices, PlatformConfig, EntryPoint, Socket, StdHeader); diff --git a/src/vendorcode/amd/agesa/f14/Proc/CPU/Feature/cpuDmi.c b/src/vendorcode/amd/agesa/f14/Proc/CPU/Feature/cpuDmi.c index eb2d509818..0bf357d87a 100644 --- a/src/vendorcode/amd/agesa/f14/Proc/CPU/Feature/cpuDmi.c +++ b/src/vendorcode/amd/agesa/f14/Proc/CPU/Feature/cpuDmi.c @@ -92,6 +92,28 @@ IntToString ( IN UINT8 SizeInByte ); +AGESA_STATUS +GetDmiInfoStub ( + IN OUT AMD_CONFIG_PARAMS *StdHeader, + IN OUT DMI_INFO **DmiTable + ); + +AGESA_STATUS +GetDmiInfoMain ( + IN OUT AMD_CONFIG_PARAMS *StdHeader, + IN OUT DMI_INFO **DmiTable + ); + +AGESA_STATUS +ReleaseDmiBufferStub ( + IN OUT AMD_CONFIG_PARAMS *StdHeader + ); + +AGESA_STATUS +ReleaseDmiBuffer ( + IN OUT AMD_CONFIG_PARAMS *StdHeader + ); + /*---------------------------------------------------------------------------------------- * E X P O R T E D F U N C T I O N S *---------------------------------------------------------------------------------------- @@ -183,7 +205,7 @@ GetDmiInfoMain ( UINT16 NumberOfDimm; UINT32 SocketNum; UINT64 MsrData; - UINT64 MsrRegister; + UINT64 MsrReg; BOOLEAN FamilyNotFound; AGESA_STATUS Flag; AGESA_STATUS CalledStatus; @@ -357,12 +379,12 @@ GetDmiInfoMain ( // TYPE 19 DmiBufferPtr->T19.StartingAddr = 0; - LibAmdMsrRead (TOP_MEM2, &MsrRegister, StdHeader); - if (MsrRegister == 0) { - LibAmdMsrRead (TOP_MEM, &MsrRegister, StdHeader); - DmiBufferPtr->T19.EndingAddr = (UINT32) (MsrRegister >> 10); - } else if (MsrRegister != 0) { - DmiBufferPtr->T19.EndingAddr = (UINT32) (MsrRegister >> 10); + LibAmdMsrRead (TOP_MEM2, &MsrReg, StdHeader); + if (MsrReg == 0) { + LibAmdMsrRead (TOP_MEM, &MsrReg, StdHeader); + DmiBufferPtr->T19.EndingAddr = (UINT32) (MsrReg >> 10); + } else if (MsrReg != 0) { + DmiBufferPtr->T19.EndingAddr = (UINT32) (MsrReg >> 10); } DmiBufferPtr->T19.PartitionWidth = 0xFF; diff --git a/src/vendorcode/amd/agesa/f14/Proc/CPU/Feature/cpuFeatureLeveling.c b/src/vendorcode/amd/agesa/f14/Proc/CPU/Feature/cpuFeatureLeveling.c index afa222600e..2d11ffa6c0 100644 --- a/src/vendorcode/amd/agesa/f14/Proc/CPU/Feature/cpuFeatureLeveling.c +++ b/src/vendorcode/amd/agesa/f14/Proc/CPU/Feature/cpuFeatureLeveling.c @@ -130,7 +130,7 @@ FeatureLeveling ( { UINT32 BscSocket; UINT32 Ignored; - UINT32 BscCore; + UINT32 BscCoreNum; UINT32 Socket; UINT32 Core; UINT32 NumberOfSockets; @@ -151,7 +151,7 @@ FeatureLeveling ( *NeedLeveling = FALSE; LibAmdMemFill (globalCpuFeatureList, 0xFF, sizeof (CPU_FEATURES_LIST), StdHeader); - IdentifyCore (StdHeader, &BscSocket, &Ignored, &BscCore, &IgnoredSts); + IdentifyCore (StdHeader, &BscSocket, &Ignored, &BscCoreNum, &IgnoredSts); NumberOfSockets = GetPlatformNumberOfSockets (); TaskPtr.FuncAddress.PfApTaskI = SaveFeatures; @@ -174,7 +174,7 @@ FeatureLeveling ( for (Socket = 0; Socket < NumberOfSockets; Socket++) { if (GetActiveCoresInGivenSocket (Socket, &NumberOfCores, StdHeader)) { for (Core = 0; Core < NumberOfCores; Core++) { - if ((Socket != BscSocket) || (Core != BscCore)) { + if ((Socket != BscSocket) || (Core != BscCoreNum)) { ApUtilRunCodeOnSocketCore ((UINT8)Socket, (UINT8)Core, &TaskPtr, StdHeader); } } @@ -210,7 +210,7 @@ SaveFeatures ( CPU_SPECIFIC_SERVICES *FamilySpecificServices; FamilySpecificServices = NULL; - GetCpuServicesOfCurrentCore (&FamilySpecificServices, StdHeader); + GetCpuServicesOfCurrentCore ((const CPU_SPECIFIC_SERVICES **)&FamilySpecificServices, StdHeader); FamilySpecificServices->SaveFeatures (FamilySpecificServices, cpuFeatureListPtr, StdHeader); } @@ -235,7 +235,7 @@ WriteFeatures ( CPU_SPECIFIC_SERVICES *FamilySpecificServices; FamilySpecificServices = NULL; - GetCpuServicesOfCurrentCore (&FamilySpecificServices, StdHeader); + GetCpuServicesOfCurrentCore ((const CPU_SPECIFIC_SERVICES **)&FamilySpecificServices, StdHeader); FamilySpecificServices->WriteFeatures (FamilySpecificServices, cpuFeatureListPtr, StdHeader); } @@ -258,9 +258,9 @@ GetGlobalCpuFeatureListAddress ( IN AMD_CONFIG_PARAMS *StdHeader ) { - UINT64 AddressValue; + VOID *AddressValue; - AddressValue = GLOBAL_CPU_FEATURE_LIST_TEMP_ADDR; + AddressValue = (VOID *)GLOBAL_CPU_FEATURE_LIST_TEMP_ADDR; *Address = (UINT64 *)(AddressValue); } diff --git a/src/vendorcode/amd/agesa/f14/Proc/CPU/Feature/cpuFeatures.c b/src/vendorcode/amd/agesa/f14/Proc/CPU/Feature/cpuFeatures.c index fa18acf6fe..799fed0fe7 100644 --- a/src/vendorcode/amd/agesa/f14/Proc/CPU/Feature/cpuFeatures.c +++ b/src/vendorcode/amd/agesa/f14/Proc/CPU/Feature/cpuFeatures.c @@ -178,7 +178,7 @@ IsNonCoherentHt1 ( for (Socket = 0; Socket < GetPlatformNumberOfSockets (); Socket++) { if (IsProcessorPresent (Socket, StdHeader)) { - GetCpuServicesOfSocket (Socket, &CpuServices, StdHeader); + GetCpuServicesOfSocket (Socket, (const CPU_SPECIFIC_SERVICES **)&CpuServices, StdHeader); for (Module = 0; Module < GetPlatformNumberOfModules (); Module++) { if (GetPciAddress (StdHeader, Socket, Module, &PciAddress, &AgesaStatus)) { HtHostFeats.HtHostValue = 0; diff --git a/src/vendorcode/amd/agesa/f14/Proc/CPU/Feature/cpuHtAssist.c b/src/vendorcode/amd/agesa/f14/Proc/CPU/Feature/cpuHtAssist.c index c0c3e0a91f..9370afdddf 100644 --- a/src/vendorcode/amd/agesa/f14/Proc/CPU/Feature/cpuHtAssist.c +++ b/src/vendorcode/amd/agesa/f14/Proc/CPU/Feature/cpuHtAssist.c @@ -135,7 +135,7 @@ IsHtAssistEnabled ( if (IsEnabled) { for (Socket = 0; Socket < GetPlatformNumberOfSockets (); Socket++) { if (IsProcessorPresent (Socket, StdHeader)) { - GetFeatureServicesOfSocket (&HtAssistFamilyServiceTable, Socket, &FamilyServices, StdHeader); + GetFeatureServicesOfSocket (&HtAssistFamilyServiceTable, Socket, (const VOID **)&FamilyServices, StdHeader); if ((FamilyServices == NULL) || !FamilyServices->IsHtAssistSupported (FamilyServices, Socket, StdHeader)) { IsEnabled = FALSE; break; @@ -197,7 +197,7 @@ InitializeHtAssistFeature ( // cache is still enabled. for (Socket = 0; Socket < MAX_SOCKETS_SUPPORTED; Socket++) { if (IsProcessorPresent (Socket, StdHeader)) { - GetFeatureServicesOfSocket (&HtAssistFamilyServiceTable, Socket, &FamilyServices[Socket], StdHeader); + GetFeatureServicesOfSocket (&HtAssistFamilyServiceTable, Socket, (const VOID **)&FamilyServices[Socket], StdHeader); } else { FamilyServices[Socket] = NULL; } @@ -303,7 +303,7 @@ DisableAllCaches ( UINT32 CR0Data; HT_ASSIST_FAMILY_SERVICES *FamilyServices; - GetFeatureServicesOfCurrentCore (&HtAssistFamilyServiceTable, &FamilyServices, &ApExeParams->StdHeader); + GetFeatureServicesOfCurrentCore (&HtAssistFamilyServiceTable, (const VOID **)&FamilyServices, &ApExeParams->StdHeader); FamilyServices->HookDisableCache (FamilyServices, &ApExeParams->StdHeader); @@ -341,7 +341,7 @@ EnableAllCaches ( CR0Data &= ~(0x60000000); LibAmdWriteCpuReg (0, CR0Data); - GetFeatureServicesOfCurrentCore (&HtAssistFamilyServiceTable, &FamilyServices, &ApExeParams->StdHeader); + GetFeatureServicesOfCurrentCore (&HtAssistFamilyServiceTable, (const VOID **)&FamilyServices, &ApExeParams->StdHeader); FamilyServices->HookEnableCache (FamilyServices, &ApExeParams->StdHeader); diff --git a/src/vendorcode/amd/agesa/f14/Proc/CPU/Feature/cpuHwC1e.c b/src/vendorcode/amd/agesa/f14/Proc/CPU/Feature/cpuHwC1e.c index b5b62c733a..c3542a19ae 100644 --- a/src/vendorcode/amd/agesa/f14/Proc/CPU/Feature/cpuHwC1e.c +++ b/src/vendorcode/amd/agesa/f14/Proc/CPU/Feature/cpuHwC1e.c @@ -117,7 +117,7 @@ IsHwC1eFeatureEnabled ( if (GetNumberOfProcessors (StdHeader) == 1) { GetApMailbox (&ApMailboxes.ApMailInfo.Info, StdHeader); if (ApMailboxes.ApMailInfo.Fields.ModuleType == 0) { - GetFeatureServicesOfCurrentCore (&HwC1eFamilyServiceTable, &FamilyServices, StdHeader); + GetFeatureServicesOfCurrentCore (&HwC1eFamilyServiceTable, (const VOID **)&FamilyServices, StdHeader); if (FamilyServices != NULL) { IsEnabled = FamilyServices->IsHwC1eSupported (FamilyServices, StdHeader); } @@ -157,7 +157,7 @@ InitializeHwC1eFeature ( IDS_HDT_CONSOLE (CPU_TRACE, " HW C1e is enabled\n"); if (IsWarmReset (StdHeader)) { - GetFeatureServicesOfCurrentCore (&HwC1eFamilyServiceTable, &FamilyServices, StdHeader); + GetFeatureServicesOfCurrentCore (&HwC1eFamilyServiceTable, (const VOID **)&FamilyServices, StdHeader); CalledStatus = FamilyServices->InitializeHwC1e (FamilyServices, EntryPoint, PlatformConfig, StdHeader); if (CalledStatus > AgesaStatus) { AgesaStatus = CalledStatus; diff --git a/src/vendorcode/amd/agesa/f14/Proc/CPU/Feature/cpuIoCstate.c b/src/vendorcode/amd/agesa/f14/Proc/CPU/Feature/cpuIoCstate.c index 8893415d38..46a8ece031 100644 --- a/src/vendorcode/amd/agesa/f14/Proc/CPU/Feature/cpuIoCstate.c +++ b/src/vendorcode/amd/agesa/f14/Proc/CPU/Feature/cpuIoCstate.c @@ -118,7 +118,7 @@ IsIoCstateFeatureSupported ( if ((PlatformConfig->CStateIoBaseAddress != 0) && (PlatformConfig->CStateIoBaseAddress <= 0xFFF8)) { for (Socket = 0; Socket < GetPlatformNumberOfSockets (); Socket++) { if (IsProcessorPresent (Socket, StdHeader)) { - GetFeatureServicesOfSocket (&IoCstateFamilyServiceTable, Socket, &IoCstateServices, StdHeader); + GetFeatureServicesOfSocket (&IoCstateFamilyServiceTable, Socket, (const VOID **)&IoCstateServices, StdHeader); if (IoCstateServices != NULL) { if (IoCstateServices->IsIoCstateSupported (IoCstateServices, Socket, StdHeader)) { IsSupported = TRUE; @@ -193,7 +193,7 @@ EnableIoCstateOnSocket ( { IO_CSTATE_FAMILY_SERVICES *FamilyServices; - GetFeatureServicesOfCurrentCore (&IoCstateFamilyServiceTable, &FamilyServices, StdHeader); + GetFeatureServicesOfCurrentCore (&IoCstateFamilyServiceTable, (const VOID **)&FamilyServices, StdHeader); FamilyServices->InitializeIoCstate (FamilyServices, *((UINT64 *) EntryPoint), &CpuEarlyParams->PlatformConfig, diff --git a/src/vendorcode/amd/agesa/f14/Proc/CPU/Feature/cpuLowPwrPstate.c b/src/vendorcode/amd/agesa/f14/Proc/CPU/Feature/cpuLowPwrPstate.c index 0b29512dac..8d5cbd1bd9 100644 --- a/src/vendorcode/amd/agesa/f14/Proc/CPU/Feature/cpuLowPwrPstate.c +++ b/src/vendorcode/amd/agesa/f14/Proc/CPU/Feature/cpuLowPwrPstate.c @@ -116,7 +116,7 @@ IsLowPwrPstateFeatureSupported ( IsSupported = FALSE; for (Socket = 0; Socket < GetPlatformNumberOfSockets (); Socket++) { if (IsProcessorPresent (Socket, StdHeader)) { - GetFeatureServicesOfSocket (&LowPwrPstateFamilyServiceTable, Socket, &FamilyServices, StdHeader); + GetFeatureServicesOfSocket (&LowPwrPstateFamilyServiceTable, Socket, (const VOID **)&FamilyServices, StdHeader); if (FamilyServices != NULL) { if (FamilyServices->IsLowPwrPstateSupported (FamilyServices, PlatformConfig, Socket, StdHeader)) { IsSupported = TRUE; @@ -189,7 +189,7 @@ EnableLowPwrPstateOnSocket ( { LOW_PWR_PSTATE_FAMILY_SERVICES *FamilyServices; - GetFeatureServicesOfCurrentCore (&LowPwrPstateFamilyServiceTable, &FamilyServices, StdHeader); + GetFeatureServicesOfCurrentCore (&LowPwrPstateFamilyServiceTable, (const VOID **)&FamilyServices, StdHeader); FamilyServices->EnableLowPwrPstate (FamilyServices, &CpuEarlyParams->PlatformConfig, *((UINT64 *) EntryPoint), diff --git a/src/vendorcode/amd/agesa/f14/Proc/CPU/Feature/cpuMsgBasedC1e.c b/src/vendorcode/amd/agesa/f14/Proc/CPU/Feature/cpuMsgBasedC1e.c index f09b2b5046..9e68d93f49 100644 --- a/src/vendorcode/amd/agesa/f14/Proc/CPU/Feature/cpuMsgBasedC1e.c +++ b/src/vendorcode/amd/agesa/f14/Proc/CPU/Feature/cpuMsgBasedC1e.c @@ -127,7 +127,7 @@ IsMsgBasedC1eFeatureEnabled ( } else { for (Socket = 0; Socket < GetPlatformNumberOfSockets (); Socket++) { if (IsProcessorPresent (Socket, StdHeader)) { - GetFeatureServicesOfSocket (&MsgBasedC1eFamilyServiceTable, Socket, &FamilyServices, StdHeader); + GetFeatureServicesOfSocket (&MsgBasedC1eFamilyServiceTable, Socket, (const VOID **)&FamilyServices, StdHeader); if ((FamilyServices == NULL) || !FamilyServices->IsMsgBasedC1eSupported (FamilyServices, Socket, StdHeader)) { IsEnabled = FALSE; break; @@ -197,7 +197,7 @@ EnableMsgC1eOnSocket ( { MSG_BASED_C1E_FAMILY_SERVICES *FamilyServices; - GetFeatureServicesOfCurrentCore (&MsgBasedC1eFamilyServiceTable, &FamilyServices, StdHeader); + GetFeatureServicesOfCurrentCore (&MsgBasedC1eFamilyServiceTable, (const VOID **)&FamilyServices, StdHeader); FamilyServices->InitializeMsgBasedC1e (FamilyServices, *((UINT64 *) EntryPoint), &CpuEarlyParams->PlatformConfig, diff --git a/src/vendorcode/amd/agesa/f14/Proc/CPU/Feature/cpuPstateGather.c b/src/vendorcode/amd/agesa/f14/Proc/CPU/Feature/cpuPstateGather.c index 96ac698fb5..3367b1350c 100644 --- a/src/vendorcode/amd/agesa/f14/Proc/CPU/Feature/cpuPstateGather.c +++ b/src/vendorcode/amd/agesa/f14/Proc/CPU/Feature/cpuPstateGather.c @@ -89,6 +89,18 @@ extern CPU_FAMILY_SUPPORT_TABLE PstateFamilyServiceTable; *---------------------------------------------------------------------------- */ +AGESA_STATUS +PStateGatherStub ( + IN AMD_CONFIG_PARAMS *StdHeader, + IN OUT S_CPU_AMD_PSTATE *PStateStrucPtr + ); + +AGESA_STATUS +PStateGatherMain ( + IN AMD_CONFIG_PARAMS *StdHeader, + IN OUT S_CPU_AMD_PSTATE *PStateStrucPtr + ); + /*---------------------------------------------------------------------------- * EXPORTED FUNCTIONS * @@ -204,7 +216,7 @@ PStateGatherMain ( ASSERT (IsBsp (StdHeader, &IgnoredSts)); FamilyServices = NULL; - GetFeatureServicesOfCurrentCore (&PstateFamilyServiceTable, &FamilyServices, StdHeader); + GetFeatureServicesOfCurrentCore (&PstateFamilyServiceTable, (const VOID **)&FamilyServices, StdHeader); ASSERT (FamilyServices != NULL); PopulatedSockets = 1; @@ -306,7 +318,7 @@ PStateGather ( FamilyServices = NULL; PStateEnabled = FALSE; - GetFeatureServicesOfCurrentCore (&PstateFamilyServiceTable, &FamilyServices, StdHeader); + GetFeatureServicesOfCurrentCore (&PstateFamilyServiceTable, (const VOID **)&FamilyServices, StdHeader); ASSERT (FamilyServices != NULL); // diff --git a/src/vendorcode/amd/agesa/f14/Proc/CPU/Feature/cpuPstateLeveling.c b/src/vendorcode/amd/agesa/f14/Proc/CPU/Feature/cpuPstateLeveling.c index a59b791a08..c0ba407847 100644 --- a/src/vendorcode/amd/agesa/f14/Proc/CPU/Feature/cpuPstateLeveling.c +++ b/src/vendorcode/amd/agesa/f14/Proc/CPU/Feature/cpuPstateLeveling.c @@ -107,6 +107,24 @@ PutCoreInPState0 ( IN AMD_CONFIG_PARAMS *StdHeader ); +AGESA_STATUS +PStateLevelingStub ( + IN OUT S_CPU_AMD_PSTATE *PStateStrucPtr, + IN AMD_CONFIG_PARAMS *StdHeader + ); + +AGESA_STATUS +PStateLevelingMain ( + IN OUT S_CPU_AMD_PSTATE *PStateStrucPtr, + IN AMD_CONFIG_PARAMS *StdHeader + ); + +VOID +CorePstateRegModify ( + IN VOID *CpuAmdPState, + IN AMD_CONFIG_PARAMS *StdHeader + ); + /** *--------------------------------------------------------------------------------------- @@ -874,7 +892,7 @@ PutAllCoreInPState0 ( AP_TASK TaskPtr; UINT32 BscSocket; UINT32 Ignored; - UINT32 BscCore; + UINT32 BscCoreNum; UINT32 Core; UINT32 Socket; UINT32 NumberOfSockets; @@ -887,7 +905,7 @@ PutAllCoreInPState0 ( TaskPtr.DataTransfer.DataPtr = PStateBufferPtr; TaskPtr.DataTransfer.DataTransferFlags = DATA_IN_MEMORY; - IdentifyCore (StdHeader, &BscSocket, &Ignored, &BscCore, &IgnoredSts); + IdentifyCore (StdHeader, &BscSocket, &Ignored, &BscCoreNum, &IgnoredSts); NumberOfSockets = GetPlatformNumberOfSockets (); PutCoreInPState0 (PStateBufferPtr, StdHeader); @@ -895,7 +913,7 @@ PutAllCoreInPState0 ( for (Socket = 0; Socket < NumberOfSockets; Socket++) { if (GetActiveCoresInGivenSocket (Socket, &NumberOfCores, StdHeader)) { for (Core = 0; Core < NumberOfCores; Core++) { - if ((Socket != (UINT32) BscSocket) || (Core != (UINT32) BscCore)) { + if ((Socket != (UINT32) BscSocket) || (Core != (UINT32) BscCoreNum)) { ApUtilRunCodeOnSocketCore ((UINT8) Socket, (UINT8) Core, &TaskPtr, StdHeader); } } @@ -931,7 +949,7 @@ CorePstateRegModify ( PSTATE_CPU_FAMILY_SERVICES *FamilySpecificServices; FamilySpecificServices = NULL; - GetFeatureServicesOfCurrentCore (&PstateFamilyServiceTable, &FamilySpecificServices, StdHeader); + GetFeatureServicesOfCurrentCore (&PstateFamilyServiceTable, (const VOID **)&FamilySpecificServices, StdHeader); ASSERT (FamilySpecificServices != NULL) FamilySpecificServices->SetPStateLevelReg (FamilySpecificServices, (S_CPU_AMD_PSTATE *) CpuAmdPState, StdHeader); } @@ -956,7 +974,7 @@ StartPstateMsrModify ( AP_TASK TaskPtr; UINT32 BscSocket; UINT32 Ignored; - UINT32 BscCore; + UINT32 BscCoreNum; UINT32 Core; UINT32 Socket; UINT32 NumberOfSockets; @@ -969,7 +987,7 @@ StartPstateMsrModify ( TaskPtr.DataTransfer.DataPtr = CpuAmdPState; TaskPtr.DataTransfer.DataTransferFlags = DATA_IN_MEMORY; - IdentifyCore (StdHeader, &BscSocket, &Ignored, &BscCore, &IgnoredSts); + IdentifyCore (StdHeader, &BscSocket, &Ignored, &BscCoreNum, &IgnoredSts); NumberOfSockets = GetPlatformNumberOfSockets (); CorePstateRegModify (CpuAmdPState, StdHeader); @@ -977,7 +995,7 @@ StartPstateMsrModify ( for (Socket = 0; Socket < NumberOfSockets; Socket++) { if (GetActiveCoresInGivenSocket (Socket, &NumberOfCores, StdHeader)) { for (Core = 0; Core < NumberOfCores; Core++) { - if ((Socket != (UINT32) BscSocket) || (Core != (UINT32) BscCore)) { + if ((Socket != (UINT32) BscSocket) || (Core != (UINT32) BscCoreNum)) { ApUtilRunCodeOnSocketCore ((UINT8) Socket, (UINT8) Core, &TaskPtr, StdHeader); } } @@ -1067,7 +1085,7 @@ PutCoreInPState0 ( return; } - GetCpuServicesOfCurrentCore (&FamilySpecificServices, StdHeader); + GetCpuServicesOfCurrentCore ((const CPU_SPECIFIC_SERVICES **)&FamilySpecificServices, StdHeader); FamilySpecificServices->TransitionPstate (FamilySpecificServices, (UINT8) 0, (BOOLEAN) FALSE, StdHeader); } diff --git a/src/vendorcode/amd/agesa/f14/Proc/CPU/Feature/cpuPstateTables.c b/src/vendorcode/amd/agesa/f14/Proc/CPU/Feature/cpuPstateTables.c index 428b3459cf..aa14af1b66 100644 --- a/src/vendorcode/amd/agesa/f14/Proc/CPU/Feature/cpuPstateTables.c +++ b/src/vendorcode/amd/agesa/f14/Proc/CPU/Feature/cpuPstateTables.c @@ -81,14 +81,14 @@ extern CPU_FAMILY_SUPPORT_TABLE IoCstateFamilyServiceTable; STATIC ACPI_TABLE_HEADER ROMDATA CpuSsdtHdrStruct = { - 'S','S','D','T', + {'S','S','D','T'}, 0, 1, 0, - 'A','M','D',' ',' ',' ', - 'P','O','W','E','R','N','O','W', + {'A','M','D',' ',' ',' '}, + {'P','O','W','E','R','N','O','W'}, 1, - 'A','M','D',' ', + {'A','M','D',' '}, 1 }; @@ -105,6 +105,47 @@ STATIC ACPI_TABLE_HEADER ROMDATA CpuSsdtHdrStruct = *---------------------------------------------------------------------------- */ +UINT32 +CalAcpiTablesSize ( + IN S_CPU_AMD_PSTATE *AmdPstatePtr, + IN PLATFORM_CONFIGURATION *PlatformConfig, + IN AMD_CONFIG_PARAMS *StdHeader + ); + +AGESA_STATUS +GenerateSsdtStub ( + IN AMD_CONFIG_PARAMS *StdHeader, + IN PLATFORM_CONFIGURATION *PlatformConfig, + IN OUT VOID **SsdtPtr + ); + +UINT32 +CreateAcpiTablesStub ( + IN PLATFORM_CONFIGURATION *PlatformConfig, + IN PSTATE_LEVELING *PStateLevelingBuffer, + IN OUT VOID **SsdtPtr, + IN UINT8 LocalApicId, + IN AMD_CONFIG_PARAMS *StdHeader + ); + +UINT32 +CreatePStateAcpiTables ( + IN PLATFORM_CONFIGURATION *PlatformConfig, + IN PSTATE_LEVELING *PStateLevelingBuffer, + IN OUT VOID **SsdtPtr, + IN UINT8 LocalApicId, + IN AMD_CONFIG_PARAMS *StdHeader + ); + +UINT32 +CreateCStateAcpiTables ( + IN PLATFORM_CONFIGURATION *PlatformConfig, + IN PSTATE_LEVELING *PStateLevelingBuffer, + IN OUT VOID **SsdtPtr, + IN UINT8 LocalApicId, + IN AMD_CONFIG_PARAMS *StdHeader + ); + /** *--------------------------------------------------------------------------------------- * @@ -147,7 +188,7 @@ CalAcpiTablesSize ( MaxSocketNumberInSystem = AmdPstatePtr->TotalSocketInSystem; if (IsFeatureEnabled (IoCstate, PlatformConfig, StdHeader)) { - GetFeatureServicesOfCurrentCore (&IoCstateFamilyServiceTable, &IoCstateFamilyServices, StdHeader); + GetFeatureServicesOfCurrentCore (&IoCstateFamilyServiceTable, (const VOID **)&IoCstateFamilyServices, StdHeader); // If we're supporting multiple families, only proceed when IO Cstate family services are available if (IoCstateFamilyServices != NULL) { CstateAcpiObjSize = IoCstateFamilyServices->GetAcpiCstObj (IoCstateFamilyServices, PlatformConfig, StdHeader); @@ -333,8 +374,8 @@ GenerateSsdt ( } ScopeAcpiTablesStructPtr->ScopeNamePt1b__ = SCOPE_NAME__; ASSERT ((PlatformConfig->ProcessorScopeName0 >= 'A') && (PlatformConfig->ProcessorScopeName0 <= 'Z')) - ASSERT ((PlatformConfig->ProcessorScopeName1 >= 'A') && (PlatformConfig->ProcessorScopeName1 <= 'Z') || \ - (PlatformConfig->ProcessorScopeName1 >= '0') && (PlatformConfig->ProcessorScopeName1 <= '9') || \ + ASSERT (((PlatformConfig->ProcessorScopeName1 >= 'A') && (PlatformConfig->ProcessorScopeName1 <= 'Z')) || \ + ((PlatformConfig->ProcessorScopeName1 >= '0') && (PlatformConfig->ProcessorScopeName1 <= '9')) || \ (PlatformConfig->ProcessorScopeName1 == '_')) ScopeAcpiTablesStructPtr->ScopeNamePt2a_C = PlatformConfig->ProcessorScopeName0; @@ -555,7 +596,7 @@ CreatePStateAcpiTables ( // Calculate PCI address for socket only GetPciAddress (StdHeader, (UINT32) PStateLevelingBuffer->SocketNumber, 0, &PciAddress, &IgnoredStatus); TransAndBusMastLatency = 0; - GetFeatureServicesOfSocket (&PstateFamilyServiceTable, (UINT32) PStateLevelingBuffer->SocketNumber, &FamilyServices, StdHeader); + GetFeatureServicesOfSocket (&PstateFamilyServiceTable, (UINT32) PStateLevelingBuffer->SocketNumber, (const VOID **)&FamilyServices, StdHeader); ASSERT (FamilyServices != NULL) FamilyServices->GetPstateLatency ( FamilyServices, PStateLevelingBuffer, @@ -698,7 +739,7 @@ CreatePStateAcpiTables ( pPsdBodyAcpiTables = (PSD_BODY *) pXpssBodyAcpiTables; // Get Total Cores Per Node if (GetActiveCoresInGivenSocket ((UINT32) PStateLevelingBuffer->SocketNumber, &CoreCount1, StdHeader)) { - GetFeatureServicesOfSocket (&PstateFamilyServiceTable, (UINT32) PStateLevelingBuffer->SocketNumber, &FamilyServices, StdHeader); + GetFeatureServicesOfSocket (&PstateFamilyServiceTable, (UINT32) PStateLevelingBuffer->SocketNumber, (const VOID **)&FamilyServices, StdHeader); ASSERT (FamilyServices != NULL) if ((CoreCount1 != 1) && (OptionPstateLateConfiguration.CfgPstatePsd) && FamilyServices->IsPstatePsdNeeded (FamilyServices, PlatformConfig, StdHeader)) { @@ -819,7 +860,7 @@ CreateCStateAcpiTables ( ObjSize = 0; if (IsFeatureEnabled (IoCstate, PlatformConfig, StdHeader)) { - GetFeatureServicesOfCurrentCore (&IoCstateFamilyServiceTable, &IoCstateFamilyServices, StdHeader); + GetFeatureServicesOfCurrentCore (&IoCstateFamilyServiceTable, (const VOID **)&IoCstateFamilyServices, StdHeader); // If we're supporting multiple families, only proceed when IO Cstate family services are available if (IoCstateFamilyServices != NULL) { IoCstateFamilyServices->CreateAcpiCstObj (IoCstateFamilyServices, LocalApicId, SsdtPtr, StdHeader); diff --git a/src/vendorcode/amd/agesa/f14/Proc/CPU/Feature/cpuSlit.c b/src/vendorcode/amd/agesa/f14/Proc/CPU/Feature/cpuSlit.c index 70567223a9..6290afea28 100644 --- a/src/vendorcode/amd/agesa/f14/Proc/CPU/Feature/cpuSlit.c +++ b/src/vendorcode/amd/agesa/f14/Proc/CPU/Feature/cpuSlit.c @@ -77,14 +77,14 @@ extern OPTION_SLIT_CONFIGURATION OptionSlitConfiguration; // global user config STATIC ACPI_TABLE_HEADER ROMDATA CpuSlitHdrStruct = { - 'S','L','I','T', + {'S','L','I','T'}, 0, 1, 0, - 'A','M','D',' ',' ',' ', - 'A','G','E','S','A',' ',' ',' ', + {'A','M','D',' ',' ',' '}, + {'A','G','E','S','A',' ',' ',' '}, 1, - 'A','M','D',' ', + {'A','M','D',' '}, 1 }; @@ -97,6 +97,21 @@ STATIC ACPI_TABLE_HEADER ROMDATA CpuSlitHdrStruct = * P R O T O T Y P E S O F L O C A L F U N C T I O N S *---------------------------------------------------------------------------------------- */ + +AGESA_STATUS +GetAcpiSlitStub ( + IN OUT AMD_CONFIG_PARAMS *StdHeader, + IN PLATFORM_CONFIGURATION *PlatformConfig, + IN OUT VOID **SlitPtr + ); + +AGESA_STATUS +GetAcpiSlitMain ( + IN OUT AMD_CONFIG_PARAMS *StdHeader, + IN PLATFORM_CONFIGURATION *PlatformConfig, + IN OUT VOID **SlitPtr + ); + VOID STATIC AcpiSlitHBufferFind ( @@ -104,12 +119,21 @@ AcpiSlitHBufferFind ( IN UINT8 **SocketTopologyPtr ); +AGESA_STATUS +ReleaseSlitBufferStub ( + IN OUT AMD_CONFIG_PARAMS *StdHeader + ); + +AGESA_STATUS +ReleaseSlitBuffer ( + IN OUT AMD_CONFIG_PARAMS *StdHeader + ); + /*---------------------------------------------------------------------------------------- * P R O T O T Y P E S O F E X P O R T E D F U N C T I O N S *---------------------------------------------------------------------------------------- */ - /*---------------------------------------------------------------------------------------- * E X P O R T E D F U N C T I O N S *---------------------------------------------------------------------------------------- diff --git a/src/vendorcode/amd/agesa/f14/Proc/CPU/Feature/cpuSrat.c b/src/vendorcode/amd/agesa/f14/Proc/CPU/Feature/cpuSrat.c index e3ba90244a..1fc2b88172 100644 --- a/src/vendorcode/amd/agesa/f14/Proc/CPU/Feature/cpuSrat.c +++ b/src/vendorcode/amd/agesa/f14/Proc/CPU/Feature/cpuSrat.c @@ -81,14 +81,14 @@ extern OPTION_SRAT_CONFIGURATION OptionSratConfiguration; // global user config */ STATIC CPU_SRAT_HEADER ROMDATA CpuSratHdrStruct = { - 'S','R','A','T', + {'S','R','A','T'}, 0, 2, 0, - 'A','M','D',' ',' ',' ', - 'A','G','E','S','A',' ',' ',' ', + {'A','M','D',' ',' ',' '}, + {'A','G','E','S','A',' ',' ',' '}, 1, - 'A','M','D',' ', + {'A','M','D',' '}, 1, 1, {0, 0, 0, 0, 0, 0, 0, 0} @@ -98,6 +98,18 @@ STATIC CPU_SRAT_HEADER ROMDATA CpuSratHdrStruct = * P R O T O T Y P E S O F L O C A L F U N C T I O N S *---------------------------------------------------------------------------------------- */ +AGESA_STATUS +GetAcpiSratStub ( + IN OUT AMD_CONFIG_PARAMS *StdHeader, + IN OUT VOID **SratPtr + ); + +AGESA_STATUS +GetAcpiSratMain ( + IN OUT AMD_CONFIG_PARAMS *StdHeader, + IN OUT VOID **SratPtr + ); + UINT8 STATIC *MakeApicEntry ( diff --git a/src/vendorcode/amd/agesa/f14/Proc/CPU/Feature/cpuSwC1e.c b/src/vendorcode/amd/agesa/f14/Proc/CPU/Feature/cpuSwC1e.c index 9fe66ce872..3be7d06564 100644 --- a/src/vendorcode/amd/agesa/f14/Proc/CPU/Feature/cpuSwC1e.c +++ b/src/vendorcode/amd/agesa/f14/Proc/CPU/Feature/cpuSwC1e.c @@ -121,7 +121,7 @@ IsSwC1eFeatureEnabled ( if (GetNumberOfProcessors (StdHeader) == 1) { GetApMailbox (&ApMailboxes.ApMailInfo.Info, StdHeader); if (ApMailboxes.ApMailInfo.Fields.ModuleType == 0) { - GetFeatureServicesOfCurrentCore (&SwC1eFamilyServiceTable, &SwFamilyServices, StdHeader); + GetFeatureServicesOfCurrentCore (&SwC1eFamilyServiceTable, (const VOID **)&SwFamilyServices, StdHeader); if (SwFamilyServices != NULL) { IsEnabled = SwFamilyServices->IsSwC1eSupported (SwFamilyServices, StdHeader); } @@ -160,7 +160,7 @@ InitializeSwC1eFeature ( IDS_HDT_CONSOLE (CPU_TRACE, " SW C1e is enabled\n"); if (IsWarmReset (StdHeader)) { - GetFeatureServicesOfCurrentCore (&SwC1eFamilyServiceTable, &FamilyServices, StdHeader); + GetFeatureServicesOfCurrentCore (&SwC1eFamilyServiceTable, (const VOID **)&FamilyServices, StdHeader); AgesaStatus = FamilyServices->InitializeSwC1e (FamilyServices, EntryPoint, PlatformConfig, StdHeader); } diff --git a/src/vendorcode/amd/agesa/f14/Proc/CPU/Feature/cpuWhea.c b/src/vendorcode/amd/agesa/f14/Proc/CPU/Feature/cpuWhea.c index ca2bd24db4..76a68792ec 100644 --- a/src/vendorcode/amd/agesa/f14/Proc/CPU/Feature/cpuWhea.c +++ b/src/vendorcode/amd/agesa/f14/Proc/CPU/Feature/cpuWhea.c @@ -85,6 +85,20 @@ CreateHestBank ( IN AMD_WHEA_INIT_DATA *WheaInitDataPtr ); +AGESA_STATUS +GetAcpiWheaStub ( + IN OUT AMD_CONFIG_PARAMS *StdHeader, + IN OUT VOID **WheaMcePtr, + IN OUT VOID **WheaCmcPtr + ); + +AGESA_STATUS +GetAcpiWheaMain ( + IN OUT AMD_CONFIG_PARAMS *StdHeader, + IN OUT VOID **WheaMcePtr, + IN OUT VOID **WheaCmcPtr + ); + /*---------------------------------------------------------------------------------------- * E X P O R T E D F U N C T I O N S *---------------------------------------------------------------------------------------- @@ -178,8 +192,8 @@ GetAcpiWheaMain ( return AGESA_ERROR; } - GetCpuServicesOfCurrentCore (&FamilySpecificServices, StdHeader); - FamilySpecificServices->GetWheaInitData (FamilySpecificServices, &WheaInitDataPtr, &Entries, StdHeader); + GetCpuServicesOfCurrentCore ((const CPU_SPECIFIC_SERVICES **)&FamilySpecificServices, StdHeader); + FamilySpecificServices->GetWheaInitData (FamilySpecificServices, (const VOID **)&WheaInitDataPtr, &Entries, StdHeader); ASSERT (WheaInitDataPtr->HestBankNum <= BankNum); diff --git a/src/vendorcode/amd/agesa/f14/Proc/CPU/S3.c b/src/vendorcode/amd/agesa/f14/Proc/CPU/S3.c index 5f2ef341a4..f3825dd928 100644 --- a/src/vendorcode/amd/agesa/f14/Proc/CPU/S3.c +++ b/src/vendorcode/amd/agesa/f14/Proc/CPU/S3.c @@ -214,11 +214,11 @@ SaveDeviceContext ( { DEVICE_DESCRIPTORS Device; UINT16 i; - UINT64 StartAddress; - UINT64 EndAddress; + VOID *StartAddress; + VOID *EndAddress; VOID *OrMask; - StartAddress = (UINT64) DeviceList; + StartAddress = DeviceList; Device.CommonDeviceHeader = (DEVICE_DESCRIPTOR *) &DeviceList[1]; OrMask = (UINT8 *) DeviceList + DeviceList->RelativeOrMaskOffset; @@ -282,7 +282,7 @@ SaveDeviceContext ( break; } } - EndAddress = (UINT64) OrMask; + EndAddress = (VOID *) OrMask; *ActualBufferSize = (UINT32) (EndAddress - StartAddress); } diff --git a/src/vendorcode/amd/agesa/f14/Proc/CPU/Table.c b/src/vendorcode/amd/agesa/f14/Proc/CPU/Table.c index 1ceaed06d0..26af05a5ef 100644 --- a/src/vendorcode/amd/agesa/f14/Proc/CPU/Table.c +++ b/src/vendorcode/amd/agesa/f14/Proc/CPU/Table.c @@ -83,6 +83,13 @@ extern OPTION_MULTISOCKET_CONFIGURATION OptionMultiSocketConfiguration; *---------------------------------------------------------------------------------------- */ +VOID +SetRegistersFromTablesAtEarly ( + IN CPU_SPECIFIC_SERVICES *FamilyServices, + IN AMD_CPU_EARLY_PARAMS *EarlyParams, + IN AMD_CONFIG_PARAMS *StdHeader + ); + /*---------------------------------------------------------------------------------------- * E X P O R T E D F U N C T I O N S *---------------------------------------------------------------------------------------- @@ -123,7 +130,7 @@ STATIC TABLE_ENTRY_FIELDS *Entries; ASSERT ((FamilySpecificServices != NULL) && (StdHeader != NULL)); - ASSERT (Selector < TableEntryTypeMax); + ASSERT (Selector < TableCoreSelectorMax); NextTable = *RegisterTableHandle; if (NextTable == NULL) { @@ -239,7 +246,7 @@ GetPerformanceFeatures ( } // Get some family, model specific performance type info. - GetCpuServicesOfCurrentCore (&FamilySpecificServices, StdHeader); + GetCpuServicesOfCurrentCore ((const CPU_SPECIFIC_SERVICES **)&FamilySpecificServices, StdHeader); ASSERT (FamilySpecificServices != NULL); // Is the Northbridge P-State feature enabled @@ -400,7 +407,7 @@ SetRegisterForHtPhyEntry ( IdentifyCore (StdHeader, &MySocket, &MyModule, &Ignored, &IgnoredStatus); GetPciAddress (StdHeader, MySocket, MyModule, &CapabilitySet, &IgnoredStatus); GetLogicalIdOfCurrentCore (&CpuFamilyRevision, StdHeader); - GetCpuServicesFromLogicalId (&CpuFamilyRevision, &FamilySpecificServices, StdHeader); + GetCpuServicesFromLogicalId (&CpuFamilyRevision, (const CPU_SPECIFIC_SERVICES **)&FamilySpecificServices, StdHeader); Link = 0; while (FamilySpecificServices->NextLinkHasHtPhyFeats ( FamilySpecificServices, @@ -461,7 +468,7 @@ SetRegisterForHtPhyRangeEntry ( IdentifyCore (StdHeader, &MySocket, &MyModule, &Ignored, &IgnoredStatus); GetPciAddress (StdHeader, MySocket, MyModule, &CapabilitySet, &IgnoredStatus); GetLogicalIdOfCurrentCore (&CpuFamilyRevision, StdHeader); - GetCpuServicesFromLogicalId (&CpuFamilyRevision, &FamilySpecificServices, StdHeader); + GetCpuServicesFromLogicalId (&CpuFamilyRevision, (const CPU_SPECIFIC_SERVICES **)&FamilySpecificServices, StdHeader); Link = 0; while (FamilySpecificServices->NextLinkHasHtPhyFeats ( FamilySpecificServices, @@ -646,7 +653,7 @@ SetRegisterForDeemphasisEntry ( IdentifyCore (StdHeader, &MySocket, &MyModule, &Ignored, &IgnoredStatus); GetPciAddress (StdHeader, MySocket, MyModule, &CapabilitySet, &IgnoredStatus); GetLogicalIdOfCurrentCore (&CpuFamilyRevision, StdHeader); - GetCpuServicesFromLogicalId (&CpuFamilyRevision, &FamilySpecificServices, StdHeader); + GetCpuServicesFromLogicalId (&CpuFamilyRevision, (const CPU_SPECIFIC_SERVICES **)&FamilySpecificServices, StdHeader); Link = 0; while (FamilySpecificServices->NextLinkHasHtPhyFeats ( FamilySpecificServices, @@ -726,7 +733,7 @@ SetRegisterForHtPhyFreqEntry ( IdentifyCore (StdHeader, &MySocket, &MyModule, &Ignored, &IgnoredStatus); GetPciAddress (StdHeader, MySocket, MyModule, &CapabilitySet, &IgnoredStatus); GetLogicalIdOfCurrentCore (&CpuFamilyRevision, StdHeader); - GetCpuServicesFromLogicalId (&CpuFamilyRevision, &FamilySpecificServices, StdHeader); + GetCpuServicesFromLogicalId (&CpuFamilyRevision, (const CPU_SPECIFIC_SERVICES **)&FamilySpecificServices, StdHeader); Link = 0; while (FamilySpecificServices->NextLinkHasHtPhyFeats ( FamilySpecificServices, @@ -903,7 +910,7 @@ SetRegisterForHtHostEntry ( IdentifyCore (StdHeader, &MySocket, &MyModule, &Ignored, &IgnoredStatus); GetPciAddress (StdHeader, MySocket, MyModule, &CapabilitySet, &IgnoredStatus); GetLogicalIdOfCurrentCore (&CpuFamilyRevision, StdHeader); - GetCpuServicesFromLogicalId (&CpuFamilyRevision, &FamilySpecificServices, StdHeader); + GetCpuServicesFromLogicalId (&CpuFamilyRevision, (const CPU_SPECIFIC_SERVICES **)&FamilySpecificServices, StdHeader); Link = 0; while (FamilySpecificServices->GetNextHtLinkFeatures (FamilySpecificServices, &Link, &CapabilitySet, &HtHostFeats, StdHeader)) { if (DoesEntryTypeSpecificInfoMatch (HtHostFeats.HtHostValue, Entry->HtHostEntry.TypeFeats.HtHostValue)) { @@ -1008,7 +1015,7 @@ SetRegisterForHtLinkTokenEntry ( IdentifyCore (StdHeader, &MySocket, &MyModule, &Ignored, &IgnoredStatus); GetPciAddress (StdHeader, MySocket, MyModule, &CapabilitySet, &IgnoredStatus); GetLogicalIdOfCurrentCore (&CpuFamilyRevision, StdHeader); - GetCpuServicesFromLogicalId (&CpuFamilyRevision, &FamilySpecificServices, StdHeader); + GetCpuServicesFromLogicalId (&CpuFamilyRevision, (const CPU_SPECIFIC_SERVICES **)&FamilySpecificServices, StdHeader); // Check if the actual processor count and SystemDegree are in either range. ProcessorCount = GetNumberOfProcessors (StdHeader); @@ -1259,7 +1266,7 @@ SetRegisterForHtFeaturePciEntry ( IdentifyCore (StdHeader, &MySocket, &MyModule, &Ignored, &IgnoredStatus); GetPciAddress (StdHeader, MySocket, MyModule, &CapabilitySet, &IgnoredStatus); GetLogicalIdOfCurrentCore (&CpuFamilyRevision, StdHeader); - GetCpuServicesFromLogicalId (&CpuFamilyRevision, &FamilySpecificServices, StdHeader); + GetCpuServicesFromLogicalId (&CpuFamilyRevision, (const CPU_SPECIFIC_SERVICES **)&FamilySpecificServices, StdHeader); ASSERT ((Entry->HtFeatPciEntry.PackageType.PackageTypeValue & ~(PACKAGE_TYPE_ALL)) == 0); @@ -1323,7 +1330,7 @@ SetRegisterForHtLinkPciEntry ( IdentifyCore (StdHeader, &MySocket, &MyModule, &Ignored, &IgnoredStatus); GetPciAddress (StdHeader, MySocket, MyModule, &CapabilitySet, &IgnoredStatus); GetLogicalIdOfCurrentCore (&CpuFamilyRevision, StdHeader); - GetCpuServicesFromLogicalId (&CpuFamilyRevision, &FamilySpecificServices, StdHeader); + GetCpuServicesFromLogicalId (&CpuFamilyRevision, (const CPU_SPECIFIC_SERVICES **)&FamilySpecificServices, StdHeader); Link = 0; while (FamilySpecificServices->GetNextHtLinkFeatures (FamilySpecificServices, &Link, &CapabilitySet, &HtHostFeats, StdHeader)) { @@ -1424,7 +1431,7 @@ GetPlatformFeatures ( // // Get some specific platform type info, VC...etc. // - GetCpuServicesOfCurrentCore (&FamilySpecificServices, StdHeader); + GetCpuServicesOfCurrentCore ((const CPU_SPECIFIC_SERVICES **)&FamilySpecificServices, StdHeader); ASSERT (FamilySpecificServices != NULL); FamilySpecificServices->GetPlatformTypeSpecificInfo (FamilySpecificServices, Features, StdHeader); @@ -1601,7 +1608,7 @@ SetRegistersFromTables ( PlatformFeatures.PlatformValue = 0; GetLogicalIdOfCurrentCore (&CpuLogicalId, StdHeader); GetPlatformFeatures (&PlatformFeatures, PlatformConfig, StdHeader); - GetCpuServicesFromLogicalId (&CpuLogicalId, &FamilySpecificServices, StdHeader); + GetCpuServicesFromLogicalId (&CpuLogicalId, (const CPU_SPECIFIC_SERVICES **)&FamilySpecificServices, StdHeader); // Build a non-sparse table of implementer methods, so we don't have to keep searching. // It is a bug to not include a descriptor for a type that is in the table (but the diff --git a/src/vendorcode/amd/agesa/f14/Proc/CPU/cpuApicUtilities.c b/src/vendorcode/amd/agesa/f14/Proc/CPU/cpuApicUtilities.c index 947696980b..40c395d6dc 100644 --- a/src/vendorcode/amd/agesa/f14/Proc/CPU/cpuApicUtilities.c +++ b/src/vendorcode/amd/agesa/f14/Proc/CPU/cpuApicUtilities.c @@ -9,7 +9,7 @@ * @xrefitem bom "File Content Label" "Release Content" * @e project: AGESA * @e sub-project: CPU - * @e \$Revision: 35136 $ @e \$Date: 2010-07-16 11:29:48 +0800 (Fri, 16 Jul 2010) $ + * @e \$Revision: 44325 $ @e \$Date: 2010-12-22 03:29:53 -0700 (Wed, 22 Dec 2010) $ * */ /* @@ -98,6 +98,23 @@ typedef VOID F_CPU_AMD_NMI_HANDLER ( ); typedef F_CPU_AMD_NMI_HANDLER *PF_CPU_AMD_NMI_HANDLER; +/// Interrupt Descriptor Table entry +typedef struct { + UINT16 OffsetLo; ///< Lower 16 bits of the interrupt handler routine's offset + UINT16 Selector; ///< Interrupt handler routine's selector + UINT8 Rsvd; ///< Reserved + UINT8 Flags; ///< Interrupt flags + UINT16 OffsetHi; ///< Upper 16 bits of the interrupt handler routine's offset + UINT32 Offset64; ///< High order 32 bits of the handler's offset needed when in 64 bit mode + UINT32 Rsvd64; ///< Reserved +} IDT_DESCRIPTOR; + +/// Structure needed to load the IDTR using the lidt instruction +//typedef struct { +// UINT16 Limit; ///< Interrupt Descriptor Table size +// UINT64 Base; ///< Interrupt Descriptor Table base address +//} IDT_BASE_LIMIT; + /*---------------------------------------------------------------------------------------- * P R O T O T Y P E S O F L O C A L F U N C T I O N S *---------------------------------------------------------------------------------------- @@ -180,6 +197,19 @@ PerformFinalHalt ( IN AMD_CONFIG_PARAMS *StdHeader ); +VOID +LocalApicInitialization ( + IN AMD_CPU_EARLY_PARAMS *CpuEarlyParamsPtr, + IN AMD_CONFIG_PARAMS *StdHeader + ); + +VOID +LocalApicInitializationAtEarly ( + IN CPU_SPECIFIC_SERVICES *FamilyServices, + IN AMD_CPU_EARLY_PARAMS *EarlyParams, + IN AMD_CONFIG_PARAMS *StdHeader + ); + /*---------------------------------------------------------------------------------------- * E X P O R T E D F U N C T I O N S *---------------------------------------------------------------------------------------- @@ -830,9 +860,9 @@ ApUtilSetupIdtForHlt ( DescSize = 8; } - HandlerOffset = (UINT64) NmiHandler; - NmiIdtDescPtr->OffsetLo = (UINT16) HandlerOffset & 0xFFFF; - NmiIdtDescPtr->OffsetHi = (UINT16) (HandlerOffset >> 16); + HandlerOffset = (UINT64)&NmiHandler; + NmiIdtDescPtr->OffsetLo = (UINT16) (HandlerOffset & 0xFFFF); + NmiIdtDescPtr->OffsetHi = (UINT16) ((HandlerOffset >> 16) & 0xFFFF); GetCsSelector (&NmiIdtDescPtr->Selector, StdHeader); NmiIdtDescPtr->Flags = SEG_DESC_PRESENT | SEG_DESC_TYPE_INT32; NmiIdtDescPtr->Rsvd = 0; @@ -1109,7 +1139,7 @@ RelinquishControlOfAllAPs ( { UINT32 BscSocket; UINT32 Ignored; - UINT32 BscCore; + UINT32 BscCoreNum; UINT32 Core; UINT32 Socket; UINT32 NumberOfSockets; @@ -1122,13 +1152,13 @@ RelinquishControlOfAllAPs ( TaskPtr.DataTransfer.DataSizeInDwords = 0; TaskPtr.ExeFlags = WAIT_FOR_CORE; - IdentifyCore (StdHeader, &BscSocket, &Ignored, &BscCore, &IgnoredSts); + IdentifyCore (StdHeader, &BscSocket, &Ignored, &BscCoreNum, &IgnoredSts); NumberOfSockets = GetPlatformNumberOfSockets (); for (Socket = 0; Socket < NumberOfSockets; Socket++) { if (GetActiveCoresInGivenSocket (Socket, &Core, StdHeader)) { while (Core-- > 0) { - if ((Socket != BscSocket) || (Core != BscCore)) { + if ((Socket != BscSocket) || (Core != BscCoreNum)) { ApUtilRunCodeOnSocketCore ((UINT8) Socket, (UINT8) Core, &TaskPtr, StdHeader); } } @@ -1162,7 +1192,7 @@ PerformFinalHalt ( UINT32 CacheEnDis; CPU_SPECIFIC_SERVICES *FamilyServices; - GetCpuServicesOfCurrentCore (&FamilyServices, StdHeader); + GetCpuServicesOfCurrentCore ((const CPU_SPECIFIC_SERVICES **)&FamilyServices, StdHeader); ASSERT (FamilyServices != NULL); // CacheEnDis is a family specific flag, that lets the code to decide whether to // keep the cache control bits set or cleared. diff --git a/src/vendorcode/amd/agesa/f14/Proc/CPU/cpuBist.c b/src/vendorcode/amd/agesa/f14/Proc/CPU/cpuBist.c index dbdd4b93c7..0d74628897 100644 --- a/src/vendorcode/amd/agesa/f14/Proc/CPU/cpuBist.c +++ b/src/vendorcode/amd/agesa/f14/Proc/CPU/cpuBist.c @@ -96,7 +96,7 @@ CheckBistStatus ( UINT32 Socket; UINT32 Core; UINT32 BscSocket; - UINT32 BscCore; + UINT32 BscCoreNum; UINT32 NumberOfSockets; UINT32 NumberOfCores; UINT32 Ignored; @@ -111,8 +111,8 @@ CheckBistStatus ( AgesaStatus = AGESA_SUCCESS; - // Get the BscSocket, BscCore and NumberOfSockets in the system - IdentifyCore (StdHeader, &BscSocket, &Ignored, &BscCore, &IgnoredSts); + // Get the BscSocket, BscCoreNum and NumberOfSockets in the system + IdentifyCore (StdHeader, &BscSocket, &Ignored, &BscCoreNum, &IgnoredSts); NumberOfSockets = GetPlatformNumberOfSockets (); // Setup TaskPtr struct to execute routine on APs @@ -123,7 +123,7 @@ CheckBistStatus ( for (Socket = 0; Socket < NumberOfSockets; Socket++) { if (GetActiveCoresInGivenSocket (Socket, &NumberOfCores, StdHeader)) { for (Core = 0; Core < NumberOfCores; Core++) { - if ((Socket != BscSocket) || (Core != BscCore)) { + if ((Socket != BscSocket) || (Core != BscCoreNum)) { ReturnCode = ApUtilRunCodeOnSocketCore ((UINT8)Socket, (UINT8)Core, &TaskPtr, StdHeader); } else { ReturnCode = TaskPtr.FuncAddress.PfApTaskO (StdHeader); diff --git a/src/vendorcode/amd/agesa/f14/Proc/CPU/cpuBrandId.c b/src/vendorcode/amd/agesa/f14/Proc/CPU/cpuBrandId.c index 0db12afdf0..c41e57d3e6 100644 --- a/src/vendorcode/amd/agesa/f14/Proc/CPU/cpuBrandId.c +++ b/src/vendorcode/amd/agesa/f14/Proc/CPU/cpuBrandId.c @@ -85,6 +85,13 @@ CONST AMD_CPU_BRAND ROMDATA Dflt_Str2 = {0, 0, 0, SOCKET_IGNORE, DR_NO_STRING, D *---------------------------------------------------------------------------------------- */ +VOID +SetBrandIdRegistersAtEarly ( + IN CPU_SPECIFIC_SERVICES *FamilyServices, + IN AMD_CPU_EARLY_PARAMS *EarlyParams, + IN AMD_CONFIG_PARAMS *StdHeader + ); + /*---------------------------------------------------------------------------------------- * E X P O R T E D F U N C T I O N S *---------------------------------------------------------------------------------------- @@ -133,7 +140,7 @@ SetBrandIdRegisters ( SocketTablePtr = NULL; SocketTableEntry = NULL; - GetCpuServicesOfCurrentCore (&FamilySpecificServices, StdHeader); + GetCpuServicesOfCurrentCore ((const CPU_SPECIFIC_SERVICES **)&FamilySpecificServices, StdHeader); // Step1: Allocate 48 bytes from Heap space AllocHeapParams.RequestedBufferSize = CPU_BRAND_ID_LENGTH; AllocHeapParams.BufferHandle = AMD_BRAND_ID_BUFFER_HANDLE; @@ -180,7 +187,7 @@ SetBrandIdRegisters ( } // Step5: Search for String1 (there can be only 1) - FamilySpecificServices->GetBrandString1 (FamilySpecificServices, (VOID **) &SocketTableEntry, &TableEntryCount, StdHeader); + FamilySpecificServices->GetBrandString1 (FamilySpecificServices, (const VOID **) &SocketTableEntry, &TableEntryCount, StdHeader); SocketTableEntry1 = (CPU_BRAND_TABLE **) SocketTableEntry; for (TableEntryIndex = 0; ((TableEntryIndex < TableEntryCount) && (SuffixStatus == 0)); TableEntryIndex++, SocketTableEntry1++) { @@ -242,7 +249,7 @@ SetBrandIdRegisters ( // Step9: Search for String2 SuffixStatus = 0; - FamilySpecificServices->GetBrandString2 (FamilySpecificServices, (VOID **) &SocketTableEntry, &TableEntryCount, StdHeader); + FamilySpecificServices->GetBrandString2 (FamilySpecificServices, (const VOID **) &SocketTableEntry, &TableEntryCount, StdHeader); SocketTableEntry1 = (CPU_BRAND_TABLE **) SocketTableEntry; for (TableEntryIndex = 0; ((TableEntryIndex < TableEntryCount) && (SuffixStatus == 0)); TableEntryIndex++, SocketTableEntry1++) { diff --git a/src/vendorcode/amd/agesa/f14/Proc/CPU/cpuEarlyInit.c b/src/vendorcode/amd/agesa/f14/Proc/CPU/cpuEarlyInit.c index d5e27f52e1..516cebfe6f 100644 --- a/src/vendorcode/amd/agesa/f14/Proc/CPU/cpuEarlyInit.c +++ b/src/vendorcode/amd/agesa/f14/Proc/CPU/cpuEarlyInit.c @@ -88,11 +88,31 @@ GetPerformEarlyFlag ( IN AMD_CONFIG_PARAMS *StdHeader ); +VOID +McaInitialization ( + IN AMD_CONFIG_PARAMS *StdHeader + ); + +VOID +McaInitializationAtEarly ( + IN CPU_SPECIFIC_SERVICES *FamilyServices, + IN AMD_CPU_EARLY_PARAMS *EarlyParams, + IN AMD_CONFIG_PARAMS *StdHeader + ); + /*---------------------------------------------------------------------------------------- * E X P O R T E D F U N C T I O N S *---------------------------------------------------------------------------------------- */ /*------------------------------------------------------------------------------------*/ + +VOID +AmdCpuEarlyInitializer ( + IN AMD_CONFIG_PARAMS *StdHeader, + IN PLATFORM_CONFIGURATION *PlatformConfig, + IN OUT AMD_CPU_EARLY_PARAMS *CpuEarlyParamsPtr + ); + /** * Initializer routine that will be invoked by AmdCpuEarly to initialize the input * structure for the Cpu Init @ Early routine. @@ -172,9 +192,9 @@ AmdCpuEarly ( IDS_OPTION_HOOK (IDS_CPU_Early_Override, &CpuEarlyParams, StdHeader); - GetCpuServicesOfCurrentCore (&FamilySpecificServices, StdHeader); + GetCpuServicesOfCurrentCore ((const CPU_SPECIFIC_SERVICES **)&FamilySpecificServices, StdHeader); EarlyTableOnCore = NULL; - FamilySpecificServices->GetEarlyInitOnCoreTable (FamilySpecificServices, &EarlyTableOnCore, &CpuEarlyParams, StdHeader); + FamilySpecificServices->GetEarlyInitOnCoreTable (FamilySpecificServices, (const S_PERFORM_EARLY_INIT_ON_CORE **) &EarlyTableOnCore, &CpuEarlyParams, StdHeader); if (EarlyTableOnCore != NULL) { GetPerformEarlyFlag (&CurrentPerformEarlyFlag, StdHeader); for (i = 0; EarlyTableOnCore[i].PerformEarlyInitOnCore != NULL; i++) { @@ -194,7 +214,7 @@ AmdCpuEarly ( // Even though the bsc does not need to send itself a heap index, this sequence performs other important initialization. // Use '0' as a dummy heap index value. GetSocketModuleOfNode (0, &SocketNum, &ModuleNum, StdHeader); - GetCpuServicesOfSocket (SocketNum, &FamilySpecificServices, StdHeader); + GetCpuServicesOfSocket (SocketNum, (const CPU_SPECIFIC_SERVICES **)&FamilySpecificServices, StdHeader); FamilySpecificServices->SetApCoreNumber (FamilySpecificServices, SocketNum, ModuleNum, 0, StdHeader); FamilySpecificServices->TransferApCoreNumber (FamilySpecificServices, StdHeader); @@ -205,7 +225,7 @@ AmdCpuEarly ( ApHeapIndex = 1; while (NodeNum < MAX_NODES && GetSocketModuleOfNode (NodeNum, &SocketNum, &ModuleNum, StdHeader)) { - GetCpuServicesOfSocket (SocketNum, &FamilySpecificServices, StdHeader); + GetCpuServicesOfSocket (SocketNum, (const CPU_SPECIFIC_SERVICES **)&FamilySpecificServices, StdHeader); GetGivenModuleCoreRange (SocketNum, ModuleNum, &PrimaryCore, &HighCore, StdHeader); if (NodeNum == 0) { StartCore = (UINT8) PrimaryCore + 1; diff --git a/src/vendorcode/amd/agesa/f14/Proc/CPU/cpuFamilyTranslation.c b/src/vendorcode/amd/agesa/f14/Proc/CPU/cpuFamilyTranslation.c index 7882c58e20..25be191a02 100644 --- a/src/vendorcode/amd/agesa/f14/Proc/CPU/cpuFamilyTranslation.c +++ b/src/vendorcode/amd/agesa/f14/Proc/CPU/cpuFamilyTranslation.c @@ -249,7 +249,7 @@ GetLogicalIdFromCpuid ( NumberOfLogicalSubFamilies = ImageSupportedId[i].Elements; SubFamilyIdPtr = ImageSupportedId[i].SubFamilyIdTable; for (j = 0; j < NumberOfLogicalSubFamilies && IdNotFound; j++) { - SubFamilyIdPtr[j] (&CpuLogicalIdAndRevPtr, &LogicalIdEntries, &LogicalFamily, StdHeader); + SubFamilyIdPtr[j] ((const CPU_LOGICAL_ID_XLAT **)&CpuLogicalIdAndRevPtr, &LogicalIdEntries, &LogicalFamily, StdHeader); ASSERT (CpuLogicalIdAndRevPtr != NULL); for (k = 0; k < LogicalIdEntries; k++) { if (CpuLogicalIdAndRevPtr[k].RawId == CpuModelAndExtendedModel) { @@ -284,7 +284,7 @@ GetCpuServicesOfSocket ( { GetFeatureServicesOfSocket (&CpuSupportedFamiliesTable, Socket, - FunctionTable, + (const VOID **)FunctionTable, StdHeader); if (*FunctionTable == NULL) { *FunctionTable = &cpuNullServices; @@ -334,7 +334,7 @@ GetCpuServicesOfCurrentCore ( ) { GetFeatureServicesOfCurrentCore (&CpuSupportedFamiliesTable, - FunctionTable, + (const VOID **)FunctionTable, StdHeader); if (*FunctionTable == NULL) { *FunctionTable = &cpuNullServices; @@ -386,7 +386,7 @@ GetCpuServicesFromLogicalId ( { GetFeatureServicesFromLogicalId (&CpuSupportedFamiliesTable, LogicalId, - FunctionTable, + (const VOID **)FunctionTable, StdHeader); if (*FunctionTable == NULL) { *FunctionTable = &cpuNullServices; diff --git a/src/vendorcode/amd/agesa/f14/Proc/CPU/cpuGeneralServices.c b/src/vendorcode/amd/agesa/f14/Proc/CPU/cpuGeneralServices.c index 29309ce00f..473c8db80d 100644 --- a/src/vendorcode/amd/agesa/f14/Proc/CPU/cpuGeneralServices.c +++ b/src/vendorcode/amd/agesa/f14/Proc/CPU/cpuGeneralServices.c @@ -577,7 +577,7 @@ ModifyCurrentSocketPci ( UINT32 Socket; UINT32 Module; UINT32 Core; - UINT32 PciRegister; + UINT32 PciReg; AGESA_STATUS AgesaStatus; PCI_ADDR Reg; @@ -587,10 +587,10 @@ ModifyCurrentSocketPci ( if (GetPciAddress (StdHeader, Socket, Module, &Reg, &AgesaStatus)) { Reg.Address.Function = PciAddress->Address.Function; Reg.Address.Register = PciAddress->Address.Register; - LibAmdPciRead (AccessWidth32, Reg, &PciRegister, StdHeader); - PciRegister &= Mask; - PciRegister |= Data; - LibAmdPciWrite (AccessWidth32, Reg, &PciRegister, StdHeader); + LibAmdPciRead (AccessWidth32, Reg, &PciReg, StdHeader); + PciReg &= Mask; + PciReg |= Data; + LibAmdPciWrite (AccessWidth32, Reg, &PciReg, StdHeader); } } } @@ -802,7 +802,7 @@ GetCurrentCore ( CORE_ID_POSITION InitApicIdCpuIdLo; CPU_SPECIFIC_SERVICES *FamilyServices; - GetCpuServicesOfCurrentCore (&FamilyServices, StdHeader); + GetCpuServicesOfCurrentCore ((const CPU_SPECIFIC_SERVICES **)&FamilyServices, StdHeader); ASSERT (FamilyServices != NULL); // Read CPUID ebx[31:24] to get initial APICID @@ -951,7 +951,7 @@ GetApMailbox ( *ApMailboxInfo = ((AP_MAILBOXES *) LocalApMailboxCache.BufferPtr)->ApMailInfo.Info; } else if (!IamBsp) { // If this is an AP, the hardware register should be good. - GetCpuServicesOfCurrentCore (&FamilyServices, StdHeader); + GetCpuServicesOfCurrentCore ((const CPU_SPECIFIC_SERVICES **)&FamilyServices, StdHeader); ASSERT (FamilyServices != NULL); FamilyServices->GetApMailboxFromHardware (FamilyServices, &ApMailboxes, StdHeader); *ApMailboxInfo = ApMailboxes.ApMailInfo.Info; @@ -980,7 +980,7 @@ CacheApMailbox ( AP_MAILBOXES ApMailboxes; CPU_SPECIFIC_SERVICES *FamilyServices; - GetCpuServicesOfCurrentCore (&FamilyServices, StdHeader); + GetCpuServicesOfCurrentCore ((const CPU_SPECIFIC_SERVICES **)&FamilyServices, StdHeader); ASSERT (FamilyServices != NULL); // Get mailbox from hardware. @@ -1046,7 +1046,7 @@ WaitMicroseconds ( CPU_SPECIFIC_SERVICES *FamilySpecificServices; LibAmdMsrRead (TSC, &InitialTsc, StdHeader); - GetCpuServicesOfCurrentCore (&FamilySpecificServices, StdHeader); + GetCpuServicesOfCurrentCore ((const CPU_SPECIFIC_SERVICES **)&FamilySpecificServices, StdHeader); FamilySpecificServices->GetTscRate (FamilySpecificServices, &TscRateInMhz, StdHeader); NumberOfTicks = Microseconds * TscRateInMhz; do { @@ -1116,7 +1116,7 @@ GetComputeUnitMapping ( Result = MaxComputeUnitMapping; IdentifyCore (StdHeader, &Socket, &Module, &CurrentCore, &IgnoredSts); - GetCpuServicesOfCurrentCore (&FamilyServices, StdHeader); + GetCpuServicesOfCurrentCore ((const CPU_SPECIFIC_SERVICES **)&FamilyServices, StdHeader); ASSERT (FamilyServices != NULL); // Get data block from heap @@ -1264,14 +1264,14 @@ InitializePciMmio ( ) { UINT8 EncodedSize; - UINT64 MsrRegister; + UINT64 MsrReg; // Make sure that Standard header is valid ASSERT (StdHeader != NULL); if ((UserOptions.CfgPciMmioAddress != 0) && (UserOptions.CfgPciMmioSize != 0)) { EncodedSize = LibAmdBitScanForward (UserOptions.CfgPciMmioSize); - MsrRegister = ((UserOptions.CfgPciMmioAddress | BIT0) | (EncodedSize << 2)); - LibAmdMsrWrite (MSR_MMIO_Cfg_Base, &MsrRegister, StdHeader); + MsrReg = ((UserOptions.CfgPciMmioAddress | BIT0) | (EncodedSize << 2)); + LibAmdMsrWrite (MSR_MMIO_Cfg_Base, &MsrReg, StdHeader); } } diff --git a/src/vendorcode/amd/agesa/f14/Proc/CPU/cpuInitEarlyTable.c b/src/vendorcode/amd/agesa/f14/Proc/CPU/cpuInitEarlyTable.c index a7844aa084..dbc7f2c949 100644 --- a/src/vendorcode/amd/agesa/f14/Proc/CPU/cpuInitEarlyTable.c +++ b/src/vendorcode/amd/agesa/f14/Proc/CPU/cpuInitEarlyTable.c @@ -74,6 +74,14 @@ RDATA_GROUP (G1_PEICC) *---------------------------------------------------------------------------------------- */ +VOID +GetCommonEarlyInitOnCoreTable ( + IN CPU_SPECIFIC_SERVICES *FamilyServices, + OUT CONST S_PERFORM_EARLY_INIT_ON_CORE **Table, + IN AMD_CPU_EARLY_PARAMS *EarlyParams, + IN AMD_CONFIG_PARAMS *StdHeader + ); + /*---------------------------------------------------------------------------------------- * E X P O R T E D F U N C T I O N S *---------------------------------------------------------------------------------------- diff --git a/src/vendorcode/amd/agesa/f14/Proc/CPU/cpuLateInit.c b/src/vendorcode/amd/agesa/f14/Proc/CPU/cpuLateInit.c index 3915e49248..bc0c975e8d 100644 --- a/src/vendorcode/amd/agesa/f14/Proc/CPU/cpuLateInit.c +++ b/src/vendorcode/amd/agesa/f14/Proc/CPU/cpuLateInit.c @@ -204,7 +204,7 @@ RunLateApTaskOnAllAPs ( UINT8 ApicId; UINT32 BscSocket; UINT32 Ignored; - UINT32 BscCore; + UINT32 BscCoreNum; AGESA_STATUS CalledStatus; AGESA_STATUS IgnoredStatus; AGESA_STATUS AgesaStatus; @@ -213,13 +213,13 @@ RunLateApTaskOnAllAPs ( AgesaStatus = AGESA_SUCCESS; - IdentifyCore (StdHeader, &BscSocket, &Ignored, &BscCore, &IgnoredStatus); + IdentifyCore (StdHeader, &BscSocket, &Ignored, &BscCoreNum, &IgnoredStatus); NumberOfSockets = GetPlatformNumberOfSockets (); for (Socket = 0; Socket < NumberOfSockets; Socket++) { if (GetActiveCoresInGivenSocket (Socket, &NumberOfCores, StdHeader)) { for (Core = 0; Core < NumberOfCores; Core++) { - if ((Socket != BscSocket) || (Core != BscCore)) { + if ((Socket != BscSocket) || (Core != BscCoreNum)) { GetApicId (StdHeader, Socket, Core, &ApicId, &IgnoredStatus); AGESA_TESTPOINT (TpIfBeforeRunApFromAllAps, StdHeader); CalledStatus = AgesaRunFcnOnAp ((UINTN) ApicId, ApParams); diff --git a/src/vendorcode/amd/agesa/f14/Proc/CPU/cpuMicrocodePatch.c b/src/vendorcode/amd/agesa/f14/Proc/CPU/cpuMicrocodePatch.c index c19b10599d..4116a6e053 100644 --- a/src/vendorcode/amd/agesa/f14/Proc/CPU/cpuMicrocodePatch.c +++ b/src/vendorcode/amd/agesa/f14/Proc/CPU/cpuMicrocodePatch.c @@ -109,6 +109,13 @@ GetMicrocodeVersion ( IN OUT AMD_CONFIG_PARAMS *StdHeader ); +VOID +LoadMicrocodePatchAtEarly ( + IN CPU_SPECIFIC_SERVICES *FamilyServices, + IN AMD_CPU_EARLY_PARAMS *EarlyParams, + IN AMD_CONFIG_PARAMS *StdHeader + ); + /*---------------------------------------------------------------------------------------- * E X P O R T E D F U N C T I O N S *---------------------------------------------------------------------------------------- @@ -144,8 +151,8 @@ LoadMicrocodePatch ( if (IsCorePairPrimary (FirstCoreIsComputeUnitPrimary, StdHeader)) { // Get the patch pointer - GetCpuServicesOfCurrentCore (&FamilySpecificServices, StdHeader); - FamilySpecificServices->GetMicroCodePatchesStruct (FamilySpecificServices, (VOID **) &MicrocodePatchPtr, &TotalPatches, StdHeader); + GetCpuServicesOfCurrentCore ((const CPU_SPECIFIC_SERVICES **)&FamilySpecificServices, StdHeader); + FamilySpecificServices->GetMicroCodePatchesStruct (FamilySpecificServices, (const VOID **) &MicrocodePatchPtr, &TotalPatches, StdHeader); IDS_OPTION_HOOK (IDS_UCODE, &TotalPatches, StdHeader); @@ -258,10 +265,10 @@ GetPatchEquivalentId ( // // find the equivalent ID for microcode purpose using the equivalence table // - GetCpuServicesOfCurrentCore (&FamilySpecificServices, StdHeader); + GetCpuServicesOfCurrentCore ((const CPU_SPECIFIC_SERVICES **)&FamilySpecificServices, StdHeader); FamilySpecificServices->GetMicrocodeEquivalenceTable (FamilySpecificServices, - &MicrocodeEquivalenceTable, + (const VOID **) &MicrocodeEquivalenceTable, &EquivalencyEntries, StdHeader); diff --git a/src/vendorcode/amd/agesa/f14/Proc/CPU/cpuPostInit.c b/src/vendorcode/amd/agesa/f14/Proc/CPU/cpuPostInit.c index 0bdd006595..3b607570be 100644 --- a/src/vendorcode/amd/agesa/f14/Proc/CPU/cpuPostInit.c +++ b/src/vendorcode/amd/agesa/f14/Proc/CPU/cpuPostInit.c @@ -86,6 +86,18 @@ SyncVariableMTRR ( IN AMD_CONFIG_PARAMS *StdHeader ); +AGESA_STATUS +GetPstateGatherDataAddressAtPost ( + OUT UINT64 **Ptr, + IN AMD_CONFIG_PARAMS *StdHeader + ); + +VOID +SyncAllApMtrrToBsc ( + IN VOID *MtrrTable, + IN AMD_CONFIG_PARAMS *StdHeader + ); + /*---------------------------------------------------------------------------------------- * E X P O R T E D F U N C T I O N S *---------------------------------------------------------------------------------------- @@ -190,11 +202,11 @@ GetPstateGatherDataAddressAtPost ( IN AMD_CONFIG_PARAMS *StdHeader ) { - UINT64 AddressValue; + VOID *AddressValue; - AddressValue = P_STATE_DATA_GATHER_TEMP_ADDR; + AddressValue = (VOID *)P_STATE_DATA_GATHER_TEMP_ADDR; - *Ptr = (UINT64 *)(AddressValue); + *Ptr = AddressValue; return AGESA_SUCCESS; } @@ -309,7 +321,7 @@ SyncApMsrsToBsc ( UINT16 i; UINT32 BscSocket; UINT32 Ignored; - UINT32 BscCore; + UINT32 BscCoreNum; UINT32 Core; UINT32 Socket; UINT32 NumberOfSockets; @@ -318,7 +330,7 @@ SyncApMsrsToBsc ( ASSERT (IsBsp (StdHeader, &IgnoredSts)); - IdentifyCore (StdHeader, &BscSocket, &Ignored, &BscCore, &IgnoredSts); + IdentifyCore (StdHeader, &BscSocket, &Ignored, &BscCoreNum, &IgnoredSts); NumberOfSockets = GetPlatformNumberOfSockets (); // @@ -337,7 +349,7 @@ SyncApMsrsToBsc ( for (Socket = 0; Socket < NumberOfSockets; Socket++) { if (GetActiveCoresInGivenSocket (Socket, &NumberOfCores, StdHeader)) { for (Core = 0; Core < NumberOfCores; Core++) { - if ((Socket != BscSocket) || (Core != BscCore)) { + if ((Socket != BscSocket) || (Core != BscCoreNum)) { ApUtilRunCodeOnSocketCore ((UINT8) Socket, (UINT8) Core, &TaskPtr, StdHeader); } } @@ -425,7 +437,7 @@ SetTscFreqSel ( FamilyServices = NULL; - GetFeatureServicesOfCurrentCore (&PstateFamilyServiceTable, &FamilyServices, StdHeader); + GetFeatureServicesOfCurrentCore (&PstateFamilyServiceTable, (const VOID **)&FamilyServices, StdHeader); if (FamilyServices != NULL) { FamilyServices->CpuSetTscFreqSel (FamilyServices, StdHeader); } @@ -449,7 +461,7 @@ SetCoresTscFreqSel ( AP_TASK TaskPtr; UINT32 BscSocket; UINT32 Ignored; - UINT32 BscCore; + UINT32 BscCoreNum; UINT32 Core; UINT32 Socket; UINT32 NumberOfSockets; @@ -458,7 +470,7 @@ SetCoresTscFreqSel ( ASSERT (IsBsp (StdHeader, &IgnoredSts)); - IdentifyCore (StdHeader, &BscSocket, &Ignored, &BscCore, &IgnoredSts); + IdentifyCore (StdHeader, &BscSocket, &Ignored, &BscCoreNum, &IgnoredSts); NumberOfSockets = GetPlatformNumberOfSockets (); SetTscFreqSel (StdHeader); @@ -472,7 +484,7 @@ SetCoresTscFreqSel ( for (Socket = 0; Socket < NumberOfSockets; Socket++) { if (GetActiveCoresInGivenSocket (Socket, &NumberOfCores, StdHeader)) { for (Core = 0; Core < NumberOfCores; Core++) { - if ((Socket != BscSocket) || (Core != BscCore)) { + if ((Socket != BscSocket) || (Core != BscCoreNum)) { ApUtilRunCodeOnSocketCore ((UINT8) Socket, (UINT8) Core, &TaskPtr, StdHeader); } } diff --git a/src/vendorcode/amd/agesa/f14/Proc/CPU/cpuPowerMgmt.c b/src/vendorcode/amd/agesa/f14/Proc/CPU/cpuPowerMgmt.c index c5be71543a..2c09af38fc 100644 --- a/src/vendorcode/amd/agesa/f14/Proc/CPU/cpuPowerMgmt.c +++ b/src/vendorcode/amd/agesa/f14/Proc/CPU/cpuPowerMgmt.c @@ -187,8 +187,8 @@ PerformThisPmStep ( SYS_PM_TBL_STEP *FamilyTablePtr; CPU_SPECIFIC_SERVICES *FamilySpecificServices; - GetCpuServicesOfCurrentCore (&FamilySpecificServices, StdHeader); - FamilySpecificServices->GetSysPmTableStruct (FamilySpecificServices, &FamilyTablePtr, &MyNumberOfSteps, StdHeader); + GetCpuServicesOfCurrentCore ((const CPU_SPECIFIC_SERVICES **)&FamilySpecificServices, StdHeader); + FamilySpecificServices->GetSysPmTableStruct (FamilySpecificServices, (const VOID **)&FamilyTablePtr, &MyNumberOfSteps, StdHeader); if (*(UINT8 *)Step < MyNumberOfSteps) { if (FamilyTablePtr[*(UINT8 *)Step].FuncPtr != NULL) { @@ -248,6 +248,6 @@ GoToMemInitPstateCore ( { CPU_SPECIFIC_SERVICES *FamilySpecificServices; - GetCpuServicesOfCurrentCore (&FamilySpecificServices, StdHeader); + GetCpuServicesOfCurrentCore ((const CPU_SPECIFIC_SERVICES **)&FamilySpecificServices, StdHeader); FamilySpecificServices->TransitionPstate (FamilySpecificServices, CpuEarlyParamsPtr->MemInitPState, (BOOLEAN) FALSE, StdHeader); } diff --git a/src/vendorcode/amd/agesa/f14/Proc/CPU/cpuPowerMgmtMultiSocket.c b/src/vendorcode/amd/agesa/f14/Proc/CPU/cpuPowerMgmtMultiSocket.c index 07cfd9d9ee..e975ccb112 100644 --- a/src/vendorcode/amd/agesa/f14/Proc/CPU/cpuPowerMgmtMultiSocket.c +++ b/src/vendorcode/amd/agesa/f14/Proc/CPU/cpuPowerMgmtMultiSocket.c @@ -86,6 +86,11 @@ GetNextEvent ( IN AMD_CONFIG_PARAMS *StdHeader ); +AGESA_STATUS +GetEarlyPmErrorsMulti ( + IN AMD_CONFIG_PARAMS *StdHeader + ); + /*---------------------------------------------------------------------------------------- * E X P O R T E D F U N C T I O N S *---------------------------------------------------------------------------------------- @@ -114,7 +119,7 @@ RunCodeOnAllSystemCore0sMulti ( { UINT32 BscSocket; UINT32 BscModule; - UINT32 BscCore; + UINT32 BscCoreNum; UINT8 Socket; UINT32 NumberOfSockets; AGESA_STATUS DummyStatus; @@ -123,7 +128,7 @@ RunCodeOnAllSystemCore0sMulti ( NumberOfSockets = GetPlatformNumberOfSockets (); - IdentifyCore (StdHeader, &BscSocket, &BscModule, &BscCore, &DummyStatus); + IdentifyCore (StdHeader, &BscSocket, &BscModule, &BscCoreNum, &DummyStatus); for (Socket = 0; Socket < NumberOfSockets; Socket++) { if (Socket != BscSocket) { @@ -166,8 +171,8 @@ GetNumberOfSystemPmStepsPtrMulti ( for (Socket = 0; Socket < NumberOfSockets; Socket++) { if (IsProcessorPresent (Socket, StdHeader)) { - GetCpuServicesOfSocket (Socket, &FamilySpecificServices, StdHeader); - FamilySpecificServices->GetSysPmTableStruct (FamilySpecificServices, &Ignored, &NumberOfSteps, StdHeader); + GetCpuServicesOfSocket (Socket, (const CPU_SPECIFIC_SERVICES **)&FamilySpecificServices, StdHeader); + FamilySpecificServices->GetSysPmTableStruct (FamilySpecificServices, (const VOID **)&Ignored, &NumberOfSteps, StdHeader); if (NumberOfSteps > *NumSystemSteps) { *NumSystemSteps = NumberOfSteps; } @@ -230,7 +235,7 @@ GetSystemNbCofMulti ( NbPstateDisabled = FALSE; for (Socket = 0; Socket < GetPlatformNumberOfSockets (); Socket++) { if (IsProcessorPresent (Socket, StdHeader)) { - GetCpuServicesOfSocket (Socket, &FamilySpecificServices, StdHeader); + GetCpuServicesOfSocket (Socket, (const CPU_SPECIFIC_SERVICES **)&FamilySpecificServices, StdHeader); for (Module = 0; Module < GetPlatformNumberOfModules (); Module++) { if (GetPciAddress (StdHeader, Socket, Module, &PciAddress, &Ignored)) { break; @@ -308,7 +313,7 @@ GetSystemNbCofVidUpdateMulti ( AtLeast1RequiresUpdate = FALSE; for (Socket = 0; Socket < NumberOfSockets; Socket++) { if (IsProcessorPresent (Socket, StdHeader)) { - GetCpuServicesOfSocket (Socket, &FamilySpecificServices, StdHeader); + GetCpuServicesOfSocket (Socket, (const CPU_SPECIFIC_SERVICES **)&FamilySpecificServices, StdHeader); for (Module = 0; Module < GetPlatformNumberOfModules (); Module++) { if (GetPciAddress (StdHeader, (UINT8) Socket, Module, &PciAddress, &Ignored)) { break; @@ -348,7 +353,7 @@ GetEarlyPmErrorsMulti ( UINT16 i; UINT32 BscSocket; UINT32 BscModule; - UINT32 BscCore; + UINT32 BscCoreNum; UINT32 Socket; UINT32 NumberOfSockets; AP_TASK TaskPtr; @@ -367,7 +372,7 @@ GetEarlyPmErrorsMulti ( EventLogEntry.DataParam4 = 0; NumberOfSockets = GetPlatformNumberOfSockets (); - IdentifyCore (StdHeader, &BscSocket, &BscModule, &BscCore, &DummyStatus); + IdentifyCore (StdHeader, &BscSocket, &BscModule, &BscCoreNum, &DummyStatus); TaskPtr.FuncAddress.PfApTaskI = GetNextEvent; TaskPtr.DataTransfer.DataSizeInDwords = SIZE_IN_DWORDS (AGESA_EVENT); diff --git a/src/vendorcode/amd/agesa/f14/Proc/CPU/cpuPowerMgmtSingleSocket.c b/src/vendorcode/amd/agesa/f14/Proc/CPU/cpuPowerMgmtSingleSocket.c index 4e9a47fde3..0578fcff1a 100644 --- a/src/vendorcode/amd/agesa/f14/Proc/CPU/cpuPowerMgmtSingleSocket.c +++ b/src/vendorcode/amd/agesa/f14/Proc/CPU/cpuPowerMgmtSingleSocket.c @@ -77,6 +77,11 @@ RDATA_GROUP (G1_PEICC) *---------------------------------------------------------------------------------------- */ +AGESA_STATUS +GetEarlyPmErrorsSingle ( + IN AMD_CONFIG_PARAMS *StdHeader + ); + /*---------------------------------------------------------------------------------------- * E X P O R T E D F U N C T I O N S *---------------------------------------------------------------------------------------- @@ -125,8 +130,8 @@ GetNumberOfSystemPmStepsPtrSingle ( SYS_PM_TBL_STEP *Ignored; CPU_SPECIFIC_SERVICES *FamilySpecificServices; - GetCpuServicesOfCurrentCore (&FamilySpecificServices, StdHeader); - FamilySpecificServices->GetSysPmTableStruct (FamilySpecificServices, &Ignored, NumSystemSteps, StdHeader); + GetCpuServicesOfCurrentCore ((const CPU_SPECIFIC_SERVICES **)&FamilySpecificServices, StdHeader); + FamilySpecificServices->GetSysPmTableStruct (FamilySpecificServices, (const VOID **)&Ignored, NumSystemSteps, StdHeader); } @@ -166,7 +171,7 @@ GetSystemNbCofSingle ( PciAddress.AddressValue = MAKE_SBDFO (0, 0, 24, 0, 0); *SystemNbCofsMatch = TRUE; - GetCpuServicesOfCurrentCore (&FamilySpecificServices, StdHeader); + GetCpuServicesOfCurrentCore ((const CPU_SPECIFIC_SERVICES **)&FamilySpecificServices, StdHeader); *NbPstateIsEnabledOnAllCPUs = FamilySpecificServices->GetNbPstateInfo (FamilySpecificServices, PlatformConfig, &PciAddress, @@ -203,7 +208,7 @@ GetSystemNbCofVidUpdateSingle ( CPU_SPECIFIC_SERVICES *FamilySpecificServices; PciAddress.AddressValue = MAKE_SBDFO (0, 0, 24, 0, 0); - GetCpuServicesOfCurrentCore (&FamilySpecificServices, StdHeader); + GetCpuServicesOfCurrentCore ((const CPU_SPECIFIC_SERVICES **)&FamilySpecificServices, StdHeader); return (FamilySpecificServices->IsNbCofInitNeeded (FamilySpecificServices, &PciAddress, &Ignored, StdHeader)); } diff --git a/src/vendorcode/amd/agesa/f14/Proc/CPU/cpuRegisters.h b/src/vendorcode/amd/agesa/f14/Proc/CPU/cpuRegisters.h index beeb2a48f9..c84628ac7d 100644 --- a/src/vendorcode/amd/agesa/f14/Proc/CPU/cpuRegisters.h +++ b/src/vendorcode/amd/agesa/f14/Proc/CPU/cpuRegisters.h @@ -9,7 +9,7 @@ * @xrefitem bom "File Content Label" "Release Content" * @e project: AGESA * @e sub-project: CPU - * @e \$Revision: 37150 $ @e \$Date: 2010-08-31 23:53:37 +0800 (Tue, 31 Aug 2010) $ + * @e \$Revision: 48588 $ @e \$Date: 2011-03-10 08:57:36 -0700 (Thu, 10 Mar 2011) $ * */ /* @@ -176,6 +176,9 @@ typedef struct { #define MSR_SYS_CFG 0xC0010010 // SYSCFG - F15 Shared #define MSR_TOM2 0xC001001D // TOP_MEM2 - F15 Shared +#define MSR_MC0_CTL_MASK 0xC0010044 // MC0 Control Mask +#define MSR_MC1_CTL_MASK 0xC0010045 // MC1 Control Mask +#define MSR_MC2_CTL_MASK 0xC0010046 // MC2 Control Mask #define MSR_MC4_CTL_MASK 0xC0010048 // MC4 Control Mask #define MSR_CPUID_FEATS 0xC0011004 // CPUID Features @@ -381,27 +384,11 @@ typedef enum { REG_EDX ///< EDX } CPUID_REG; -/// MSR table entry for DSM workaround -typedef struct { - UINT32 Address; ///< MSR address to program - UINT64 Nand; ///< Bitwise NAND mask to apply during read-modify-write - UINT64 Or; ///< Bitwise OR mask to apply during read-modify-write -} MSR_DSM_ENTRY; - -/// Interrupt Descriptor Table entry -typedef struct { - UINT16 OffsetLo; ///< Lower 16 bits of the interrupt handler routine's offset - UINT16 Selector; ///< Interrupt handler routine's selector - UINT8 Rsvd; ///< Reserved - UINT8 Flags; ///< Interrupt flags - UINT16 OffsetHi; ///< Upper 16 bits of the interrupt handler routine's offset - UINT32 Offset64; ///< High order 32 bits of the handler's offset needed when in 64 bit mode - UINT32 Rsvd64; ///< Reserved -} IDT_DESCRIPTOR; - +/// Structure needed to load the IDTR using the lidt instruction typedef struct { UINT16 Limit; ///< Interrupt Descriptor Table size UINT64 Base; ///< Interrupt Descriptor Table base address } IDT_BASE_LIMIT; + #endif // _CPU_REGISTERS_H_ diff --git a/src/vendorcode/amd/agesa/f14/Proc/CPU/cpuWarmReset.c b/src/vendorcode/amd/agesa/f14/Proc/CPU/cpuWarmReset.c index bfed40aaa8..81ac8f63e5 100644 --- a/src/vendorcode/amd/agesa/f14/Proc/CPU/cpuWarmReset.c +++ b/src/vendorcode/amd/agesa/f14/Proc/CPU/cpuWarmReset.c @@ -101,7 +101,7 @@ SetWarmResetFlag ( CPU_SPECIFIC_SERVICES *FamilySpecificServices; FamilySpecificServices = NULL; - GetCpuServicesOfCurrentCore (&FamilySpecificServices, StdHeader); + GetCpuServicesOfCurrentCore ((const CPU_SPECIFIC_SERVICES **)&FamilySpecificServices, StdHeader); FamilySpecificServices->SetWarmResetFlag (FamilySpecificServices, StdHeader, Request); } @@ -127,7 +127,7 @@ GetWarmResetFlag ( CPU_SPECIFIC_SERVICES *FamilySpecificServices; FamilySpecificServices = NULL; - GetCpuServicesOfCurrentCore (&FamilySpecificServices, StdHeader); + GetCpuServicesOfCurrentCore ((const CPU_SPECIFIC_SERVICES **)&FamilySpecificServices, StdHeader); FamilySpecificServices->GetWarmResetFlag (FamilySpecificServices, StdHeader, Request); switch (StdHeader->Func) { @@ -189,7 +189,7 @@ IsWarmReset ( break; } - GetCpuServicesOfCurrentCore (&FamilySpecificServices, StdHeader); + GetCpuServicesOfCurrentCore ((const CPU_SPECIFIC_SERVICES **)&FamilySpecificServices, StdHeader); FamilySpecificServices->GetWarmResetFlag (FamilySpecificServices, StdHeader, &Request); if (Request.StateBits >= PostStage) { diff --git a/src/vendorcode/amd/agesa/f14/Proc/CPU/heapManager.c b/src/vendorcode/amd/agesa/f14/Proc/CPU/heapManager.c index 520b96176c..57e1838387 100644 --- a/src/vendorcode/amd/agesa/f14/Proc/CPU/heapManager.c +++ b/src/vendorcode/amd/agesa/f14/Proc/CPU/heapManager.c @@ -156,8 +156,8 @@ HeapManagerInit ( return AGESA_FATAL; } - GetCpuServicesOfCurrentCore (&FamilySpecificServices, StdHeader); - FamilySpecificServices->GetCacheInfo (FamilySpecificServices, &CacheInfoPtr, &Ignored, StdHeader); + GetCpuServicesOfCurrentCore ((const CPU_SPECIFIC_SERVICES **)&FamilySpecificServices, StdHeader); + FamilySpecificServices->GetCacheInfo (FamilySpecificServices, (const VOID **)&CacheInfoPtr, &Ignored, StdHeader); HeapBufferPtr = (UINT8 *) StdHeader->HeapBasePtr; // Check whether the heap manager is already initialized @@ -655,8 +655,8 @@ HeapLocateBuffer ( * @return Heap base address of the executing core's heap. * */ -UINT64 -HeapGetBaseAddress ( +VOID +*HeapGetBaseAddress ( IN AMD_CONFIG_PARAMS *StdHeader ) { @@ -787,7 +787,7 @@ InsertFreeSpaceNode ( HEAP_MANAGER *HeapManager; BUFFER_NODE *CurrentFreeSpaceNode; BUFFER_NODE *PreviousFreeSpaceNode; - BUFFER_NODE *InsertFreeSpaceNode; + BUFFER_NODE *FreeSpaceInsertNode; BaseAddress = (UINT8 *) StdHeader->HeapBasePtr; HeapManager = (HEAP_MANAGER *) BaseAddress; @@ -795,14 +795,14 @@ InsertFreeSpaceNode ( OffsetOfPreviousNode = AMD_HEAP_INVALID_HEAP_OFFSET; OffsetOfCurrentNode = HeapManager->FirstFreeSpaceOffset; CurrentFreeSpaceNode = (BUFFER_NODE *) (BaseAddress + OffsetOfCurrentNode); - InsertFreeSpaceNode = (BUFFER_NODE *) (BaseAddress + OffsetOfInsertNode); + FreeSpaceInsertNode = (BUFFER_NODE *) (BaseAddress + OffsetOfInsertNode); while ((OffsetOfCurrentNode != AMD_HEAP_INVALID_HEAP_OFFSET) && - (CurrentFreeSpaceNode->BufferSize < InsertFreeSpaceNode->BufferSize)) { + (CurrentFreeSpaceNode->BufferSize < FreeSpaceInsertNode->BufferSize)) { OffsetOfPreviousNode = OffsetOfCurrentNode; OffsetOfCurrentNode = CurrentFreeSpaceNode->OffsetOfNextNode; CurrentFreeSpaceNode = (BUFFER_NODE *) (BaseAddress + OffsetOfCurrentNode); } - InsertFreeSpaceNode->OffsetOfNextNode = OffsetOfCurrentNode; + FreeSpaceInsertNode->OffsetOfNextNode = OffsetOfCurrentNode; if (OffsetOfPreviousNode == AMD_HEAP_INVALID_HEAP_OFFSET) { HeapManager->FirstFreeSpaceOffset = OffsetOfInsertNode; } else { @@ -838,7 +838,7 @@ HeapGetCurrentBase ( if (IsBsp (StdHeader, &IgnoredStatus)) { ReturnPtr = AMD_HEAP_START_ADDRESS; } else { - GetCpuServicesOfCurrentCore (&FamilyServices, StdHeader); + GetCpuServicesOfCurrentCore ((const CPU_SPECIFIC_SERVICES **)&FamilyServices, StdHeader); ASSERT (FamilyServices != NULL); SystemCoreNumber = FamilyServices->GetApCoreNumber (FamilyServices, StdHeader); diff --git a/src/vendorcode/amd/agesa/f14/Proc/CPU/heapManager.h b/src/vendorcode/amd/agesa/f14/Proc/CPU/heapManager.h index 14e58f044d..678a7cdd8c 100644 --- a/src/vendorcode/amd/agesa/f14/Proc/CPU/heapManager.h +++ b/src/vendorcode/amd/agesa/f14/Proc/CPU/heapManager.h @@ -65,7 +65,7 @@ #define AMD_HEAP_REGION_END_ADDRESS 0xBFFFFF #define AMD_HEAP_SIZE_PER_CORE 0x010000 #define AMD_HEAP_INVALID_HEAP_OFFSET 0xFFFFFFFF -#define AMD_HEAP_MTRR_MASK ((0xFFFFFFFFFFFFF800 & ((AMD_HEAP_SIZE_PER_CORE ^ (-1)) + 1) | 0x800)) +#define AMD_HEAP_MTRR_MASK (0xFFFFFFFFFFFFF800ull & (((AMD_HEAP_SIZE_PER_CORE ^ (-1)) + 1) | 0x800)) #define AMD_HEAP_SIZE_DWORD_PER_CORE (AMD_HEAP_SIZE_PER_CORE / 4) #define AMD_TEMP_TOM 0x20000000 // Set TOM to 512 MB (temporary value) @@ -144,7 +144,7 @@ typedef struct _HEAP_MANAGER { } HEAP_MANAGER; /// AGESA Buffer Handles (These are reserved) -typedef enum { +typedef enum _AGESA_BUFFER_HANDLE { AMD_INIT_RESET_HANDLE = 0x000A000, ///< Assign 0x000A000 buffer handle to AmdInitReset routine. AMD_INIT_EARLY_HANDLE, ///< Assign 0x000A001 buffer handle to AmdInitEarly routine. AMD_INIT_POST_HANDLE, ///< Assign 0x000A002 buffer handle to AmdInitPost routine. @@ -218,8 +218,8 @@ HeapLocateBuffer ( IN AMD_CONFIG_PARAMS *StdHeader ); -UINT64 -HeapGetBaseAddress ( +VOID +*HeapGetBaseAddress ( IN AMD_CONFIG_PARAMS *StdHeader ); diff --git a/src/vendorcode/amd/agesa/f14/Proc/Common/AmdInitEarly.c b/src/vendorcode/amd/agesa/f14/Proc/Common/AmdInitEarly.c index bf74376c4e..ea048eb4de 100644 --- a/src/vendorcode/amd/agesa/f14/Proc/Common/AmdInitEarly.c +++ b/src/vendorcode/amd/agesa/f14/Proc/Common/AmdInitEarly.c @@ -60,6 +60,7 @@ #include "cpuServices.h" #include "CommonInits.h" #include "GnbInterface.h" +//#include "GnbInitAtEarly.h" #include "Filecode.h" CODE_GROUP (G1_PEICC) RDATA_GROUP (G1_PEICC) @@ -87,6 +88,23 @@ EXECUTION_CACHE_REGION InitExeCacheMap[] = *---------------------------------------------------------------------------------------- */ +AGESA_STATUS +AmdEarlyPlatformConfigInit ( + IN OUT PLATFORM_CONFIGURATION *PlatformConfig, + IN OUT AMD_CONFIG_PARAMS *StdHeader + ); + +AGESA_STATUS +AllocateExecutionCacheInitializer ( + IN AMD_CONFIG_PARAMS *StdHeader, + IN EXECUTION_CACHE_REGION *AmdExeAddrMapPtr + ); + +AGESA_STATUS +AmdInitEarlyInitializer ( + IN AMD_CONFIG_PARAMS *StdHeader, + IN OUT AMD_EARLY_PARAMS *EarlyParams + ); /*---------------------------------------------------------------------------------------- * E X P O R T E D F U N C T I O N S diff --git a/src/vendorcode/amd/agesa/f14/Proc/Common/AmdInitEnv.c b/src/vendorcode/amd/agesa/f14/Proc/Common/AmdInitEnv.c index c986795370..1e32c21433 100644 --- a/src/vendorcode/amd/agesa/f14/Proc/Common/AmdInitEnv.c +++ b/src/vendorcode/amd/agesa/f14/Proc/Common/AmdInitEnv.c @@ -53,6 +53,7 @@ #include "Ids.h" #include "cpuEnvInit.h" #include "heapManager.h" +#include "CreateStruct.h" #include "GnbInterface.h" #include "CommonInits.h" #include "S3SaveState.h" diff --git a/src/vendorcode/amd/agesa/f14/Proc/Common/AmdInitLate.c b/src/vendorcode/amd/agesa/f14/Proc/Common/AmdInitLate.c index 3bc1aa24d7..d5669e4ed4 100644 --- a/src/vendorcode/amd/agesa/f14/Proc/Common/AmdInitLate.c +++ b/src/vendorcode/amd/agesa/f14/Proc/Common/AmdInitLate.c @@ -83,6 +83,23 @@ extern OPTION_PSTATE_LATE_CONFIGURATION OptionPstateLateConfiguration; *---------------------------------------------------------------------------------------- */ +AGESA_STATUS +AmdLatePlatformConfigInit ( + IN OUT PLATFORM_CONFIGURATION *PlatformConfig, + IN OUT AMD_CONFIG_PARAMS *StdHeader + ); + +AGESA_STATUS +AmdInitLateInitializer ( + IN AMD_CONFIG_PARAMS *StdHeader, + IN OUT AMD_LATE_PARAMS *LateParamsPtr + ); + +AGESA_STATUS +AmdInitLateDestructor ( + IN AMD_CONFIG_PARAMS *StdHeader, + IN AMD_LATE_PARAMS *LateParamsPtr + ); /*---------------------------------------------------------------------------------------- * E X P O R T E D F U N C T I O N S diff --git a/src/vendorcode/amd/agesa/f14/Proc/Common/AmdInitMid.c b/src/vendorcode/amd/agesa/f14/Proc/Common/AmdInitMid.c index efa668c815..e707f7d49d 100644 --- a/src/vendorcode/amd/agesa/f14/Proc/Common/AmdInitMid.c +++ b/src/vendorcode/amd/agesa/f14/Proc/Common/AmdInitMid.c @@ -53,6 +53,7 @@ #include "Ids.h" #include "cpuFeatures.h" #include "CommonInits.h" +#include "CreateStruct.h" #include "GnbInterface.h" #include "Filecode.h" CODE_GROUP (G1_PEICC) diff --git a/src/vendorcode/amd/agesa/f14/Proc/Common/AmdInitPost.c b/src/vendorcode/amd/agesa/f14/Proc/Common/AmdInitPost.c index c7ab7d4e3c..958d1e5598 100644 --- a/src/vendorcode/amd/agesa/f14/Proc/Common/AmdInitPost.c +++ b/src/vendorcode/amd/agesa/f14/Proc/Common/AmdInitPost.c @@ -57,6 +57,7 @@ #include "cpuServices.h" #include "cpuPostInit.h" #include "AdvancedApi.h" +#include "CreateStruct.h" #include "heapManager.h" #include "CommonInits.h" #include "cpuServices.h" @@ -83,6 +84,11 @@ RDATA_GROUP (G1_PEICC) *---------------------------------------------------------------------------------------- */ +AGESA_STATUS +AmdPostPlatformConfigInit ( + IN OUT PLATFORM_CONFIGURATION *PlatformConfig, + IN OUT AMD_CONFIG_PARAMS *StdHeader + ); /*---------------------------------------------------------------------------------------- * E X P O R T E D F U N C T I O N S diff --git a/src/vendorcode/amd/agesa/f14/Proc/Common/AmdInitReset.c b/src/vendorcode/amd/agesa/f14/Proc/Common/AmdInitReset.c index 2a7b99e30b..a3f0870d73 100644 --- a/src/vendorcode/amd/agesa/f14/Proc/Common/AmdInitReset.c +++ b/src/vendorcode/amd/agesa/f14/Proc/Common/AmdInitReset.c @@ -80,6 +80,17 @@ extern BUILD_OPT_CFG UserOptions; *---------------------------------------------------------------------------------------- */ +AGESA_STATUS +AmdInitResetExecutionCacheAllocateInitializer ( + IN AMD_CONFIG_PARAMS *StdHeader, + IN EXECUTION_CACHE_REGION *AmdExeAddrMapPtr + ); + +AGESA_STATUS +AmdInitResetConstructor ( + IN AMD_CONFIG_PARAMS *StdHeader, + IN AMD_RESET_PARAMS *AmdResetParams + ); /*---------------------------------------------------------------------------------------- * E X P O R T E D F U N C T I O N S diff --git a/src/vendorcode/amd/agesa/f14/Proc/Common/AmdInitResume.c b/src/vendorcode/amd/agesa/f14/Proc/Common/AmdInitResume.c index b199fba482..532f7d51db 100644 --- a/src/vendorcode/amd/agesa/f14/Proc/Common/AmdInitResume.c +++ b/src/vendorcode/amd/agesa/f14/Proc/Common/AmdInitResume.c @@ -60,6 +60,7 @@ #include "cpuRegisters.h" #include "cpuApicUtilities.h" #include "cpuPostInit.h" +#include "CreateStruct.h" #include "CommonInits.h" #include "cpuFeatures.h" CODE_GROUP (G1_PEICC) diff --git a/src/vendorcode/amd/agesa/f14/Proc/Common/AmdLateRunApTask.c b/src/vendorcode/amd/agesa/f14/Proc/Common/AmdLateRunApTask.c index 74aebbcd11..84f5cafef6 100644 --- a/src/vendorcode/amd/agesa/f14/Proc/Common/AmdLateRunApTask.c +++ b/src/vendorcode/amd/agesa/f14/Proc/Common/AmdLateRunApTask.c @@ -52,6 +52,7 @@ #include "AGESA.h" #include "Ids.h" #include "Options.h" +#include "CreateStruct.h" #include "Filecode.h" CODE_GROUP (G3_DXE) RDATA_GROUP (G3_DXE) diff --git a/src/vendorcode/amd/agesa/f14/Proc/Common/AmdS3LateRestore.c b/src/vendorcode/amd/agesa/f14/Proc/Common/AmdS3LateRestore.c index b38bb67989..62e23d6984 100644 --- a/src/vendorcode/amd/agesa/f14/Proc/Common/AmdS3LateRestore.c +++ b/src/vendorcode/amd/agesa/f14/Proc/Common/AmdS3LateRestore.c @@ -56,6 +56,7 @@ #include "cpuFeatures.h" #include "S3SaveState.h" #include "CommonInits.h" +#include "CreateStruct.h" #include "Filecode.h" CODE_GROUP (G2_PEI) RDATA_GROUP (G2_PEI) @@ -120,7 +121,7 @@ AmdS3LateRestore ( ASSERT (S3LateParams != NULL); BufferPointer = (UINT8 *) S3LateParams->S3DataBlock.VolatileStorage; - S3LateParams->StdHeader.HeapBasePtr = (UINT64) &BufferPointer[((S3_VOLATILE_STORAGE_HEADER *) S3LateParams->S3DataBlock.VolatileStorage)->HeapOffset]; + S3LateParams->StdHeader.HeapBasePtr = &BufferPointer[((S3_VOLATILE_STORAGE_HEADER *) S3LateParams->S3DataBlock.VolatileStorage)->HeapOffset]; ASSERT (S3LateParams->StdHeader.HeapBasePtr != NULL); IDS_OPTION_HOOK (IDS_PLATFORMCFG_OVERRIDE, &S3LateParams->PlatformConfig, &S3LateParams->StdHeader); diff --git a/src/vendorcode/amd/agesa/f14/Proc/Common/AmdS3Save.c b/src/vendorcode/amd/agesa/f14/Proc/Common/AmdS3Save.c index 147487bb09..f994c87f66 100644 --- a/src/vendorcode/amd/agesa/f14/Proc/Common/AmdS3Save.c +++ b/src/vendorcode/amd/agesa/f14/Proc/Common/AmdS3Save.c @@ -57,6 +57,7 @@ #include "S3.h" #include "mfs3.h" #include "CommonInits.h" +#include "CreateStruct.h" #include "Filecode.h" #include "heapManager.h" #include "Topology.h" @@ -225,9 +226,9 @@ AmdS3Save ( BufferPointer = AllocParams.BufferPtr; AmdS3SaveParams->S3DataBlock.VolatileStorage = &(BufferPointer[EarlyBufferSize]); - ((S3_VOLATILE_STORAGE_HEADER *) AmdS3SaveParams->S3DataBlock.VolatileStorage)->HeapOffset = NULL; + ((S3_VOLATILE_STORAGE_HEADER *) AmdS3SaveParams->S3DataBlock.VolatileStorage)->HeapOffset = 0; ((S3_VOLATILE_STORAGE_HEADER *) AmdS3SaveParams->S3DataBlock.VolatileStorage)->HeapSize = HeapSize; - ((S3_VOLATILE_STORAGE_HEADER *) AmdS3SaveParams->S3DataBlock.VolatileStorage)->RegisterDataOffset = NULL; + ((S3_VOLATILE_STORAGE_HEADER *) AmdS3SaveParams->S3DataBlock.VolatileStorage)->RegisterDataOffset = 0; ((S3_VOLATILE_STORAGE_HEADER *) AmdS3SaveParams->S3DataBlock.VolatileStorage)->RegisterDataSize = LateContextSize; if (HeapSize != 0) { diff --git a/src/vendorcode/amd/agesa/f14/Proc/Common/CommonInits.c b/src/vendorcode/amd/agesa/f14/Proc/Common/CommonInits.c index edfdbb1d89..3b23e205fa 100644 --- a/src/vendorcode/amd/agesa/f14/Proc/Common/CommonInits.c +++ b/src/vendorcode/amd/agesa/f14/Proc/Common/CommonInits.c @@ -51,6 +51,7 @@ */ #include "AGESA.h" #include "Ids.h" +#include "CommonInits.h" #include "Filecode.h" #include "heapManager.h" CODE_GROUP (G1_PEICC) diff --git a/src/vendorcode/amd/agesa/f14/Proc/Common/CommonReturns.c b/src/vendorcode/amd/agesa/f14/Proc/Common/CommonReturns.c index 90e2918d2d..4aa9f45dd1 100644 --- a/src/vendorcode/amd/agesa/f14/Proc/Common/CommonReturns.c +++ b/src/vendorcode/amd/agesa/f14/Proc/Common/CommonReturns.c @@ -52,6 +52,7 @@ #include "AGESA.h" #include "Ids.h" +#include "CommonReturns.h" #include "Filecode.h" CODE_GROUP (G1_PEICC) RDATA_GROUP (G1_PEICC) diff --git a/src/vendorcode/amd/agesa/f14/Proc/Common/CreateStruct.c b/src/vendorcode/amd/agesa/f14/Proc/Common/CreateStruct.c index 68ecb63a3c..1b691a6132 100644 --- a/src/vendorcode/amd/agesa/f14/Proc/Common/CreateStruct.c +++ b/src/vendorcode/amd/agesa/f14/Proc/Common/CreateStruct.c @@ -136,7 +136,7 @@ AmdCreateStruct ( if (!IsBsp (&InterfaceParams->StdHeader, &IgnoredSts)) { // APs must transfer their system core number from the mailbox to // a local register while it is still valid. - GetCpuServicesOfCurrentCore (&FamilySpecificServices, &InterfaceParams->StdHeader); + GetCpuServicesOfCurrentCore ((const CPU_SPECIFIC_SERVICES **)&FamilySpecificServices, &InterfaceParams->StdHeader); FamilySpecificServices->TransferApCoreNumber (FamilySpecificServices, &InterfaceParams->StdHeader); } InterfaceParams->StdHeader.HeapStatus = HEAP_DO_NOT_EXIST_YET; diff --git a/src/vendorcode/amd/agesa/f14/Proc/Common/CreateStruct.h b/src/vendorcode/amd/agesa/f14/Proc/Common/CreateStruct.h index df47cbeb37..8d539420d3 100644 --- a/src/vendorcode/amd/agesa/f14/Proc/Common/CreateStruct.h +++ b/src/vendorcode/amd/agesa/f14/Proc/Common/CreateStruct.h @@ -98,7 +98,7 @@ typedef struct { /// Do NOT include a config params header! OUT PF_AGESA_FUNCTION AgesaFunction; ///< The constructor function OUT PF_AGESA_DESTRUCTOR AgesaDestructor; ///< The destructor function. - IN AGESA_BUFFER_HANDLE BufferHandle; ///< The buffer handle id for the service. + IN UINT32 BufferHandle; ///< The buffer handle id for the service. } FUNCTION_PARAMS_INFO; /** diff --git a/src/vendorcode/amd/agesa/f14/Proc/Common/S3SaveState.c b/src/vendorcode/amd/agesa/f14/Proc/Common/S3SaveState.c index 7fe7476128..7c52ed80aa 100644 --- a/src/vendorcode/amd/agesa/f14/Proc/Common/S3SaveState.c +++ b/src/vendorcode/amd/agesa/f14/Proc/Common/S3SaveState.c @@ -77,6 +77,12 @@ extern S3_SCRIPT_CONFIGURATION OptionS3ScriptConfiguration; *---------------------------------------------------------------------------------------- */ +AGESA_STATUS +S3SaveStateExtendTableLenth ( + IN AMD_CONFIG_PARAMS *StdHeader, + IN OUT S3_SAVE_TABLE_HEADER **S3SaveTable + ); + /*----------------------------------------------------------------------------------------*/ /** * Initialize S3 Script framework @@ -570,31 +576,31 @@ S3SaveDebugOpcodeString ( { switch (Op) { case SAVE_STATE_IO_WRITE_OPCODE: - return "IO WR"; + return (CHAR8*)"IO WR"; case SAVE_STATE_IO_READ_WRITE_OPCODE: - return "IO RD/WR"; + return (CHAR8*)"IO RD/WR"; case SAVE_STATE_IO_POLL_OPCODE: - return "IO POLL"; + return (CHAR8*)"IO POLL"; case SAVE_STATE_MEM_WRITE_OPCODE: - return "MEM WR"; + return (CHAR8*)"MEM WR"; case SAVE_STATE_MEM_READ_WRITE_OPCODE: - return "MEM RD/WR"; + return (CHAR8*)"MEM RD/WR"; case SAVE_STATE_MEM_POLL_OPCODE: - return "MEM POLL"; + return (CHAR8*)"MEM POLL"; case SAVE_STATE_PCI_CONFIG_WRITE_OPCODE: - return "PCI WR"; + return (CHAR8*)"PCI WR"; case SAVE_STATE_PCI_CONFIG_READ_WRITE_OPCODE: - return "PCI RD/WR"; + return (CHAR8*)"PCI RD/WR"; case SAVE_STATE_PCI_CONFIG_POLL_OPCODE: - return "PCI POLL"; + return (CHAR8*)"PCI POLL"; case SAVE_STATE_STALL_OPCODE: - return "STALL"; + return (CHAR8*)"STALL"; case SAVE_STATE_DISPATCH_OPCODE: - return "DISPATCH"; + return (CHAR8*)"DISPATCH"; default: IDS_ERROR_TRAP; } - return "!!! Unrecognize opcode !!!"; + return (CHAR8*)"!!! Unrecognize opcode !!!"; } diff --git a/src/vendorcode/amd/agesa/f14/Proc/GNB/Common/Gnb.h b/src/vendorcode/amd/agesa/f14/Proc/GNB/Common/Gnb.h index 72ccb844a4..8f5c179172 100644 --- a/src/vendorcode/amd/agesa/f14/Proc/GNB/Common/Gnb.h +++ b/src/vendorcode/amd/agesa/f14/Proc/GNB/Common/Gnb.h @@ -9,7 +9,7 @@ * @xrefitem bom "File Content Label" "Release Content" * @e project: AGESA * @e sub-project: GNB - * @e \$Revision: 40151 $ @e \$Date: 2010-10-20 06:38:17 +0800 (Wed, 20 Oct 2010) $ + * @e \$Revision: 44325 $ @e \$Date: 2010-12-22 03:29:53 -0700 (Wed, 22 Dec 2010) $ * */ /* @@ -69,13 +69,16 @@ #endif #endif +#ifndef MIN #define MIN(x, y) (((x) > (y))? (y):(x)) +#endif + +#ifndef MAX #define MAX(x, y) (((x) > (y))? (x):(y)) +#endif #define OFF 0 -#define PVOID UINT64 - #define GnbLibGetHeader(x) ((AMD_CONFIG_PARAMS*) (x)->StdHeader) #define AGESA_STATUS_UPDATE(Current, Aggregated) \ diff --git a/src/vendorcode/amd/agesa/f14/Proc/GNB/Common/GnbFuseTable.h b/src/vendorcode/amd/agesa/f14/Proc/GNB/Common/GnbFuseTable.h index fe41a396a6..11b0cf7664 100644 --- a/src/vendorcode/amd/agesa/f14/Proc/GNB/Common/GnbFuseTable.h +++ b/src/vendorcode/amd/agesa/f14/Proc/GNB/Common/GnbFuseTable.h @@ -9,7 +9,7 @@ * @xrefitem bom "File Content Label" "Release Content" * @e project: AGESA * @e sub-project: GNB - * @e \$Revision: 38902 $ @e \$Date: 2010-10-02 02:01:38 +0800 (Sat, 02 Oct 2010) $ + * @e \$Revision: 47437 $ @e \$Date: 2011-02-20 15:32:39 -0700 (Sun, 20 Feb 2011) $ * */ /* @@ -52,13 +52,14 @@ #define PP_FUSE_MAX_NUM_DPM_STATE 5 #define PP_FUSE_MAX_NUM_SW_STATE 6 + /// Fuse definition structure typedef struct { UINT8 PPlayTableRev; ///< PP table revision UINT8 SclkDpmValid[6]; ///< Valid DPM states - UINT8 SclkDpmDid[5]; ///< Sclk DPM DID - UINT8 SclkDpmVid[5]; ///< Sclk DPM VID - UINT8 SclkDpmCac[5]; ///< Sclk DPM Cac + UINT8 SclkDpmDid[6]; ///< Sclk DPM DID + UINT8 SclkDpmVid[6]; ///< Sclk DPM VID + UINT8 SclkDpmCac[6]; ///< Sclk DPM Cac UINT8 PolicyFlags[6]; ///< State policy flags UINT8 PolicyLabel[6]; ///< State policy label UINT8 VclkDid[4]; ///< VCLK DID @@ -72,6 +73,11 @@ typedef struct { UINT8 PcieGen2Vid; ///< Pcie Gen 2 VID UINT8 MainPllId; ///< Main PLL Id from fuses UINT8 WrCkDid; ///< WRCK SMU clock Divisor + UINT8 GpuBoostCap; ///< GPU boost cap + UINT16 SclkDpmTdpLimit[6]; ///< Sclk DPM TDP limit + UINT16 SclkDpmTdpLimitPG; ///< TDP limit PG + UINT32 SclkDpmBoostMargin; ///< Boost margin + UINT32 SclkDpmThrottleMargin; ///< Throttle margin } PP_FUSE_ARRAY; #pragma pack (pop) diff --git a/src/vendorcode/amd/agesa/f14/Proc/GNB/Common/GnbGfx.h b/src/vendorcode/amd/agesa/f14/Proc/GNB/Common/GnbGfx.h index 65212e2da7..e1eb89343a 100644 --- a/src/vendorcode/amd/agesa/f14/Proc/GNB/Common/GnbGfx.h +++ b/src/vendorcode/amd/agesa/f14/Proc/GNB/Common/GnbGfx.h @@ -47,10 +47,6 @@ #ifndef _GNBGFX_H_ #define _GNBGFX_H_ -//#ifndef PVOID -// typedef UINT64 PVOID; -//#endif - #define DEVICE_DFP 0x1 #define DEVICE_CRT 0x2 #define DEVICE_LCD 0x3 @@ -119,7 +115,7 @@ typedef enum { /// Graphics Platform Configuration typedef struct { - PVOID StdHeader; ///< Standard Header + AMD_CONFIG_PARAMS* StdHeader; ///< Standard Header PCI_ADDR GfxPciAddress; ///< Graphics PCI Address UMA_INFO UmaInfo; ///< UMA Information UINT32 GmmBase; ///< GMM Base @@ -144,6 +140,8 @@ typedef struct { GFX_CONTROLLER_MODE GfxControllerMode; ///< Gfx controller mode UINT16 LvdsSpreadSpectrum; ///< Spread spectrum value in 0.01 % UINT16 LvdsSpreadSpectrumRate; ///< Spread spectrum frequency used by SS hardware logic in unit of 10Hz, 0 - default frequency 40kHz + LVDS_MISC_CONTROL LvdsMiscControl; ///< This item configures LVDS swap/Hsync/Vsync/BLON + UINT16 PcieRefClkSpreadSpectrum; ///< Spread spectrum value in 0.01 % } GFX_PLATFORM_CONFIG; @@ -275,7 +273,15 @@ typedef struct _ATOM_INTEGRATED_SYSTEM_INFO_V6 { USHORT usHDMISSpreadRateIn10Hz; ///< usHDMISSpreadRateIn10Hz USHORT usDVISSPercentage; ///< usDVISSPercentage USHORT usDVISSpreadRateIn10Hz; ///< usDVISSpreadRateIn10Hz - ULONG ulReserved3[21]; ///< Reserved + ULONG SclkDpmBoostMargin; ///< SclkDpmBoostMargin + ULONG SclkDpmThrottleMargin; ///< SclkDpmThrottleMargin + USHORT SclkDpmTdpLimitPG; ///< SclkDpmTdpLimitPG + USHORT SclkDpmTdpLimitBoost; ///< SclkDpmTdpLimitBoost + ULONG ulBoostEngineCLock; ///< ulBoostEngineCLock + UCHAR ulBoostVid_2bit; ///< ulBoostVid_2bit + UCHAR EnableBoost; ///< EnableBoost + USHORT GnbTdpLimit; ///< GnbTdpLimit + ULONG ulReserved3[16]; ///< Reserved ATOM_EXTERNAL_DISPLAY_CONNECTION_INFO sExtDispConnInfo; ///< Display connector definition } ATOM_INTEGRATED_SYSTEM_INFO_V6; diff --git a/src/vendorcode/amd/agesa/f14/Proc/GNB/Common/GnbGfxFamServices.h b/src/vendorcode/amd/agesa/f14/Proc/GNB/Common/GnbGfxFamServices.h index 42e4ef363d..86b39a26fa 100644 --- a/src/vendorcode/amd/agesa/f14/Proc/GNB/Common/GnbGfxFamServices.h +++ b/src/vendorcode/amd/agesa/f14/Proc/GNB/Common/GnbGfxFamServices.h @@ -54,10 +54,15 @@ GfxFmMapEngineToDisplayPath ( IN GFX_PLATFORM_CONFIG *Gfx ); -AGESA_STATUS +UINT32 GfxFmCalculateClock ( IN UINT8 Did, IN AMD_CONFIG_PARAMS *StdHeader ); +VOID +GfxFmSetIdleVoltageMode ( + IN GFX_PLATFORM_CONFIG *Gfx + ); + #endif diff --git a/src/vendorcode/amd/agesa/f14/Proc/GNB/Common/GnbLibFeatures.c b/src/vendorcode/amd/agesa/f14/Proc/GNB/Common/GnbLibFeatures.c index afa652266f..3101d81c35 100644 --- a/src/vendorcode/amd/agesa/f14/Proc/GNB/Common/GnbLibFeatures.c +++ b/src/vendorcode/amd/agesa/f14/Proc/GNB/Common/GnbLibFeatures.c @@ -52,6 +52,7 @@ #include "AMD.h" #include "Gnb.h" #include "OptionGnb.h" +#include "GnbLibFeatures.h" #include "Filecode.h" #define FILECODE PROC_GNB_COMMON_GNBLIBFEATURES_FILECODE /*---------------------------------------------------------------------------------------- @@ -71,6 +72,10 @@ *---------------------------------------------------------------------------------------- */ +AGESA_STATUS +GnbCommonFeatureStub ( + IN AMD_CONFIG_PARAMS *StdHeader + ); diff --git a/src/vendorcode/amd/agesa/f14/Proc/GNB/Common/GnbPcie.h b/src/vendorcode/amd/agesa/f14/Proc/GNB/Common/GnbPcie.h index 2a819b25dd..1d80410b21 100644 --- a/src/vendorcode/amd/agesa/f14/Proc/GNB/Common/GnbPcie.h +++ b/src/vendorcode/amd/agesa/f14/Proc/GNB/Common/GnbPcie.h @@ -65,36 +65,32 @@ #define DESCRIPTOR_ALL_ENGINES (DESCRIPTOR_DDI_ENGINE | DESCRIPTOR_PCIE_ENGINE) #define UNUSED_LANE_ID 128 -#define PCIE_LINK_RECEIVER_DETECTION_POOLING (60 * 1000) -#define PCIE_LINK_L0_POOLING (60 * 1000) -#define PCIE_LINK_GPIO_RESET_ASSERT_TIME (2 * 1000) -#define PCIE_LINK_RESET_TO_TRAINING_TIME (2 * 1000) - -#define IS_LAST_DESCRIPTOR(x) (x->Flags & DESCRIPTOR_TERMINATE_LIST) == 0 -#define IS_VALID_DESCRIPTOR(x) ((x->Flags & DESCRIPTOR_ALLOCATED) != 0) - -// Get lowes phy lane on engine -#define PcieUtilGetLoPhyLane(Engine) ((Engine->EngineData.StartLane > Engine->EngineData.EndLane) ? Engine->EngineData.EndLane : Engine->EngineData.StartLane) -// Get highest phy lane on engine -#define PcieUtilGetHiPhyLane(Engine) ((Engine->EngineData.StartLane > Engine->EngineData.EndLane) ? Engine->EngineData.StartLane : Engine->EngineData.EndLane) + +#define IS_LAST_DESCRIPTOR(Descriptor) (Descriptor != NULL ? ((Descriptor->Flags & DESCRIPTOR_TERMINATE_LIST) == 0) : (1==1)) +#define IS_VALID_DESCRIPTOR(Descriptor) (Descriptor != NULL ? ((Descriptor->Flags & DESCRIPTOR_ALLOCATED) != 0) : (1==0)) + +// Get lowest PHY lane on engine +#define PcieLibGetLoPhyLane(Engine) (Engine != NULL ? ((Engine->EngineData.StartLane > Engine->EngineData.EndLane) ? Engine->EngineData.EndLane : Engine->EngineData.StartLane) : 0xFF) +// Get highest PHY lane on engine +#define PcieLibGetHiPhyLane(Engine) (Engine != NULL ? ((Engine->EngineData.StartLane > Engine->EngineData.EndLane) ? Engine->EngineData.StartLane : Engine->EngineData.EndLane) : 0xFF) // Get number of lanes on wrapper -#define PcieLibWrapperNumberOfLanes(Wrapper) ((UINT8)(Wrapper->EndPhyLane - Wrapper->StartPhyLane + 1)) +#define PcieLibWrapperNumberOfLanes(Wrapper) (Wrapper != NULL ? ((UINT8)(Wrapper->EndPhyLane - Wrapper->StartPhyLane + 1)) : 0) // Check if virtual descriptor -#define PcieLibIsVirtualDesciptor(Descriptor) ((Descriptor->Flags & DESCRIPTOR_VIRTUAL) != 0) +#define PcieLibIsVirtualDesciptor(Descriptor) (Descriptor != NULL ? ((Descriptor->Flags & DESCRIPTOR_VIRTUAL) != 0) : (1==0)) // Check if it is allocated descriptor -#define PcieLibIsEngineAllocated(Descriptor) ((Descriptor->Flags & DESCRIPTOR_ALLOCATED) != 0) +#define PcieLibIsEngineAllocated(Descriptor) (Descriptor != NULL ? ((Descriptor->Flags & DESCRIPTOR_ALLOCATED) != 0) : (1==0)) // Check if it is last descriptor in list -#define PcieLibIsLastDescriptor(Descriptor) ((Descriptor->Flags & DESCRIPTOR_TERMINATE_LIST) != 0) +#define PcieLibIsLastDescriptor(Descriptor) (Descriptor != NULL ? ((Descriptor->Flags & DESCRIPTOR_TERMINATE_LIST) != 0) : (1==1)) // Check if descriptor a PCIe engine -#define PcieLibIsPcieEngine(Descriptor) ((Descriptor->Flags & DESCRIPTOR_PCIE_ENGINE) != 0) +#define PcieLibIsPcieEngine(Descriptor) (Descriptor != NULL ? ((Descriptor->Flags & DESCRIPTOR_PCIE_ENGINE) != 0) : (1==0)) // Check if descriptor a DDI engine -#define PcieLibIsDdiEngine(Descriptor) ((Descriptor->Flags & DESCRIPTOR_DDI_ENGINE) != 0) +#define PcieLibIsDdiEngine(Descriptor) (Descriptor != NULL ? ((Descriptor->Flags & DESCRIPTOR_DDI_ENGINE) != 0) : (1==0)) // Check if descriptor a DDI wrapper -#define PcieLibIsDdiWrapper(Descriptor) ((Descriptor->Flags & DESCRIPTOR_DDI_WRAPPER) != 0) +#define PcieLibIsDdiWrapper(Descriptor) (Descriptor != NULL ? ((Descriptor->Flags & DESCRIPTOR_DDI_WRAPPER) != 0) : (1==0)) // Check if descriptor a PCIe wrapper -#define PcieLibIsPcieWrapper(Descriptor) ((Descriptor->Flags & DESCRIPTOR_PCIE_WRAPPER) != 0) +#define PcieLibIsPcieWrapper(Descriptor) (Descriptor != NULL ? ((Descriptor->Flags & DESCRIPTOR_PCIE_WRAPPER) != 0) : (1==0)) // Check if descriptor a PCIe wrapper -#define PcieLibGetNextDescriptor(Descriptor) ((((Descriptor->Flags & DESCRIPTOR_TERMINATE_LIST) != 0) ? NULL : (++Descriptor))) +#define PcieLibGetNextDescriptor(Descriptor) (Descriptor != NULL ? (((Descriptor->Flags & DESCRIPTOR_TERMINATE_LIST) != 0) ? NULL : ((++Descriptor) != NULL ? Descriptor : NULL)) : NULL) @@ -116,9 +112,9 @@ #define LANE_TYPE_ACTIVE (LANE_TYPE_PCIE_ACTIVE | LANE_TYPE_DDI_ACTIVE) #define LANE_TYPE_ALLOCATED (LANE_TYPE_PCIE_ALLOCATED | LANE_TYPE_DDI_ALLOCATED) -typedef UINT64 PPCIe_ENGINE_CONFIG; -typedef UINT64 PPCIe_WRAPPER_CONFIG; -typedef UINT64 PPCIe_SILICON_CONFIG; +//typedef UINT64 PPCIe_ENGINE_CONFIG; +//typedef UINT64 PPCIe_WRAPPER_CONFIG; +//typedef UINT64 PPCIe_SILICON_CONFIG; #define INIT_STATUS_PCIE_PORT_GEN2_RECOVERY 0x00000001ull #define INIT_STATUS_PCIE_PORT_BROKEN_LANE_RECOVERY 0x00000002ull @@ -135,6 +131,15 @@ typedef UINT64 PPCIe_SILICON_CONFIG; #define PCIE_GLOBAL_GEN_CAP_TRAINED_PORTS 0x00000011 #define PCIE_GLOBAL_GEN_CAP_HOTPLUG_PORTS 0x00000012 +/// PCIe Link Training State +typedef enum { + PcieTrainingStandard, ///< Standard training algorithm. Training contained to AmdEarlyInit. + ///< PCIe device accessible after AmdEarlyInit complete + PcieTrainingDistributed, ///< Distribute training algorithm. Training distributed across AmdEarlyInit/AmdPostInit/AmdS3LateRestore + ///< PCIe device accessible after AmdPostInit complete. + ///< Algorithm potentially save up to 60ms in S3 resume time by skipping training empty slots. +} PCIE_TRAINING_ALGORITHM; + /// PCIe port configuration info typedef struct { PCIe_PORT_DATA PortData; ///< Port data @@ -165,7 +170,7 @@ typedef struct { * @li @b Bit31 - last descriptor on wrapper * @li @b Bit30 - Descriptor allocated for PCIe port or DDI */ - PPCIe_WRAPPER_CONFIG Wrapper; ///< Pointer to parent wrapper + VOID *Wrapper; ///< Pointer to parent wrapper PCIe_ENGINE_DATA EngineData; ///< Engine Data UINT32 InitStatus; ///< Initialization Status UINT8 Scratch; ///< Scratch pad @@ -196,9 +201,9 @@ typedef struct { UINT8 TxclkGatingPllPowerDown:1; ///< TXCLK clock gating PLL power down UINT8 PllOffInL1:1; ///< PLL off in L1 } Features; - PPCIe_ENGINE_CONFIG EngineList; ///< Pointer to Engine list - PPCIe_SILICON_CONFIG Silicon; ///< Pointer to parent silicon - PVOID FmWrapper; ///< Pointer to family Specific configuration data + VOID *EngineList; ///< Pointer to Engine list + VOID *Silicon; ///< Pointer to parent silicon + VOID *FmWrapper; ///< Pointer to family Specific configuration data } PCIe_WRAPPER_CONFIG; @@ -211,8 +216,8 @@ typedef struct { * @li @b Bit31 - last descriptor on complex */ PCI_ADDR Address; ///< PCI address of GNB host bridge - PPCIe_WRAPPER_CONFIG WrapperList; ///< Pointer to wrapper list - PVOID FmSilicon; ///< Pointer to family Specific configuration data + VOID *WrapperList; ///< Pointer to wrapper list + VOID *FmSilicon; ///< Pointer to family Specific configuration data } PCIe_SILICON_CONFIG; #define PcieSiliconGetWrapperList(mSiliconPtr) ((PCIe_WRAPPER_CONFIG *) (mSiliconPtr->WrapperList)) @@ -223,14 +228,14 @@ typedef struct { * @li @b Bit31 - last descriptor on platform */ UINT8 SocketId; ///< Processor socket ID - PPCIe_SILICON_CONFIG SiliconList; ///< Pointer to silicon list + VOID *SiliconList; ///< Pointer to silicon list } PCIe_COMPLEX_CONFIG; #define PcieComplexGetSiliconList(mComplexPtr) ((PCIe_SILICON_CONFIG *)(UINTN)((mComplexPtr)->SiliconList)) /// PCIe platform configuration info typedef struct { - PVOID StdHeader; ///< Standard configuration header + AMD_CONFIG_PARAMS *StdHeader; ///< Standard configuration header UINT64 This; ///< base structure Base UINT32 LinkReceiverDetectionPooling; ///< Receiver pooling detection time in us. UINT32 LinkL0Pooling; ///< Pooling for link to get to L0 in us @@ -238,6 +243,8 @@ typedef struct { UINT32 LinkResetToTrainingTime; ///< Time duration between deassert GPIO reset and release training in us /// UINT8 GfxCardWorkaround; ///< GFX Card Workaround UINT8 PsppPolicy; ///< PSPP policy + UINT8 TrainingExitState; ///< State at which training should exit (see PCIE_LINK_TRAINING_STATE) + UINT8 TrainingAlgorithm; ///< Training algorithm (see PCIE_TRAINING_ALGORITHM) PCIe_COMPLEX_CONFIG ComplexList[MAX_NUMBER_OF_COMPLEXES]; ///< } PCIe_PLATFORM_CONFIG; diff --git a/src/vendorcode/amd/agesa/f14/Proc/GNB/Common/GnbRegistersON.h b/src/vendorcode/amd/agesa/f14/Proc/GNB/Common/GnbRegistersON.h index 2095f0e925..c71eeddf9d 100644 --- a/src/vendorcode/amd/agesa/f14/Proc/GNB/Common/GnbRegistersON.h +++ b/src/vendorcode/amd/agesa/f14/Proc/GNB/Common/GnbRegistersON.h @@ -17,7 +17,7 @@ * * Copyright (c) 2011, Advanced Micro Devices, Inc. * All rights reserved. - * + * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions are met: * * Redistributions of source code must retain the above copyright @@ -28,7 +28,7 @@ * * Neither the name of Advanced Micro Devices, Inc. nor the names of * its contributors may be used to endorse or promote products derived * from this software without specific prior written permission. - * + * * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE @@ -1220,36 +1220,36 @@ typedef union { UINT32 Value; ///< } D18F2x80_STRUCT; -// **** D18F2x084 Register Definition **** +// **** D18F2x84 Register Definition **** // Address -#define D18F2x084_ADDRESS 0x84 +#define D18F2x84_ADDRESS 0x84 // Type -#define D18F2x084_TYPE TYPE_D18F2 +#define D18F2x84_TYPE TYPE_D18F2 // Field Data -#define D18F2x084_BurstCtrl_OFFSET 0 -#define D18F2x084_BurstCtrl_WIDTH 2 -#define D18F2x084_BurstCtrl_MASK 0x3 -#define D18F2x084_Reserved_3_2_OFFSET 2 -#define D18F2x084_Reserved_3_2_WIDTH 2 -#define D18F2x084_Reserved_3_2_MASK 0xc -#define D18F2x084_Twr_OFFSET 4 -#define D18F2x084_Twr_WIDTH 3 -#define D18F2x084_Twr_MASK 0x70 -#define D18F2x084_Reserved_19_7_OFFSET 7 -#define D18F2x084_Reserved_19_7_WIDTH 13 -#define D18F2x084_Reserved_19_7_MASK 0xfff80 -#define D18F2x084_Tcwl_OFFSET 20 -#define D18F2x084_Tcwl_WIDTH 3 -#define D18F2x084_Tcwl_MASK 0x700000 -#define D18F2x084_PchgPDModeSel_OFFSET 23 -#define D18F2x084_PchgPDModeSel_WIDTH 1 -#define D18F2x084_PchgPDModeSel_MASK 0x800000 -#define D18F2x084_Reserved_31_24_OFFSET 24 -#define D18F2x084_Reserved_31_24_WIDTH 8 -#define D18F2x084_Reserved_31_24_MASK 0xff000000 +#define D18F2x84_BurstCtrl_OFFSET 0 +#define D18F2x84_BurstCtrl_WIDTH 2 +#define D18F2x84_BurstCtrl_MASK 0x3 +#define D18F2x84_Reserved_3_2_OFFSET 2 +#define D18F2x84_Reserved_3_2_WIDTH 2 +#define D18F2x84_Reserved_3_2_MASK 0xc +#define D18F2x84_Twr_OFFSET 4 +#define D18F2x84_Twr_WIDTH 3 +#define D18F2x84_Twr_MASK 0x70 +#define D18F2x84_Reserved_19_7_OFFSET 7 +#define D18F2x84_Reserved_19_7_WIDTH 13 +#define D18F2x84_Reserved_19_7_MASK 0xfff80 +#define D18F2x84_Tcwl_OFFSET 20 +#define D18F2x84_Tcwl_WIDTH 3 +#define D18F2x84_Tcwl_MASK 0x700000 +#define D18F2x84_PchgPDModeSel_OFFSET 23 +#define D18F2x84_PchgPDModeSel_WIDTH 1 +#define D18F2x84_PchgPDModeSel_MASK 0x800000 +#define D18F2x84_Reserved_31_24_OFFSET 24 +#define D18F2x84_Reserved_31_24_WIDTH 8 +#define D18F2x84_Reserved_31_24_MASK 0xff000000 -/// D18F2x084 +/// D18F2x84 typedef union { struct { ///< UINT32 BurstCtrl:2 ; ///< @@ -1261,53 +1261,80 @@ typedef union { UINT32 Reserved_31_24:8 ; ///< } Field; ///< UINT32 Value; ///< -} D18F2x084_STRUCT; - -// **** D18F2x08C Register Definition **** -// Address -#define D18F2x08C_ADDRESS 0x8c - -// Type -#define D18F2x08C_TYPE TYPE_D18F2 -// Field Data -#define D18F2x08C_TrwtWB_OFFSET 0 -#define D18F2x08C_TrwtWB_WIDTH 4 -#define D18F2x08C_TrwtWB_MASK 0xf -#define D18F2x08C_TrwtTO_OFFSET 4 -#define D18F2x08C_TrwtTO_WIDTH 4 -#define D18F2x08C_TrwtTO_MASK 0xf0 -#define D18F2x08C_Reserved_9_8_OFFSET 8 -#define D18F2x08C_Reserved_9_8_WIDTH 2 -#define D18F2x08C_Reserved_9_8_MASK 0x300 -#define D18F2x08C_Twrrd_1_0__OFFSET 10 -#define D18F2x08C_Twrrd_1_0__WIDTH 2 -#define D18F2x08C_Twrrd_1_0__MASK 0xc00 -#define D18F2x08C_Twrwr_1_0__OFFSET 12 -#define D18F2x08C_Twrwr_1_0__WIDTH 2 -#define D18F2x08C_Twrwr_1_0__MASK 0x3000 -#define D18F2x08C_Trdrd_1_0__OFFSET 14 -#define D18F2x08C_Trdrd_1_0__WIDTH 2 -#define D18F2x08C_Trdrd_1_0__MASK 0xc000 -#define D18F2x08C_Tref_OFFSET 16 -#define D18F2x08C_Tref_WIDTH 2 -#define D18F2x08C_Tref_MASK 0x30000 -#define D18F2x08C_DisAutoRefresh_OFFSET 18 -#define D18F2x08C_DisAutoRefresh_WIDTH 1 -#define D18F2x08C_DisAutoRefresh_MASK 0x40000 -#define D18F2x08C_Reserved_19_19_OFFSET 19 -#define D18F2x08C_Reserved_19_19_WIDTH 1 -#define D18F2x08C_Reserved_19_19_MASK 0x80000 -#define D18F2x08C_Trfc0_OFFSET 20 -#define D18F2x08C_Trfc0_WIDTH 3 -#define D18F2x08C_Trfc0_MASK 0x700000 -#define D18F2x08C_Trfc1_OFFSET 23 -#define D18F2x08C_Trfc1_WIDTH 3 -#define D18F2x08C_Trfc1_MASK 0x3800000 -#define D18F2x08C_Reserved_31_26_OFFSET 26 -#define D18F2x08C_Reserved_31_26_WIDTH 6 -#define D18F2x08C_Reserved_31_26_MASK 0xfc000000 - -/// D18F2x08C +} D18F2x84_STRUCT; + +// **** D18F2x88 Register Definition **** +// Address +#define D18F2x88_ADDRESS 0x88 + +// Type +#define D18F2x88_TYPE TYPE_D18F2 +// Field Data +#define D18F2x88_Tcl_OFFSET 0 +#define D18F2x88_Tcl_WIDTH 4 +#define D18F2x88_Tcl_MASK 0xf +#define D18F2x88_Reserved_23_4_OFFSET 4 +#define D18F2x88_Reserved_23_4_WIDTH 20 +#define D18F2x88_Reserved_23_4_MASK 0xfffff0 +#define D18F2x88_MemClkDis_OFFSET 24 +#define D18F2x88_MemClkDis_WIDTH 8 +#define D18F2x88_MemClkDis_MASK 0xff000000 + +/// D18F2x88 +typedef union { + struct { ///< + UINT32 Tcl:4 ; ///< + UINT32 Reserved_23_4:20; ///< + UINT32 MemClkDis:8 ; ///< + } Field; ///< + UINT32 Value; ///< +} D18F2x88_STRUCT; + +// **** D18F2x8C Register Definition **** +// Address +#define D18F2x8C_ADDRESS 0x8c + +// Type +#define D18F2x8C_TYPE TYPE_D18F2 +// Field Data +#define D18F2x8C_TrwtWB_OFFSET 0 +#define D18F2x8C_TrwtWB_WIDTH 4 +#define D18F2x8C_TrwtWB_MASK 0xf +#define D18F2x8C_TrwtTO_OFFSET 4 +#define D18F2x8C_TrwtTO_WIDTH 4 +#define D18F2x8C_TrwtTO_MASK 0xf0 +#define D18F2x8C_Reserved_9_8_OFFSET 8 +#define D18F2x8C_Reserved_9_8_WIDTH 2 +#define D18F2x8C_Reserved_9_8_MASK 0x300 +#define D18F2x8C_Twrrd_1_0__OFFSET 10 +#define D18F2x8C_Twrrd_1_0__WIDTH 2 +#define D18F2x8C_Twrrd_1_0__MASK 0xc00 +#define D18F2x8C_Twrwr_1_0__OFFSET 12 +#define D18F2x8C_Twrwr_1_0__WIDTH 2 +#define D18F2x8C_Twrwr_1_0__MASK 0x3000 +#define D18F2x8C_Trdrd_1_0__OFFSET 14 +#define D18F2x8C_Trdrd_1_0__WIDTH 2 +#define D18F2x8C_Trdrd_1_0__MASK 0xc000 +#define D18F2x8C_Tref_OFFSET 16 +#define D18F2x8C_Tref_WIDTH 2 +#define D18F2x8C_Tref_MASK 0x30000 +#define D18F2x8C_DisAutoRefresh_OFFSET 18 +#define D18F2x8C_DisAutoRefresh_WIDTH 1 +#define D18F2x8C_DisAutoRefresh_MASK 0x40000 +#define D18F2x8C_Reserved_19_19_OFFSET 19 +#define D18F2x8C_Reserved_19_19_WIDTH 1 +#define D18F2x8C_Reserved_19_19_MASK 0x80000 +#define D18F2x8C_Trfc0_OFFSET 20 +#define D18F2x8C_Trfc0_WIDTH 3 +#define D18F2x8C_Trfc0_MASK 0x700000 +#define D18F2x8C_Trfc1_OFFSET 23 +#define D18F2x8C_Trfc1_WIDTH 3 +#define D18F2x8C_Trfc1_MASK 0x3800000 +#define D18F2x8C_Reserved_31_26_OFFSET 26 +#define D18F2x8C_Reserved_31_26_WIDTH 6 +#define D18F2x8C_Reserved_31_26_MASK 0xfc000000 + +/// D18F2x8C typedef union { struct { ///< UINT32 TrwtWB:4 ; ///< @@ -1324,56 +1351,56 @@ typedef union { UINT32 Reserved_31_26:6 ; ///< } Field; ///< UINT32 Value; ///< -} D18F2x08C_STRUCT; - -// **** D18F2x090 Register Definition **** -// Address -#define D18F2x090_ADDRESS 0x90 - -// Type -#define D18F2x090_TYPE TYPE_D18F2 -// Field Data -#define D18F2x090_Reserved_0_0_OFFSET 0 -#define D18F2x090_Reserved_0_0_WIDTH 1 -#define D18F2x090_Reserved_0_0_MASK 0x1 -#define D18F2x090_ExitSelfRef_OFFSET 1 -#define D18F2x090_ExitSelfRef_WIDTH 1 -#define D18F2x090_ExitSelfRef_MASK 0x2 -#define D18F2x090_Reserved_16_2_OFFSET 2 -#define D18F2x090_Reserved_16_2_WIDTH 15 -#define D18F2x090_Reserved_16_2_MASK 0x1fffc -#define D18F2x090_EnterSelfRef_OFFSET 17 -#define D18F2x090_EnterSelfRef_WIDTH 1 -#define D18F2x090_EnterSelfRef_MASK 0x20000 -#define D18F2x090_Reserved_19_18_OFFSET 18 -#define D18F2x090_Reserved_19_18_WIDTH 2 -#define D18F2x090_Reserved_19_18_MASK 0xc0000 -#define D18F2x090_DynPageCloseEn_OFFSET 20 -#define D18F2x090_DynPageCloseEn_WIDTH 1 -#define D18F2x090_DynPageCloseEn_MASK 0x100000 -#define D18F2x090_IdleCycInit_OFFSET 21 -#define D18F2x090_IdleCycInit_WIDTH 2 -#define D18F2x090_IdleCycInit_MASK 0x600000 -#define D18F2x090_ForceAutoPchg_OFFSET 23 -#define D18F2x090_ForceAutoPchg_WIDTH 1 -#define D18F2x090_ForceAutoPchg_MASK 0x800000 -#define D18F2x090_Reserved_24_24_OFFSET 24 -#define D18F2x090_Reserved_24_24_WIDTH 1 -#define D18F2x090_Reserved_24_24_MASK 0x1000000 -#define D18F2x090_EnDispAutoPrecharge_OFFSET 25 -#define D18F2x090_EnDispAutoPrecharge_WIDTH 1 -#define D18F2x090_EnDispAutoPrecharge_MASK 0x2000000 -#define D18F2x090_DbeSkidBufDis_OFFSET 26 -#define D18F2x090_DbeSkidBufDis_WIDTH 1 -#define D18F2x090_DbeSkidBufDis_MASK 0x4000000 -#define D18F2x090_DisDllShutdownSR_OFFSET 27 -#define D18F2x090_DisDllShutdownSR_WIDTH 1 -#define D18F2x090_DisDllShutdownSR_MASK 0x8000000 -#define D18F2x090_Reserved_31_28_OFFSET 28 -#define D18F2x090_Reserved_31_28_WIDTH 4 -#define D18F2x090_Reserved_31_28_MASK 0xf0000000 - -/// D18F2x090 +} D18F2x8C_STRUCT; + +// **** D18F2x90 Register Definition **** +// Address +#define D18F2x90_ADDRESS 0x90 + +// Type +#define D18F2x90_TYPE TYPE_D18F2 +// Field Data +#define D18F2x90_Reserved_0_0_OFFSET 0 +#define D18F2x90_Reserved_0_0_WIDTH 1 +#define D18F2x90_Reserved_0_0_MASK 0x1 +#define D18F2x90_ExitSelfRef_OFFSET 1 +#define D18F2x90_ExitSelfRef_WIDTH 1 +#define D18F2x90_ExitSelfRef_MASK 0x2 +#define D18F2x90_Reserved_16_2_OFFSET 2 +#define D18F2x90_Reserved_16_2_WIDTH 15 +#define D18F2x90_Reserved_16_2_MASK 0x1fffc +#define D18F2x90_EnterSelfRef_OFFSET 17 +#define D18F2x90_EnterSelfRef_WIDTH 1 +#define D18F2x90_EnterSelfRef_MASK 0x20000 +#define D18F2x90_Reserved_19_18_OFFSET 18 +#define D18F2x90_Reserved_19_18_WIDTH 2 +#define D18F2x90_Reserved_19_18_MASK 0xc0000 +#define D18F2x90_DynPageCloseEn_OFFSET 20 +#define D18F2x90_DynPageCloseEn_WIDTH 1 +#define D18F2x90_DynPageCloseEn_MASK 0x100000 +#define D18F2x90_IdleCycInit_OFFSET 21 +#define D18F2x90_IdleCycInit_WIDTH 2 +#define D18F2x90_IdleCycInit_MASK 0x600000 +#define D18F2x90_ForceAutoPchg_OFFSET 23 +#define D18F2x90_ForceAutoPchg_WIDTH 1 +#define D18F2x90_ForceAutoPchg_MASK 0x800000 +#define D18F2x90_Reserved_24_24_OFFSET 24 +#define D18F2x90_Reserved_24_24_WIDTH 1 +#define D18F2x90_Reserved_24_24_MASK 0x1000000 +#define D18F2x90_EnDispAutoPrecharge_OFFSET 25 +#define D18F2x90_EnDispAutoPrecharge_WIDTH 1 +#define D18F2x90_EnDispAutoPrecharge_MASK 0x2000000 +#define D18F2x90_DbeSkidBufDis_OFFSET 26 +#define D18F2x90_DbeSkidBufDis_WIDTH 1 +#define D18F2x90_DbeSkidBufDis_MASK 0x4000000 +#define D18F2x90_DisDllShutdownSR_OFFSET 27 +#define D18F2x90_DisDllShutdownSR_WIDTH 1 +#define D18F2x90_DisDllShutdownSR_MASK 0x8000000 +#define D18F2x90_Reserved_31_28_OFFSET 28 +#define D18F2x90_Reserved_31_28_WIDTH 4 +#define D18F2x90_Reserved_31_28_MASK 0xf0000000 + +/// D18F2x90 typedef union { struct { ///< UINT32 Reserved_0_0:1 ; ///< @@ -1391,12 +1418,172 @@ typedef union { UINT32 Reserved_31_28:4 ; ///< } Field; ///< UINT32 Value; ///< -} D18F2x090_STRUCT; +} D18F2x90_STRUCT; + +// **** D18F2x94 Register Definition **** +// Address +#define D18F2x94_ADDRESS 0x94 + +// Type +#define D18F2x94_TYPE TYPE_D18F2 +// Field Data +#define D18F2x94_MemClkFreq_OFFSET 0 +#define D18F2x94_MemClkFreq_WIDTH 5 +#define D18F2x94_MemClkFreq_MASK 0x1f +#define D18F2x94_Reserved_6_5_OFFSET 5 +#define D18F2x94_Reserved_6_5_WIDTH 2 +#define D18F2x94_Reserved_6_5_MASK 0x60 +#define D18F2x94_MemClkFreqVal_OFFSET 7 +#define D18F2x94_MemClkFreqVal_WIDTH 1 +#define D18F2x94_MemClkFreqVal_MASK 0x80 +#define D18F2x94_Reserved_9_8_OFFSET 8 +#define D18F2x94_Reserved_9_8_WIDTH 2 +#define D18F2x94_Reserved_9_8_MASK 0x300 +#define D18F2x94_ZqcsInterval_OFFSET 10 +#define D18F2x94_ZqcsInterval_WIDTH 2 +#define D18F2x94_ZqcsInterval_MASK 0xc00 +#define D18F2x94_Reserved_13_12_OFFSET 12 +#define D18F2x94_Reserved_13_12_WIDTH 2 +#define D18F2x94_Reserved_13_12_MASK 0x3000 +#define D18F2x94_DisDramInterface_OFFSET 14 +#define D18F2x94_DisDramInterface_WIDTH 1 +#define D18F2x94_DisDramInterface_MASK 0x4000 +#define D18F2x94_PowerDownEn_OFFSET 15 +#define D18F2x94_PowerDownEn_WIDTH 1 +#define D18F2x94_PowerDownEn_MASK 0x8000 +#define D18F2x94_PowerDownMode_OFFSET 16 +#define D18F2x94_PowerDownMode_WIDTH 1 +#define D18F2x94_PowerDownMode_MASK 0x10000 +#define D18F2x94_Reserved_19_17_OFFSET 17 +#define D18F2x94_Reserved_19_17_WIDTH 3 +#define D18F2x94_Reserved_19_17_MASK 0xe0000 +#define D18F2x94_SlowAccessMode_OFFSET 20 +#define D18F2x94_SlowAccessMode_WIDTH 1 +#define D18F2x94_SlowAccessMode_MASK 0x100000 +#define D18F2x94_Reserved_21_21_OFFSET 21 +#define D18F2x94_Reserved_21_21_WIDTH 1 +#define D18F2x94_Reserved_21_21_MASK 0x200000 +#define D18F2x94_BankSwizzleMode_OFFSET 22 +#define D18F2x94_BankSwizzleMode_WIDTH 1 +#define D18F2x94_BankSwizzleMode_MASK 0x400000 +#define D18F2x94_ProcOdtDis_OFFSET 23 +#define D18F2x94_ProcOdtDis_WIDTH 1 +#define D18F2x94_ProcOdtDis_MASK 0x800000 +#define D18F2x94_DcqBypassMax_OFFSET 24 +#define D18F2x94_DcqBypassMax_WIDTH 4 +#define D18F2x94_DcqBypassMax_MASK 0xf000000 +#define D18F2x94_FourActWindow_OFFSET 28 +#define D18F2x94_FourActWindow_WIDTH 4 +#define D18F2x94_FourActWindow_MASK 0xf0000000 + +/// D18F2x94 +typedef union { + struct { ///< + UINT32 MemClkFreq:5 ; ///< + UINT32 Reserved_6_5:2 ; ///< + UINT32 MemClkFreqVal:1 ; ///< + UINT32 Reserved_9_8:2 ; ///< + UINT32 ZqcsInterval:2 ; ///< + UINT32 Reserved_13_12:3 ; ///< + UINT32 DisDramInterface:1 ; ///< + UINT32 PowerDownEn:1 ; ///< + UINT32 PowerDownMode:1 ; ///< + UINT32 Reserved_19_17:3 ; ///< + UINT32 SlowAccessMode:1 ; ///< + UINT32 Reserved_21_21:1 ; ///< + UINT32 BankSwizzleMode:1 ; ///< + UINT32 ProcOdtDis:1 ; ///< + UINT32 DcqBypassMax:4 ; ///< + UINT32 FourActWindow:4 ; ///< + } Field; ///< + UINT32 Value; ///< +} D18F2x94_STRUCT; + +// **** D18F2x98 Register Definition **** +// Address +#define D18F2x98_ADDRESS 0x98 + +// Type +#define D18F2x98_TYPE TYPE_D18F2 +// Field Data +#define D18F2x98_DctOffset_OFFSET 0 +#define D18F2x98_DctOffset_WIDTH 30 +#define D18F2x98_DctOffset_MASK 0x3fffffff +#define D18F2x98_DctAccessWrite_OFFSET 30 +#define D18F2x98_DctAccessWrite_WIDTH 1 +#define D18F2x98_DctAccessWrite_MASK 0x40000000 +#define D18F2x98_DctAccessDone_OFFSET 31 +#define D18F2x98_DctAccessDone_WIDTH 1 +#define D18F2x98_DctAccessDone_MASK 0x80000000 + +/// D18F2x98 +typedef union { + struct { ///< + UINT32 DctOffset:30; ///< + UINT32 DctAccessWrite:1 ; ///< + UINT32 DctAccessDone:1 ; ///< + } Field; ///< + UINT32 Value; ///< +} D18F2x98_STRUCT; // **** D18F2x9C Register Definition **** // Address #define D18F2x9C_ADDRESS 0x9c +// Type +#define D18F2x9C_TYPE TYPE_D18F2 +// Field Data +#define D18F2x9C_DctDataPort_OFFSET 0 +#define D18F2x9C_DctDataPort_WIDTH 32 +#define D18F2x9C_DctDataPort_MASK 0xffffffff + +/// D18F2x9C +typedef union { + struct { ///< + UINT32 DctDataPort:32; ///< + } Field; ///< + UINT32 Value; ///< +} D18F2x9C_STRUCT; + +// **** D18F2x09C_x0D0FE00A Register Definition **** +// Address +#define D18F2x09C_x0D0FE00A_ADDRESS 0x0D0FE00A + +// Type +#define D18F2x09C_x0D0FE00A_TYPE TYPE_D18F2x9C +// Field Data +#define D18F2x09C_x0D0FE00A_Reserved_3_0_OFFSET 0 +#define D18F2x09C_x0D0FE00A_Reserved_3_0_WIDTH 4 +#define D18F2x09C_x0D0FE00A_Reserved_3_0_MASK 0xF +#define D18F2x09C_x0D0FE00A_SkewMemClk_OFFSET 4 +#define D18F2x09C_x0D0FE00A_SkewMemClk_WIDTH 1 +#define D18F2x09C_x0D0FE00A_SkewMemClk_MASK 0x10 +#define D18F2x09C_x0D0FE00A_Reserved_11_5_OFFSET 5 +#define D18F2x09C_x0D0FE00A_Reserved_11_5_WIDTH 7 +#define D18F2x09C_x0D0FE00A_Reserved_11_5_MASK 0xFE0 +#define D18F2x09C_x0D0FE00A_CsrPhySrPllPdMode_OFFSET 12 +#define D18F2x09C_x0D0FE00A_CsrPhySrPllPdMode_WIDTH 2 +#define D18F2x09C_x0D0FE00A_CsrPhySrPllPdMode_MASK 0x3000 +#define D18F2x09C_x0D0FE00A_SelCsrPllPdMode_OFFSET 14 +#define D18F2x09C_x0D0FE00A_SelCsrPllPdMode_WIDTH 1 +#define D18F2x09C_x0D0FE00A_SelCsrPllPdMode_MASK 0x4000 +#define D18F2x09C_x0D0FE00A_Reserved_31_15_OFFSET 15 +#define D18F2x09C_x0D0FE00A_Reserved_31_15_WIDTH 17 +#define D18F2x09C_x0D0FE00A_Reserved_31_15_MASK 0xFFFF8000 + +/// D18F2x09C_x0D0FE00A +typedef union { + struct { ///< + UINT32 Reserved_3_0:4; ///< + UINT32 SkewMemClk:1; ///< + UINT32 Reserved_11_5:7; ///< + UINT32 CsrPhySrPllPdMode:2; ///< + UINT32 SelCsrPllPdMode:1; ///< + UINT32 Reserved_31_15:17; ///< + } Field; ///< + UINT32 Value; ///< +} D18F2x09C_x0D0FE00A_STRUCT; + // **** D18F2xA0 Register Definition **** // Address #define D18F2xA0_ADDRESS 0xa0 @@ -1497,6 +1684,542 @@ typedef union { UINT32 Value; ///< } D18F2xAC_STRUCT; +// **** D18F2xB0 Register Definition **** +// Address +#define D18F2xB0_ADDRESS 0xb0 + +// Type +#define D18F2xB0_TYPE TYPE_D18F2 +// Field Data +#define D18F2xB0_TscLow_OFFSET 0 +#define D18F2xB0_TscLow_WIDTH 32 +#define D18F2xB0_TscLow_MASK 0xffffffff + +/// D18F2xB0 +typedef union { + struct { ///< + UINT32 TscLow:32; ///< + } Field; ///< + UINT32 Value; ///< +} D18F2xB0_STRUCT; + +// **** D18F2xB4 Register Definition **** +// Address +#define D18F2xB4_ADDRESS 0xb4 + +// Type +#define D18F2xB4_TYPE TYPE_D18F2 +// Field Data +#define D18F2xB4_TscHigh_OFFSET 0 +#define D18F2xB4_TscHigh_WIDTH 32 +#define D18F2xB4_TscHigh_MASK 0xffffffff + +/// D18F2xB4 +typedef union { + struct { ///< + UINT32 TscHigh:32; ///< + } Field; ///< + UINT32 Value; ///< +} D18F2xB4_STRUCT; + +// **** D18F2xB8 Register Definition **** +// Address +#define D18F2xB8_ADDRESS 0xb8 + +// Type +#define D18F2xB8_TYPE TYPE_D18F2 +// Field Data +#define D18F2xB8_TrcBufDramBase_35_24__OFFSET 0 +#define D18F2xB8_TrcBufDramBase_35_24__WIDTH 12 +#define D18F2xB8_TrcBufDramBase_35_24__MASK 0xfff +#define D18F2xB8_TrcBufDramBase_39_36__OFFSET 12 +#define D18F2xB8_TrcBufDramBase_39_36__WIDTH 4 +#define D18F2xB8_TrcBufDramBase_39_36__MASK 0xf000 +#define D18F2xB8_TrcBufDramLimit_35_24__OFFSET 16 +#define D18F2xB8_TrcBufDramLimit_35_24__WIDTH 12 +#define D18F2xB8_TrcBufDramLimit_35_24__MASK 0xfff0000 +#define D18F2xB8_TrcBufDramLimit_39_36__OFFSET 28 +#define D18F2xB8_TrcBufDramLimit_39_36__WIDTH 4 +#define D18F2xB8_TrcBufDramLimit_39_36__MASK 0xf0000000 + +/// D18F2xB8 +typedef union { + struct { ///< + UINT32 TrcBufDramBase_35_24_:12; ///< + UINT32 TrcBufDramBase_39_36_:4 ; ///< + UINT32 TrcBufDramLimit_35_24_:12; ///< + UINT32 TrcBufDramLimit_39_36_:4 ; ///< + } Field; ///< + UINT32 Value; ///< +} D18F2xB8_STRUCT; + +// **** D18F2xBC Register Definition **** +// Address +#define D18F2xBC_ADDRESS 0xbc + +// Type +#define D18F2xBC_TYPE TYPE_D18F2 +// Field Data +#define D18F2xBC_TrcBufAdrPtr_35_6__OFFSET 0 +#define D18F2xBC_TrcBufAdrPtr_35_6__WIDTH 30 +#define D18F2xBC_TrcBufAdrPtr_35_6__MASK 0x3fffffff +#define D18F2xBC_TrcBufAdrPtr_37_36__OFFSET 30 +#define D18F2xBC_TrcBufAdrPtr_37_36__WIDTH 2 +#define D18F2xBC_TrcBufAdrPtr_37_36__MASK 0xc0000000 + +/// D18F2xBC +typedef union { + struct { ///< + UINT32 TrcBufAdrPtr_35_6_:30; ///< + UINT32 TrcBufAdrPtr_37_36_:2 ; ///< + } Field; ///< + UINT32 Value; ///< +} D18F2xBC_STRUCT; + +// **** D18F2xC0 Register Definition **** +// Address +#define D18F2xC0_ADDRESS 0xc0 + +// Type +#define D18F2xC0_TYPE TYPE_D18F2 +// Field Data +#define D18F2xC0_TraceModeEn_OFFSET 0 +#define D18F2xC0_TraceModeEn_WIDTH 1 +#define D18F2xC0_TraceModeEn_MASK 0x1 +#define D18F2xC0_TcbModeEn_OFFSET 1 +#define D18F2xC0_TcbModeEn_WIDTH 1 +#define D18F2xC0_TcbModeEn_MASK 0x2 +#define D18F2xC0_Reserved_3_2_OFFSET 2 +#define D18F2xC0_Reserved_3_2_WIDTH 2 +#define D18F2xC0_Reserved_3_2_MASK 0xc +#define D18F2xC0_ncHTEn0_OFFSET 4 +#define D18F2xC0_ncHTEn0_WIDTH 1 +#define D18F2xC0_ncHTEn0_MASK 0x10 +#define D18F2xC0_ncHTEn1_OFFSET 5 +#define D18F2xC0_ncHTEn1_WIDTH 1 +#define D18F2xC0_ncHTEn1_MASK 0x20 +#define D18F2xC0_Reserved_11_6_OFFSET 6 +#define D18F2xC0_Reserved_11_6_WIDTH 6 +#define D18F2xC0_Reserved_11_6_MASK 0xfc0 +#define D18F2xC0_FlushTcb_OFFSET 12 +#define D18F2xC0_FlushTcb_WIDTH 1 +#define D18F2xC0_FlushTcb_MASK 0x1000 +#define D18F2xC0_Reserved_14_13_OFFSET 13 +#define D18F2xC0_Reserved_14_13_WIDTH 2 +#define D18F2xC0_Reserved_14_13_MASK 0x6000 +#define D18F2xC0_TraceCmdMtchReq_OFFSET 15 +#define D18F2xC0_TraceCmdMtchReq_WIDTH 1 +#define D18F2xC0_TraceCmdMtchReq_MASK 0x8000 +#define D18F2xC0_Reserved_17_16_OFFSET 16 +#define D18F2xC0_Reserved_17_16_WIDTH 2 +#define D18F2xC0_Reserved_17_16_MASK 0x30000 +#define D18F2xC0_MultiLevelSingleEvent_OFFSET 18 +#define D18F2xC0_MultiLevelSingleEvent_WIDTH 1 +#define D18F2xC0_MultiLevelSingleEvent_MASK 0x40000 +#define D18F2xC0_MultiLevelMultiEvent_OFFSET 19 +#define D18F2xC0_MultiLevelMultiEvent_WIDTH 1 +#define D18F2xC0_MultiLevelMultiEvent_MASK 0x80000 +#define D18F2xC0_Reserved_20_20_OFFSET 20 +#define D18F2xC0_Reserved_20_20_WIDTH 1 +#define D18F2xC0_Reserved_20_20_MASK 0x100000 +#define D18F2xC0_TraceSrcDstAndEn_OFFSET 21 +#define D18F2xC0_TraceSrcDstAndEn_WIDTH 1 +#define D18F2xC0_TraceSrcDstAndEn_MASK 0x200000 +#define D18F2xC0_TraceFlushOnDbReq_OFFSET 22 +#define D18F2xC0_TraceFlushOnDbReq_WIDTH 1 +#define D18F2xC0_TraceFlushOnDbReq_MASK 0x400000 +#define D18F2xC0_TraceOneShotEn_OFFSET 23 +#define D18F2xC0_TraceOneShotEn_WIDTH 1 +#define D18F2xC0_TraceOneShotEn_MASK 0x800000 +#define D18F2xC0_Reserved_31_24_OFFSET 24 +#define D18F2xC0_Reserved_31_24_WIDTH 8 +#define D18F2xC0_Reserved_31_24_MASK 0xff000000 + +/// D18F2xC0 +typedef union { + struct { ///< + UINT32 TraceModeEn:1 ; ///< + UINT32 TcbModeEn:1 ; ///< + UINT32 Reserved_3_2:2 ; ///< + UINT32 ncHTEn0:1 ; ///< + UINT32 ncHTEn1:1 ; ///< + UINT32 Reserved_11_6:6 ; ///< + UINT32 FlushTcb:1 ; ///< + UINT32 Reserved_14_13:2 ; ///< + UINT32 TraceCmdMtchReq:1 ; ///< + UINT32 Reserved_17_16:2 ; ///< + UINT32 MultiLevelSingleEvent:1 ; ///< + UINT32 MultiLevelMultiEvent:1 ; ///< + UINT32 Reserved_20_20:1 ; ///< + UINT32 TraceSrcDstAndEn:1 ; ///< + UINT32 TraceFlushOnDbReq:1 ; ///< + UINT32 TraceOneShotEn:1 ; ///< + UINT32 Reserved_31_24:8 ; ///< + } Field; ///< + UINT32 Value; ///< +} D18F2xC0_STRUCT; + +// **** D18F2xC4 Register Definition **** +// Address +#define D18F2xC4_ADDRESS 0xc4 + +// Type +#define D18F2xC4_TYPE TYPE_D18F2 +// Field Data +#define D18F2xC4_StartCmd0_OFFSET 0 +#define D18F2xC4_StartCmd0_WIDTH 1 +#define D18F2xC4_StartCmd0_MASK 0x1 +#define D18F2xC4_StartCmd1_OFFSET 1 +#define D18F2xC4_StartCmd1_WIDTH 1 +#define D18F2xC4_StartCmd1_MASK 0x2 +#define D18F2xC4_Reserved_21_2_OFFSET 2 +#define D18F2xC4_Reserved_21_2_WIDTH 20 +#define D18F2xC4_Reserved_21_2_MASK 0x3ffffc +#define D18F2xC4_StartDbRdy_OFFSET 22 +#define D18F2xC4_StartDbRdy_WIDTH 1 +#define D18F2xC4_StartDbRdy_MASK 0x400000 +#define D18F2xC4_StartDbReq_OFFSET 23 +#define D18F2xC4_StartDbReq_WIDTH 1 +#define D18F2xC4_StartDbReq_MASK 0x800000 +#define D18F2xC4_StartPerfMon0_OFFSET 24 +#define D18F2xC4_StartPerfMon0_WIDTH 1 +#define D18F2xC4_StartPerfMon0_MASK 0x1000000 +#define D18F2xC4_StartPerfMon1_OFFSET 25 +#define D18F2xC4_StartPerfMon1_WIDTH 1 +#define D18F2xC4_StartPerfMon1_MASK 0x2000000 +#define D18F2xC4_StartPerfMon2_OFFSET 26 +#define D18F2xC4_StartPerfMon2_WIDTH 1 +#define D18F2xC4_StartPerfMon2_MASK 0x4000000 +#define D18F2xC4_StartPerfMon3_OFFSET 27 +#define D18F2xC4_StartPerfMon3_WIDTH 1 +#define D18F2xC4_StartPerfMon3_MASK 0x8000000 +#define D18F2xC4_StartMCE_OFFSET 28 +#define D18F2xC4_StartMCE_WIDTH 1 +#define D18F2xC4_StartMCE_MASK 0x10000000 +#define D18F2xC4_Reserved_29_29_OFFSET 29 +#define D18F2xC4_Reserved_29_29_WIDTH 1 +#define D18F2xC4_Reserved_29_29_MASK 0x20000000 +#define D18F2xC4_StartTSC_OFFSET 30 +#define D18F2xC4_StartTSC_WIDTH 1 +#define D18F2xC4_StartTSC_MASK 0x40000000 +#define D18F2xC4_StartNow_OFFSET 31 +#define D18F2xC4_StartNow_WIDTH 1 +#define D18F2xC4_StartNow_MASK 0x80000000 + +/// D18F2xC4 +typedef union { + struct { ///< + UINT32 StartCmd0:1 ; ///< + UINT32 StartCmd1:1 ; ///< + UINT32 Reserved_21_2:20; ///< + UINT32 StartDbRdy:1 ; ///< + UINT32 StartDbReq:1 ; ///< + UINT32 StartPerfMon0:1 ; ///< + UINT32 StartPerfMon1:1 ; ///< + UINT32 StartPerfMon2:1 ; ///< + UINT32 StartPerfMon3:1 ; ///< + UINT32 StartMCE:1 ; ///< + UINT32 Reserved_29_29:1 ; ///< + UINT32 StartTSC:1 ; ///< + UINT32 StartNow:1 ; ///< + } Field; ///< + UINT32 Value; ///< +} D18F2xC4_STRUCT; + +// **** D18F2xC8 Register Definition **** +// Address +#define D18F2xC8_ADDRESS 0xc8 + +// Type +#define D18F2xC8_TYPE TYPE_D18F2 +// Field Data +#define D18F2xC8_StopCmd0_OFFSET 0 +#define D18F2xC8_StopCmd0_WIDTH 1 +#define D18F2xC8_StopCmd0_MASK 0x1 +#define D18F2xC8_StopCmd1_OFFSET 1 +#define D18F2xC8_StopCmd1_WIDTH 1 +#define D18F2xC8_StopCmd1_MASK 0x2 +#define D18F2xC8_Reserved_21_2_OFFSET 2 +#define D18F2xC8_Reserved_21_2_WIDTH 20 +#define D18F2xC8_Reserved_21_2_MASK 0x3ffffc +#define D18F2xC8_StopDbRdy_OFFSET 22 +#define D18F2xC8_StopDbRdy_WIDTH 1 +#define D18F2xC8_StopDbRdy_MASK 0x400000 +#define D18F2xC8_StopDbReq_OFFSET 23 +#define D18F2xC8_StopDbReq_WIDTH 1 +#define D18F2xC8_StopDbReq_MASK 0x800000 +#define D18F2xC8_StopPerfMon0_OFFSET 24 +#define D18F2xC8_StopPerfMon0_WIDTH 1 +#define D18F2xC8_StopPerfMon0_MASK 0x1000000 +#define D18F2xC8_StopPerfMon1_OFFSET 25 +#define D18F2xC8_StopPerfMon1_WIDTH 1 +#define D18F2xC8_StopPerfMon1_MASK 0x2000000 +#define D18F2xC8_StopPerfMon2_OFFSET 26 +#define D18F2xC8_StopPerfMon2_WIDTH 1 +#define D18F2xC8_StopPerfMon2_MASK 0x4000000 +#define D18F2xC8_StopPerfMon3_OFFSET 27 +#define D18F2xC8_StopPerfMon3_WIDTH 1 +#define D18F2xC8_StopPerfMon3_MASK 0x8000000 +#define D18F2xC8_StopMCE_OFFSET 28 +#define D18F2xC8_StopMCE_WIDTH 1 +#define D18F2xC8_StopMCE_MASK 0x10000000 +#define D18F2xC8_StopTrcBufFull_OFFSET 29 +#define D18F2xC8_StopTrcBufFull_WIDTH 1 +#define D18F2xC8_StopTrcBufFull_MASK 0x20000000 +#define D18F2xC8_StopTSC_OFFSET 30 +#define D18F2xC8_StopTSC_WIDTH 1 +#define D18F2xC8_StopTSC_MASK 0x40000000 +#define D18F2xC8_StopNow_OFFSET 31 +#define D18F2xC8_StopNow_WIDTH 1 +#define D18F2xC8_StopNow_MASK 0x80000000 + +/// D18F2xC8 +typedef union { + struct { ///< + UINT32 StopCmd0:1 ; ///< + UINT32 StopCmd1:1 ; ///< + UINT32 Reserved_21_2:20; ///< + UINT32 StopDbRdy:1 ; ///< + UINT32 StopDbReq:1 ; ///< + UINT32 StopPerfMon0:1 ; ///< + UINT32 StopPerfMon1:1 ; ///< + UINT32 StopPerfMon2:1 ; ///< + UINT32 StopPerfMon3:1 ; ///< + UINT32 StopMCE:1 ; ///< + UINT32 StopTrcBufFull:1 ; ///< + UINT32 StopTSC:1 ; ///< + UINT32 StopNow:1 ; ///< + } Field; ///< + UINT32 Value; ///< +} D18F2xC8_STRUCT; + +// **** D18F2xCC Register Definition **** +// Address +#define D18F2xCC_ADDRESS 0xcc + +// Type +#define D18F2xCC_TYPE TYPE_D18F2 +// Field Data +#define D18F2xCC_TrcCmd0_OFFSET 0 +#define D18F2xCC_TrcCmd0_WIDTH 1 +#define D18F2xCC_TrcCmd0_MASK 0x1 +#define D18F2xCC_TrcCmd1_OFFSET 1 +#define D18F2xCC_TrcCmd1_WIDTH 1 +#define D18F2xCC_TrcCmd1_MASK 0x2 +#define D18F2xCC_Reserved_3_2_OFFSET 2 +#define D18F2xCC_Reserved_3_2_WIDTH 2 +#define D18F2xCC_Reserved_3_2_MASK 0xc +#define D18F2xCC_TrcRsp0_OFFSET 4 +#define D18F2xCC_TrcRsp0_WIDTH 1 +#define D18F2xCC_TrcRsp0_MASK 0x10 +#define D18F2xCC_TrcRsp1_OFFSET 5 +#define D18F2xCC_TrcRsp1_WIDTH 1 +#define D18F2xCC_TrcRsp1_MASK 0x20 +#define D18F2xCC_Reserved_11_6_OFFSET 6 +#define D18F2xCC_Reserved_11_6_WIDTH 6 +#define D18F2xCC_Reserved_11_6_MASK 0xfc0 +#define D18F2xCC_TrcDat0_OFFSET 12 +#define D18F2xCC_TrcDat0_WIDTH 1 +#define D18F2xCC_TrcDat0_MASK 0x1000 +#define D18F2xCC_TrcDat1_OFFSET 13 +#define D18F2xCC_TrcDat1_WIDTH 1 +#define D18F2xCC_TrcDat1_MASK 0x2000 +#define D18F2xCC_MultiDatXbarSel_OFFSET 14 +#define D18F2xCC_MultiDatXbarSel_WIDTH 1 +#define D18F2xCC_MultiDatXbarSel_MASK 0x4000 +#define D18F2xCC_TrcCmdSrcPtr_OFFSET 15 +#define D18F2xCC_TrcCmdSrcPtr_WIDTH 7 +#define D18F2xCC_TrcCmdSrcPtr_MASK 0x3f8000 +#define D18F2xCC_MultiTscCapture_OFFSET 22 +#define D18F2xCC_MultiTscCapture_WIDTH 1 +#define D18F2xCC_MultiTscCapture_MASK 0x400000 +#define D18F2xCC_TscBase_OFFSET 23 +#define D18F2xCC_TscBase_WIDTH 1 +#define D18F2xCC_TscBase_MASK 0x800000 +#define D18F2xCC_TrcCmdDstPtr_OFFSET 24 +#define D18F2xCC_TrcCmdDstPtr_WIDTH 6 +#define D18F2xCC_TrcCmdDstPtr_MASK 0x3f000000 +#define D18F2xCC_DisTscCapture_OFFSET 30 +#define D18F2xCC_DisTscCapture_WIDTH 1 +#define D18F2xCC_DisTscCapture_MASK 0x40000000 +#define D18F2xCC_TrcDatSrcDst_OFFSET 31 +#define D18F2xCC_TrcDatSrcDst_WIDTH 1 +#define D18F2xCC_TrcDatSrcDst_MASK 0x80000000 + +/// D18F2xCC +typedef union { + struct { ///< + UINT32 TrcCmd0:1 ; ///< + UINT32 TrcCmd1:1 ; ///< + UINT32 Reserved_3_2:2 ; ///< + UINT32 TrcRsp0:1 ; ///< + UINT32 TrcRsp1:1 ; ///< + UINT32 Reserved_11_6:6 ; ///< + UINT32 TrcDat0:1 ; ///< + UINT32 TrcDat1:1 ; ///< + UINT32 MultiDatXbarSel:1 ; ///< + UINT32 TrcCmdSrcPtr:7 ; ///< + UINT32 MultiTscCapture:1 ; ///< + UINT32 TscBase:1 ; ///< + UINT32 TrcCmdDstPtr:6 ; ///< + UINT32 DisTscCapture:1 ; ///< + UINT32 TrcDatSrcDst:1 ; ///< + } Field; ///< + UINT32 Value; ///< +} D18F2xCC_STRUCT; + +// **** D18F2xD0 Register Definition **** +// Address +#define D18F2xD0_ADDRESS 0xd0 + +// Type +#define D18F2xD0_TYPE TYPE_D18F2 +// Field Data +#define D18F2xD0_HTCmdLow_OFFSET 0 +#define D18F2xD0_HTCmdLow_WIDTH 32 +#define D18F2xD0_HTCmdLow_MASK 0xffffffff + +/// D18F2xD0 +typedef union { + struct { ///< + UINT32 HTCmdLow:32; ///< + } Field; ///< + UINT32 Value; ///< +} D18F2xD0_STRUCT; + +// **** D18F2xD4 Register Definition **** +// Address +#define D18F2xD4_ADDRESS 0xd4 + +// Type +#define D18F2xD4_TYPE TYPE_D18F2 +// Field Data +#define D18F2xD4_HTCmdHigh_OFFSET 0 +#define D18F2xD4_HTCmdHigh_WIDTH 32 +#define D18F2xD4_HTCmdHigh_MASK 0xffffffff + +/// D18F2xD4 +typedef union { + struct { ///< + UINT32 HTCmdHigh:32; ///< + } Field; ///< + UINT32 Value; ///< +} D18F2xD4_STRUCT; + +// **** D18F2xD8 Register Definition **** +// Address +#define D18F2xD8_ADDRESS 0xd8 + +// Type +#define D18F2xD8_TYPE TYPE_D18F2 +// Field Data +#define D18F2xD8_HTMaskLow_OFFSET 0 +#define D18F2xD8_HTMaskLow_WIDTH 32 +#define D18F2xD8_HTMaskLow_MASK 0xffffffff + +/// D18F2xD8 +typedef union { + struct { ///< + UINT32 HTMaskLow:32; ///< + } Field; ///< + UINT32 Value; ///< +} D18F2xD8_STRUCT; + +// **** D18F2xDC Register Definition **** +// Address +#define D18F2xDC_ADDRESS 0xdc + +// Type +#define D18F2xDC_TYPE TYPE_D18F2 +// Field Data +#define D18F2xDC_HTMaskHigh_OFFSET 0 +#define D18F2xDC_HTMaskHigh_WIDTH 32 +#define D18F2xDC_HTMaskHigh_MASK 0xffffffff + +/// D18F2xDC +typedef union { + struct { ///< + UINT32 HTMaskHigh:32; ///< + } Field; ///< + UINT32 Value; ///< +} D18F2xDC_STRUCT; + +// **** D18F2xE0 Register Definition **** +// Address +#define D18F2xE0_ADDRESS 0xe0 + +// Type +#define D18F2xE0_TYPE TYPE_D18F2 +// Field Data +#define D18F2xE0_HTCmdLow_OFFSET 0 +#define D18F2xE0_HTCmdLow_WIDTH 32 +#define D18F2xE0_HTCmdLow_MASK 0xffffffff + +/// D18F2xE0 +typedef union { + struct { ///< + UINT32 HTCmdLow:32; ///< + } Field; ///< + UINT32 Value; ///< +} D18F2xE0_STRUCT; + +// **** D18F2xE4 Register Definition **** +// Address +#define D18F2xE4_ADDRESS 0xe4 + +// Type +#define D18F2xE4_TYPE TYPE_D18F2 +// Field Data +#define D18F2xE4_HTCmdHigh_OFFSET 0 +#define D18F2xE4_HTCmdHigh_WIDTH 32 +#define D18F2xE4_HTCmdHigh_MASK 0xffffffff + +/// D18F2xE4 +typedef union { + struct { ///< + UINT32 HTCmdHigh:32; ///< + } Field; ///< + UINT32 Value; ///< +} D18F2xE4_STRUCT; + +// **** D18F2xE8 Register Definition **** +// Address +#define D18F2xE8_ADDRESS 0xe8 + +// Type +#define D18F2xE8_TYPE TYPE_D18F2 +// Field Data +#define D18F2xE8_HTMaskLow_OFFSET 0 +#define D18F2xE8_HTMaskLow_WIDTH 32 +#define D18F2xE8_HTMaskLow_MASK 0xffffffff + +/// D18F2xE8 +typedef union { + struct { ///< + UINT32 HTMaskLow:32; ///< + } Field; ///< + UINT32 Value; ///< +} D18F2xE8_STRUCT; + +// **** D18F2xEC Register Definition **** +// Address +#define D18F2xEC_ADDRESS 0xec + +// Type +#define D18F2xEC_TYPE TYPE_D18F2 +// Field Data +#define D18F2xEC_HTMaskHigh_OFFSET 0 +#define D18F2xEC_HTMaskHigh_WIDTH 32 +#define D18F2xEC_HTMaskHigh_MASK 0xffffffff + +/// D18F2xEC +typedef union { + struct { ///< + UINT32 HTMaskHigh:32; ///< + } Field; ///< + UINT32 Value; ///< +} D18F2xEC_STRUCT; + // **** D18F2xF0 Register Definition **** // Address #define D18F2xF0_ADDRESS 0xf0 @@ -1528,6 +2251,30 @@ typedef union { UINT32 Value; ///< } D18F2xF0_STRUCT; +// **** D18F2x184 Register Definition **** +// Address +#define D18F2x184_ADDRESS 0x184 + +// **** D18F2x18C Register Definition **** +// Address +#define D18F2x18C_ADDRESS 0x18c + +// **** D18F2x190 Register Definition **** +// Address +#define D18F2x190_ADDRESS 0x190 + +// **** D18F2x194 Register Definition **** +// Address +#define D18F2x194_ADDRESS 0x194 + +// **** D18F2x198 Register Definition **** +// Address +#define D18F2x198_ADDRESS 0x198 + +// **** D18F2x1F0 Register Definition **** +// Address +#define D18F2x1F0_ADDRESS 0x1f0 + // **** D18F2xF4 Register Definition **** // Address #define D18F2xF4_ADDRESS 0xf4 @@ -1547,6 +2294,92 @@ typedef union { UINT32 Value; ///< } D18F2xF4_STRUCT; +// **** D18F2x0F4_x40 Register Definition **** +// Address +#define D18F2x0F4_x40_ADDRESS 0x40 + +// Type +#define D18F2x0F4_x40_TYPE TYPE_D18F2x0F4 +// Field Data +#define D18F2x0F4_x40_Trcd_OFFSET 0 +#define D18F2x0F4_x40_Trcd_WIDTH 4 +#define D18F2x0F4_x40_Trcd_MASK 0xf +#define D18F2x0F4_x40_Reserved_7_4_OFFSET 4 +#define D18F2x0F4_x40_Reserved_7_4_WIDTH 4 +#define D18F2x0F4_x40_Reserved_7_4_MASK 0xf0 +#define D18F2x0F4_x40_Trp_OFFSET 8 +#define D18F2x0F4_x40_Trp_WIDTH 4 +#define D18F2x0F4_x40_Trp_MASK 0xf00 +#define D18F2x0F4_x40_Reserved_15_12_OFFSET 12 +#define D18F2x0F4_x40_Reserved_15_12_WIDTH 4 +#define D18F2x0F4_x40_Reserved_15_12_MASK 0xf000 +#define D18F2x0F4_x40_Tras_OFFSET 16 +#define D18F2x0F4_x40_Tras_WIDTH 5 +#define D18F2x0F4_x40_Tras_MASK 0x1f0000 +#define D18F2x0F4_x40_Reserved_23_21_OFFSET 21 +#define D18F2x0F4_x40_Reserved_23_21_WIDTH 3 +#define D18F2x0F4_x40_Reserved_23_21_MASK 0xe00000 +#define D18F2x0F4_x40_Trc_OFFSET 24 +#define D18F2x0F4_x40_Trc_WIDTH 6 +#define D18F2x0F4_x40_Trc_MASK 0x3f000000 +#define D18F2x0F4_x40_Reserved_31_30_OFFSET 30 +#define D18F2x0F4_x40_Reserved_31_30_WIDTH 2 +#define D18F2x0F4_x40_Reserved_31_30_MASK 0xc0000000 + +/// D18F2x0F4_x40 +typedef union { + struct { ///< + UINT32 Trcd:4 ; ///< + UINT32 Reserved_7_4:4 ; ///< + UINT32 Trp:4 ; ///< + UINT32 Reserved_15_12:4 ; ///< + UINT32 Tras:5 ; ///< + UINT32 Reserved_23_21:3 ; ///< + UINT32 Trc:6 ; ///< + UINT32 Reserved_31_30:2 ; ///< + } Field; ///< + UINT32 Value; ///< +} D18F2x0F4_x40_STRUCT; + +// **** D18F2x0F4_x41 Register Definition **** +// Address +#define D18F2x0F4_x41_ADDRESS 0x41 + +// Type +#define D18F2x0F4_x41_TYPE TYPE_D18F2x0F4 +// Field Data +#define D18F2x0F4_x41_Trtp_OFFSET 0 +#define D18F2x0F4_x41_Trtp_WIDTH 3 +#define D18F2x0F4_x41_Trtp_MASK 0x7 +#define D18F2x0F4_x41_Reserved_7_3_OFFSET 3 +#define D18F2x0F4_x41_Reserved_7_3_WIDTH 5 +#define D18F2x0F4_x41_Reserved_7_3_MASK 0xf8 +#define D18F2x0F4_x41_Trrd_OFFSET 8 +#define D18F2x0F4_x41_Trrd_WIDTH 3 +#define D18F2x0F4_x41_Trrd_MASK 0x700 +#define D18F2x0F4_x41_Reserved_15_11_OFFSET 11 +#define D18F2x0F4_x41_Reserved_15_11_WIDTH 5 +#define D18F2x0F4_x41_Reserved_15_11_MASK 0xf800 +#define D18F2x0F4_x41_Twtr_OFFSET 16 +#define D18F2x0F4_x41_Twtr_WIDTH 3 +#define D18F2x0F4_x41_Twtr_MASK 0x70000 +#define D18F2x0F4_x41_Reserved_31_19_OFFSET 19 +#define D18F2x0F4_x41_Reserved_31_19_WIDTH 13 +#define D18F2x0F4_x41_Reserved_31_19_MASK 0xfff80000 + +/// D18F2x0F4_x41 +typedef union { + struct { ///< + UINT32 Trtp:3 ; ///< + UINT32 Reserved_7_3:5 ; ///< + UINT32 Trrd:3 ; ///< + UINT32 Reserved_15_11:5 ; ///< + UINT32 Twtr:3 ; ///< + UINT32 Reserved_31_19:13; ///< + } Field; ///< + UINT32 Value; ///< +} D18F2x0F4_x41_STRUCT; + // **** D18F2x110 Register Definition **** // Address #define D18F2x110_ADDRESS 0x110 @@ -1785,9 +2618,9 @@ typedef union { #define D18F3x7C_Reserved_15_14_OFFSET 14 #define D18F3x7C_Reserved_15_14_WIDTH 2 #define D18F3x7C_Reserved_15_14_MASK 0xc000 -#define D18F3x7C_LoPriNPBC_OFFSET 16 -#define D18F3x7C_LoPriNPBC_WIDTH 6 -#define D18F3x7C_LoPriNPBC_MASK 0x3f0000 +#define D18F3x7C_LoPriNpBC_OFFSET 16 +#define D18F3x7C_LoPriNpBC_WIDTH 6 +#define D18F3x7C_LoPriNpBC_MASK 0x3f0000 #define D18F3x7C_Reserved_23_22_OFFSET 22 #define D18F3x7C_Reserved_23_22_WIDTH 2 #define D18F3x7C_Reserved_23_22_MASK 0xc00000 @@ -1813,6 +2646,57 @@ typedef union { UINT32 Value; ///< } D18F3x7C_STRUCT; +// **** D18F3xD4 Register Definition **** +// Address +#define D18F3xD4_ADDRESS 0xd4 + +// Type +#define D18F3xD4_TYPE TYPE_D18F3 +// Field Data +#define D18F3xD4_MainPllOpFreqId_OFFSET 0 +#define D18F3xD4_MainPllOpFreqId_WIDTH 6 +#define D18F3xD4_MainPllOpFreqId_MASK 0x3f +#define D18F3xD4_MainPllOpFreqIdEn_OFFSET 6 +#define D18F3xD4_MainPllOpFreqIdEn_WIDTH 1 +#define D18F3xD4_MainPllOpFreqIdEn_MASK 0x40 +#define D18F3xD4_Reserved_7_7_OFFSET 7 +#define D18F3xD4_Reserved_7_7_WIDTH 1 +#define D18F3xD4_Reserved_7_7_MASK 0x80 +#define D18F3xD4_ClkRampHystSel_OFFSET 8 +#define D18F3xD4_ClkRampHystSel_WIDTH 4 +#define D18F3xD4_ClkRampHystSel_MASK 0xf00 +#define D18F3xD4_NbOutHyst_OFFSET 12 +#define D18F3xD4_NbOutHyst_WIDTH 4 +#define D18F3xD4_NbOutHyst_MASK 0xf000 +#define D18F3xD4_DisNclkGatingIdle_OFFSET 16 +#define D18F3xD4_DisNclkGatingIdle_WIDTH 1 +#define D18F3xD4_DisNclkGatingIdle_MASK 0x10000 +#define D18F3xD4_ClockGatingEnDram_OFFSET 17 +#define D18F3xD4_ClockGatingEnDram_WIDTH 1 +#define D18F3xD4_ClockGatingEnDram_MASK 0x20000 +#define D18F3xD4_Reserved_18_18_OFFSET 18 +#define D18F3xD4_Reserved_18_18_WIDTH 1 +#define D18F3xD4_Reserved_18_18_MASK 0x40000 +#define D18F3xD4_Reserved_31_19_OFFSET 19 +#define D18F3xD4_Reserved_31_19_WIDTH 13 +#define D18F3xD4_Reserved_31_19_MASK 0xfff80000 + +/// D18F3xD4 +typedef union { + struct { ///< + UINT32 MainPllOpFreqId:6 ; ///< + UINT32 MainPllOpFreqIdEn:1 ; ///< + UINT32 Reserved_7_7:1 ; ///< + UINT32 ClkRampHystSel:4 ; ///< + UINT32 NbOutHyst:4 ; ///< + UINT32 DisNclkGatingIdle:1 ; ///< + UINT32 ClockGatingEnDram:1 ; ///< + UINT32 Reserved_18_18:1 ; ///< + UINT32 Reserved_31_19:13; ///< + } Field; ///< + UINT32 Value; ///< +} D18F3xD4_STRUCT; + // **** D18F3xD8 Register Definition **** // Address #define D18F3xD8_ADDRESS 0xd8 @@ -1996,6 +2880,41 @@ typedef union { UINT32 Value; ///< } D18F4x12C_STRUCT; +// **** D18F4x15C Register Definition **** +// Address +#define D18F4x15C_ADDRESS 0x15c + +// Type +#define D18F4x15C_TYPE TYPE_D18F4 +// Field Data +#define D18F4x15C_BoostSrc_OFFSET 0 +#define D18F4x15C_BoostSrc_WIDTH 2 +#define D18F4x15C_BoostSrc_MASK 0x3 +#define D18F4x15C_NumBoostStates_OFFSET 2 +#define D18F4x15C_NumBoostStates_WIDTH 3 +#define D18F4x15C_NumBoostStates_MASK 0x1c +#define D18F4x15C_Reserved_28_5_OFFSET 5 +#define D18F4x15C_Reserved_28_5_WIDTH 24 +#define D18F4x15C_Reserved_28_5_MASK 0x1fffffe0 +#define D18F4x15C_BoostEnAllCores_OFFSET 29 +#define D18F4x15C_BoostEnAllCores_WIDTH 1 +#define D18F4x15C_BoostEnAllCores_MASK 0x20000000 +#define D18F4x15C_Reserved_31_30_OFFSET 30 +#define D18F4x15C_Reserved_31_30_WIDTH 2 +#define D18F4x15C_Reserved_31_30_MASK 0xc0000000 + +/// D18F4x15C +typedef union { + struct { ///< + UINT32 BoostSrc:2 ; ///< + UINT32 NumBoostStates:3 ; ///< + UINT32 Reserved_28_5:24; ///< + UINT32 BoostEnAllCores:1 ; ///< + UINT32 Reserved_31_30:2 ; ///< + } Field; ///< + UINT32 Value; ///< +} D18F4x15C_STRUCT; + // **** D18F4x164 Register Definition **** // Address #define D18F4x164_ADDRESS 0x164 @@ -3744,6 +4663,88 @@ typedef union { UINT32 Value; ///< } FCRxFE00_7009_STRUCT; +// **** FCRxFE00_7079 Register Definition **** +// Address +#define FCRxFE00_7079_ADDRESS 0xfe007079 + +// Type +#define FCRxFE00_7079_TYPE TYPE_FCR +// Field Data +#define FCRxFE00_7079_Reserved_4_0_OFFSET 0 +#define FCRxFE00_7079_Reserved_4_0_WIDTH 5 +#define FCRxFE00_7079_Reserved_4_0_MASK 0x1f +#define FCRxFE00_7079_CoreDis_OFFSET 5 +#define FCRxFE00_7079_CoreDis_WIDTH 2 +#define FCRxFE00_7079_CoreDis_MASK 0x60 +#define FCRxFE00_7079_Reserved_31_7_OFFSET 7 +#define FCRxFE00_7079_Reserved_31_7_WIDTH 25 +#define FCRxFE00_7079_Reserved_31_7_MASK 0xffffff80 + +/// FCRxFE00_7079 +typedef union { + struct { ///< + UINT32 Reserved_4_0:5 ; ///< + UINT32 CoreDis:2 ; ///< + UINT32 Reserved_31_7:25; ///< + } Field; ///< + UINT32 Value; ///< +} FCRxFE00_7079_STRUCT; + + +// **** FCRxFF30_0AE6 Register Definition **** +// Address +#define FCRxFF30_0AE6_ADDRESS 0xff300ae6 + +// Type +#define FCRxFF30_0AE6_TYPE TYPE_FCR +// Field Data +#define FCRxFF30_0AE6_RengExecuteNonsecureStartPtr_OFFSET 0 +#define FCRxFF30_0AE6_RengExecuteNonsecureStartPtr_WIDTH 10 +#define FCRxFF30_0AE6_RengExecuteNonsecureStartPtr_MASK 0x3ff +#define FCRxFF30_0AE6_Reserved_10_10_OFFSET 10 +#define FCRxFF30_0AE6_Reserved_10_10_WIDTH 1 +#define FCRxFF30_0AE6_Reserved_10_10_MASK 0x400 +#define FCRxFF30_0AE6_RengExecuteOnRegUpdate_OFFSET 11 +#define FCRxFF30_0AE6_RengExecuteOnRegUpdate_WIDTH 1 +#define FCRxFF30_0AE6_RengExecuteOnRegUpdate_MASK 0x800 +#define FCRxFF30_0AE6_Reserved_15_12_OFFSET 12 +#define FCRxFF30_0AE6_Reserved_15_12_WIDTH 4 +#define FCRxFF30_0AE6_Reserved_15_12_MASK 0xf000 +#define FCRxFF30_0AE6_StctrlStutterEn_OFFSET 16 +#define FCRxFF30_0AE6_StctrlStutterEn_WIDTH 1 +#define FCRxFF30_0AE6_StctrlStutterEn_MASK 0x10000 +#define FCRxFF30_0AE6_Reserved_23_17_OFFSET 17 +#define FCRxFF30_0AE6_Reserved_23_17_WIDTH 7 +#define FCRxFF30_0AE6_Reserved_23_17_MASK 0xfe0000 +#define FCRxFF30_0AE6_StctrlIgnoreProtectionFault_OFFSET 24 +#define FCRxFF30_0AE6_StctrlIgnoreProtectionFault_WIDTH 1 +#define FCRxFF30_0AE6_StctrlIgnoreProtectionFault_MASK 0x1000000 +#define FCRxFF30_0AE6_Reserved_26_25_OFFSET 25 +#define FCRxFF30_0AE6_Reserved_26_25_WIDTH 2 +#define FCRxFF30_0AE6_Reserved_26_25_MASK 0x6000000 +#define FCRxFF30_0AE6_CriticalRegsLock_OFFSET 27 +#define FCRxFF30_0AE6_CriticalRegsLock_WIDTH 1 +#define FCRxFF30_0AE6_CriticalRegsLock_MASK 0x8000000 +#define FCRxFF30_0AE6_Reserved_31_28_OFFSET 28 +#define FCRxFF30_0AE6_Reserved_31_28_WIDTH 4 +#define FCRxFF30_0AE6_Reserved_31_28_MASK 0xf0000000 + +/// FCRxFF30_0AE6 +typedef union { + struct { ///< + UINT32 RengExecuteNonsecureStartPtr:10; ///< + UINT32 Reserved_10_10:1 ; ///< + UINT32 RengExecuteOnRegUpdate:1 ; ///< + UINT32 Reserved_15_12:4 ; ///< + UINT32 StctrlStutterEn:1 ; ///< + UINT32 Reserved_23_17:7 ; ///< + UINT32 StctrlIgnoreProtectionFault:1 ; ///< + UINT32 Reserved_26_25:2 ; ///< + UINT32 CriticalRegsLock:1 ; ///< + UINT32 Reserved_31_28:4 ; ///< + } Field; ///< + UINT32 Value; ///< +} FCRxFF30_0AE6_STRUCT; // **** D0F0x64_x00 Register Definition **** // Address @@ -3927,6 +4928,85 @@ typedef union { UINT32 Value; ///< } D0F0x64_x1A_STRUCT; +// **** D0F0x64_x1C Register Definition **** +// Address +#define D0F0x64_x1C_ADDRESS 0x1c + +// Type +#define D0F0x64_x1C_TYPE TYPE_D0F0x64 +// Field Data +#define D0F0x64_x1C_WriteDis_OFFSET 0 +#define D0F0x64_x1C_WriteDis_WIDTH 1 +#define D0F0x64_x1C_WriteDis_MASK 0x1 +#define D0F0x64_x1C_F0NonlegacyDeviceTypeEn_OFFSET 1 +#define D0F0x64_x1C_F0NonlegacyDeviceTypeEn_WIDTH 1 +#define D0F0x64_x1C_F0NonlegacyDeviceTypeEn_MASK 0x2 +#define D0F0x64_x1C_F064BarEn_OFFSET 2 +#define D0F0x64_x1C_F064BarEn_WIDTH 1 +#define D0F0x64_x1C_F064BarEn_MASK 0x4 +#define D0F0x64_x1C_MemApSize_OFFSET 3 +#define D0F0x64_x1C_MemApSize_WIDTH 3 +#define D0F0x64_x1C_MemApSize_MASK 0x38 +#define D0F0x64_x1C_RegApSize_OFFSET 6 +#define D0F0x64_x1C_RegApSize_WIDTH 1 +#define D0F0x64_x1C_RegApSize_MASK 0x40 +#define D0F0x64_x1C_Reserved_7_7_OFFSET 7 +#define D0F0x64_x1C_Reserved_7_7_WIDTH 1 +#define D0F0x64_x1C_Reserved_7_7_MASK 0x80 +#define D0F0x64_x1C_AudioEn_OFFSET 8 +#define D0F0x64_x1C_AudioEn_WIDTH 1 +#define D0F0x64_x1C_AudioEn_MASK 0x100 +#define D0F0x64_x1C_MsiDis_OFFSET 9 +#define D0F0x64_x1C_MsiDis_WIDTH 1 +#define D0F0x64_x1C_MsiDis_MASK 0x200 +#define D0F0x64_x1C_AudioNonlegacyDeviceTypeEn_OFFSET 10 +#define D0F0x64_x1C_AudioNonlegacyDeviceTypeEn_WIDTH 1 +#define D0F0x64_x1C_AudioNonlegacyDeviceTypeEn_MASK 0x400 +#define D0F0x64_x1C_Audio64BarEn_OFFSET 11 +#define D0F0x64_x1C_Audio64BarEn_WIDTH 1 +#define D0F0x64_x1C_Audio64BarEn_MASK 0x800 +#define D0F0x64_x1C_Reserved_15_12_OFFSET 12 +#define D0F0x64_x1C_Reserved_15_12_WIDTH 4 +#define D0F0x64_x1C_Reserved_15_12_MASK 0xf000 +#define D0F0x64_x1C_IoBarDis_OFFSET 16 +#define D0F0x64_x1C_IoBarDis_WIDTH 1 +#define D0F0x64_x1C_IoBarDis_MASK 0x10000 +#define D0F0x64_x1C_F0En_OFFSET 17 +#define D0F0x64_x1C_F0En_WIDTH 1 +#define D0F0x64_x1C_F0En_MASK 0x20000 +#define D0F0x64_x1C_Reserved_22_18_OFFSET 18 +#define D0F0x64_x1C_Reserved_22_18_WIDTH 5 +#define D0F0x64_x1C_Reserved_22_18_MASK 0x7c0000 +#define D0F0x64_x1C_RcieEn_OFFSET 23 +#define D0F0x64_x1C_RcieEn_WIDTH 1 +#define D0F0x64_x1C_RcieEn_MASK 0x800000 +#define D0F0x64_x1C_Reserved_31_24_OFFSET 24 +#define D0F0x64_x1C_Reserved_31_24_WIDTH 8 +#define D0F0x64_x1C_Reserved_31_24_MASK 0xff000000 + +/// D0F0x64_x1C +typedef union { + struct { ///< + UINT32 WriteDis:1 ; ///< + UINT32 F0NonlegacyDeviceTypeEn:1 ; ///< + UINT32 F064BarEn:1 ; ///< + UINT32 MemApSize:3 ; ///< + UINT32 RegApSize:1 ; ///< + UINT32 Reserved_7_7:1 ; ///< + UINT32 AudioEn:1 ; ///< + UINT32 MsiDis:1 ; ///< + UINT32 AudioNonlegacyDeviceTypeEn:1 ; ///< + UINT32 Audio64BarEn:1 ; ///< + UINT32 Reserved_15_12:4 ; ///< + UINT32 IoBarDis:1 ; ///< + UINT32 F0En:1 ; ///< + UINT32 Reserved_22_18:5 ; ///< + UINT32 RcieEn:1 ; ///< + UINT32 Reserved_31_24:8 ; ///< + } Field; ///< + UINT32 Value; ///< +} D0F0x64_x1C_STRUCT; + // **** D0F0x64_x1D Register Definition **** // Address #define D0F0x64_x1D_ADDRESS 0x1d @@ -3989,6 +5069,148 @@ typedef union { UINT32 Value; ///< } D0F0x64_x20_STRUCT; +// **** D0F0x64_x22 Register Definition **** +// Address +#define D0F0x64_x22_ADDRESS 0x22 + +// Type +#define D0F0x64_x22_TYPE TYPE_D0F0x64 +// Field Data +#define D0F0x64_x22_Reserved_3_0_OFFSET 0 +#define D0F0x64_x22_Reserved_3_0_WIDTH 4 +#define D0F0x64_x22_Reserved_3_0_MASK 0xf +#define D0F0x64_x22_OffHysteresis_OFFSET 4 +#define D0F0x64_x22_OffHysteresis_WIDTH 8 +#define D0F0x64_x22_OffHysteresis_MASK 0xff0 +#define D0F0x64_x22_Reserved_25_12_OFFSET 12 +#define D0F0x64_x22_Reserved_25_12_WIDTH 14 +#define D0F0x64_x22_Reserved_25_12_MASK 0x3fff000 +#define D0F0x64_x22_SoftOverrideClk4_OFFSET 26 +#define D0F0x64_x22_SoftOverrideClk4_WIDTH 1 +#define D0F0x64_x22_SoftOverrideClk4_MASK 0x4000000 +#define D0F0x64_x22_SoftOverrideClk3_OFFSET 27 +#define D0F0x64_x22_SoftOverrideClk3_WIDTH 1 +#define D0F0x64_x22_SoftOverrideClk3_MASK 0x8000000 +#define D0F0x64_x22_SoftOverrideClk2_OFFSET 28 +#define D0F0x64_x22_SoftOverrideClk2_WIDTH 1 +#define D0F0x64_x22_SoftOverrideClk2_MASK 0x10000000 +#define D0F0x64_x22_SoftOverrideClk1_OFFSET 29 +#define D0F0x64_x22_SoftOverrideClk1_WIDTH 1 +#define D0F0x64_x22_SoftOverrideClk1_MASK 0x20000000 +#define D0F0x64_x22_SoftOverrideClk0_OFFSET 30 +#define D0F0x64_x22_SoftOverrideClk0_WIDTH 1 +#define D0F0x64_x22_SoftOverrideClk0_MASK 0x40000000 +#define D0F0x64_x22_Reserved_31_31_OFFSET 31 +#define D0F0x64_x22_Reserved_31_31_WIDTH 1 +#define D0F0x64_x22_Reserved_31_31_MASK 0x80000000 + +/// D0F0x64_x22 +typedef union { + struct { ///< + UINT32 Reserved_3_0:4 ; ///< + UINT32 OffHysteresis:8 ; ///< + UINT32 Reserved_25_12:14; ///< + UINT32 SoftOverrideClk4:1 ; ///< + UINT32 SoftOverrideClk3:1 ; ///< + UINT32 SoftOverrideClk2:1 ; ///< + UINT32 SoftOverrideClk1:1 ; ///< + UINT32 SoftOverrideClk0:1 ; ///< + UINT32 Reserved_31_31:1 ; ///< + } Field; ///< + UINT32 Value; ///< +} D0F0x64_x22_STRUCT; + +// **** D0F0x64_x23 Register Definition **** +// Address +#define D0F0x64_x23_ADDRESS 0x23 + +// Type +#define D0F0x64_x23_TYPE TYPE_D0F0x64 +// Field Data +#define D0F0x64_x23_Reserved_3_0_OFFSET 0 +#define D0F0x64_x23_Reserved_3_0_WIDTH 4 +#define D0F0x64_x23_Reserved_3_0_MASK 0xf +#define D0F0x64_x23_OffHysteresis_OFFSET 4 +#define D0F0x64_x23_OffHysteresis_WIDTH 8 +#define D0F0x64_x23_OffHysteresis_MASK 0xff0 +#define D0F0x64_x23_Reserved_25_12_OFFSET 12 +#define D0F0x64_x23_Reserved_25_12_WIDTH 14 +#define D0F0x64_x23_Reserved_25_12_MASK 0x3fff000 +#define D0F0x64_x23_SoftOverrideClk4_OFFSET 26 +#define D0F0x64_x23_SoftOverrideClk4_WIDTH 1 +#define D0F0x64_x23_SoftOverrideClk4_MASK 0x4000000 +#define D0F0x64_x23_SoftOverrideClk3_OFFSET 27 +#define D0F0x64_x23_SoftOverrideClk3_WIDTH 1 +#define D0F0x64_x23_SoftOverrideClk3_MASK 0x8000000 +#define D0F0x64_x23_SoftOverrideClk2_OFFSET 28 +#define D0F0x64_x23_SoftOverrideClk2_WIDTH 1 +#define D0F0x64_x23_SoftOverrideClk2_MASK 0x10000000 +#define D0F0x64_x23_SoftOverrideClk1_OFFSET 29 +#define D0F0x64_x23_SoftOverrideClk1_WIDTH 1 +#define D0F0x64_x23_SoftOverrideClk1_MASK 0x20000000 +#define D0F0x64_x23_SoftOverrideClk0_OFFSET 30 +#define D0F0x64_x23_SoftOverrideClk0_WIDTH 1 +#define D0F0x64_x23_SoftOverrideClk0_MASK 0x40000000 +#define D0F0x64_x23_Reserved_31_31_OFFSET 31 +#define D0F0x64_x23_Reserved_31_31_WIDTH 1 +#define D0F0x64_x23_Reserved_31_31_MASK 0x80000000 + +/// D0F0x64_x23 +typedef union { + struct { ///< + UINT32 Reserved_3_0:4 ; ///< + UINT32 OffHysteresis:8 ; ///< + UINT32 Reserved_25_12:14; ///< + UINT32 SoftOverrideClk4:1 ; ///< + UINT32 SoftOverrideClk3:1 ; ///< + UINT32 SoftOverrideClk2:1 ; ///< + UINT32 SoftOverrideClk1:1 ; ///< + UINT32 SoftOverrideClk0:1 ; ///< + UINT32 Reserved_31_31:1 ; ///< + } Field; ///< + UINT32 Value; ///< +} D0F0x64_x23_STRUCT; + +// **** D0F0x64_x24 Register Definition **** +// Address +#define D0F0x64_x24_ADDRESS 0x24 + +// Type +#define D0F0x64_x24_TYPE TYPE_D0F0x64 +// Field Data +#define D0F0x64_x24_Reserved_3_0_OFFSET 0 +#define D0F0x64_x24_Reserved_3_0_WIDTH 4 +#define D0F0x64_x24_Reserved_3_0_MASK 0xf +#define D0F0x64_x24_OffHysteresis_OFFSET 4 +#define D0F0x64_x24_OffHysteresis_WIDTH 8 +#define D0F0x64_x24_OffHysteresis_MASK 0xff0 +#define D0F0x64_x24_Reserved_28_12_OFFSET 12 +#define D0F0x64_x24_Reserved_28_12_WIDTH 17 +#define D0F0x64_x24_Reserved_28_12_MASK 0x1ffff000 +#define D0F0x64_x24_SoftOverrideClk1_OFFSET 29 +#define D0F0x64_x24_SoftOverrideClk1_WIDTH 1 +#define D0F0x64_x24_SoftOverrideClk1_MASK 0x20000000 +#define D0F0x64_x24_SoftOverrideClk0_OFFSET 30 +#define D0F0x64_x24_SoftOverrideClk0_WIDTH 1 +#define D0F0x64_x24_SoftOverrideClk0_MASK 0x40000000 +#define D0F0x64_x24_Reserved_31_31_OFFSET 31 +#define D0F0x64_x24_Reserved_31_31_WIDTH 1 +#define D0F0x64_x24_Reserved_31_31_MASK 0x80000000 + +/// D0F0x64_x24 +typedef union { + struct { ///< + UINT32 Reserved_3_0:4 ; ///< + UINT32 OffHysteresis:8 ; ///< + UINT32 Reserved_28_12:17; ///< + UINT32 SoftOverrideClk1:1 ; ///< + UINT32 SoftOverrideClk0:1 ; ///< + UINT32 Reserved_31_31:1 ; ///< + } Field; ///< + UINT32 Value; ///< +} D0F0x64_x24_STRUCT; + + // **** D0F0x64_x46 Register Definition **** // Address #define D0F0x64_x46_ADDRESS 0x46 @@ -4539,6 +5761,159 @@ typedef union { UINT32 Value; ///< } D0F0x98_x2C_STRUCT; +// **** D0F0x98_x49 Register Definition **** +// Address +#define D0F0x98_x49_ADDRESS 0x49 + +// Type +#define D0F0x98_x49_TYPE TYPE_D0F0x98 +// Field Data +#define D0F0x98_x49_Reserved_3_0_OFFSET 0 +#define D0F0x98_x49_Reserved_3_0_WIDTH 4 +#define D0F0x98_x49_Reserved_3_0_MASK 0xf +#define D0F0x98_x49_OffHysteresis_OFFSET 4 +#define D0F0x98_x49_OffHysteresis_WIDTH 8 +#define D0F0x98_x49_OffHysteresis_MASK 0xff0 +#define D0F0x98_x49_Reserved_23_12_OFFSET 12 +#define D0F0x98_x49_Reserved_23_12_WIDTH 12 +#define D0F0x98_x49_Reserved_23_12_MASK 0xfff000 +#define D0F0x98_x49_SoftOverrideClk6_OFFSET 24 +#define D0F0x98_x49_SoftOverrideClk6_WIDTH 1 +#define D0F0x98_x49_SoftOverrideClk6_MASK 0x1000000 +#define D0F0x98_x49_SoftOverrideClk5_OFFSET 25 +#define D0F0x98_x49_SoftOverrideClk5_WIDTH 1 +#define D0F0x98_x49_SoftOverrideClk5_MASK 0x2000000 +#define D0F0x98_x49_SoftOverrideClk4_OFFSET 26 +#define D0F0x98_x49_SoftOverrideClk4_WIDTH 1 +#define D0F0x98_x49_SoftOverrideClk4_MASK 0x4000000 +#define D0F0x98_x49_SoftOverrideClk3_OFFSET 27 +#define D0F0x98_x49_SoftOverrideClk3_WIDTH 1 +#define D0F0x98_x49_SoftOverrideClk3_MASK 0x8000000 +#define D0F0x98_x49_SoftOverrideClk2_OFFSET 28 +#define D0F0x98_x49_SoftOverrideClk2_WIDTH 1 +#define D0F0x98_x49_SoftOverrideClk2_MASK 0x10000000 +#define D0F0x98_x49_SoftOverrideClk1_OFFSET 29 +#define D0F0x98_x49_SoftOverrideClk1_WIDTH 1 +#define D0F0x98_x49_SoftOverrideClk1_MASK 0x20000000 +#define D0F0x98_x49_SoftOverrideClk0_OFFSET 30 +#define D0F0x98_x49_SoftOverrideClk0_WIDTH 1 +#define D0F0x98_x49_SoftOverrideClk0_MASK 0x40000000 +#define D0F0x98_x49_Reserved_31_31_OFFSET 31 +#define D0F0x98_x49_Reserved_31_31_WIDTH 1 +#define D0F0x98_x49_Reserved_31_31_MASK 0x80000000 + +/// D0F0x98_x49 +typedef union { + struct { ///< + UINT32 Reserved_3_0:4 ; ///< + UINT32 OffHysteresis:8 ; ///< + UINT32 Reserved_23_12:12; ///< + UINT32 SoftOverrideClk6:1 ; ///< + UINT32 SoftOverrideClk5:1 ; ///< + UINT32 SoftOverrideClk4:1 ; ///< + UINT32 SoftOverrideClk3:1 ; ///< + UINT32 SoftOverrideClk2:1 ; ///< + UINT32 SoftOverrideClk1:1 ; ///< + UINT32 SoftOverrideClk0:1 ; ///< + UINT32 Reserved_31_31:1 ; ///< + } Field; ///< + UINT32 Value; ///< +} D0F0x98_x49_STRUCT; + +// **** D0F0x98_x4A Register Definition **** +// Address +#define D0F0x98_x4A_ADDRESS 0x4a + +// Type +#define D0F0x98_x4A_TYPE TYPE_D0F0x98 +// Field Data +#define D0F0x98_x4A_Reserved_3_0_OFFSET 0 +#define D0F0x98_x4A_Reserved_3_0_WIDTH 4 +#define D0F0x98_x4A_Reserved_3_0_MASK 0xf +#define D0F0x98_x4A_OffHysteresis_OFFSET 4 +#define D0F0x98_x4A_OffHysteresis_WIDTH 8 +#define D0F0x98_x4A_OffHysteresis_MASK 0xff0 +#define D0F0x98_x4A_Reserved_23_12_OFFSET 12 +#define D0F0x98_x4A_Reserved_23_12_WIDTH 12 +#define D0F0x98_x4A_Reserved_23_12_MASK 0xfff000 +#define D0F0x98_x4A_SoftOverrideClk6_OFFSET 24 +#define D0F0x98_x4A_SoftOverrideClk6_WIDTH 1 +#define D0F0x98_x4A_SoftOverrideClk6_MASK 0x1000000 +#define D0F0x98_x4A_SoftOverrideClk5_OFFSET 25 +#define D0F0x98_x4A_SoftOverrideClk5_WIDTH 1 +#define D0F0x98_x4A_SoftOverrideClk5_MASK 0x2000000 +#define D0F0x98_x4A_SoftOverrideClk4_OFFSET 26 +#define D0F0x98_x4A_SoftOverrideClk4_WIDTH 1 +#define D0F0x98_x4A_SoftOverrideClk4_MASK 0x4000000 +#define D0F0x98_x4A_SoftOverrideClk3_OFFSET 27 +#define D0F0x98_x4A_SoftOverrideClk3_WIDTH 1 +#define D0F0x98_x4A_SoftOverrideClk3_MASK 0x8000000 +#define D0F0x98_x4A_SoftOverrideClk2_OFFSET 28 +#define D0F0x98_x4A_SoftOverrideClk2_WIDTH 1 +#define D0F0x98_x4A_SoftOverrideClk2_MASK 0x10000000 +#define D0F0x98_x4A_SoftOverrideClk1_OFFSET 29 +#define D0F0x98_x4A_SoftOverrideClk1_WIDTH 1 +#define D0F0x98_x4A_SoftOverrideClk1_MASK 0x20000000 +#define D0F0x98_x4A_SoftOverrideClk0_OFFSET 30 +#define D0F0x98_x4A_SoftOverrideClk0_WIDTH 1 +#define D0F0x98_x4A_SoftOverrideClk0_MASK 0x40000000 +#define D0F0x98_x4A_Reserved_31_31_OFFSET 31 +#define D0F0x98_x4A_Reserved_31_31_WIDTH 1 +#define D0F0x98_x4A_Reserved_31_31_MASK 0x80000000 + +/// D0F0x98_x4A +typedef union { + struct { ///< + UINT32 Reserved_3_0:4 ; ///< + UINT32 OffHysteresis:8 ; ///< + UINT32 Reserved_23_12:12; ///< + UINT32 SoftOverrideClk6:1 ; ///< + UINT32 SoftOverrideClk5:1 ; ///< + UINT32 SoftOverrideClk4:1 ; ///< + UINT32 SoftOverrideClk3:1 ; ///< + UINT32 SoftOverrideClk2:1 ; ///< + UINT32 SoftOverrideClk1:1 ; ///< + UINT32 SoftOverrideClk0:1 ; ///< + UINT32 Reserved_31_31:1 ; ///< + } Field; ///< + UINT32 Value; ///< +} D0F0x98_x4A_STRUCT; + +// **** D0F0x98_x4B Register Definition **** +// Address +#define D0F0x98_x4B_ADDRESS 0x4b + +// Type +#define D0F0x98_x4B_TYPE TYPE_D0F0x98 +// Field Data +#define D0F0x98_x4B_Reserved_3_0_OFFSET 0 +#define D0F0x98_x4B_Reserved_3_0_WIDTH 4 +#define D0F0x98_x4B_Reserved_3_0_MASK 0xf +#define D0F0x98_x4B_OffHysteresis_OFFSET 4 +#define D0F0x98_x4B_OffHysteresis_WIDTH 8 +#define D0F0x98_x4B_OffHysteresis_MASK 0xff0 +#define D0F0x98_x4B_Reserved_29_12_OFFSET 12 +#define D0F0x98_x4B_Reserved_29_12_WIDTH 18 +#define D0F0x98_x4B_Reserved_29_12_MASK 0x3ffff000 +#define D0F0x98_x4B_SoftOverrideClk_OFFSET 30 +#define D0F0x98_x4B_SoftOverrideClk_WIDTH 1 +#define D0F0x98_x4B_SoftOverrideClk_MASK 0x40000000 +#define D0F0x98_x4B_Reserved_31_31_OFFSET 31 +#define D0F0x98_x4B_Reserved_31_31_WIDTH 1 +#define D0F0x98_x4B_Reserved_31_31_MASK 0x80000000 + +/// D0F0x98_x4B +typedef union { + struct { ///< + UINT32 Reserved_3_0:4 ; ///< + UINT32 OffHysteresis:8 ; ///< + UINT32 Reserved_29_12:18; ///< + UINT32 SoftOverrideClk:1 ; ///< + UINT32 Reserved_31_31:1 ; ///< + } Field; ///< + UINT32 Value; ///< +} D0F0x98_x4B_STRUCT; + // **** D0F0xE4_WRAP_0080 Register Definition **** // Address #define D0F0xE4_WRAP_0080_ADDRESS 0x80 @@ -4662,6 +6037,346 @@ typedef union { UINT32 Value; ///< } D0F0xE4_WRAP_8002_STRUCT; +// **** D0F0xE4_WRAP_8011 Register Definition **** +// Address +#define D0F0xE4_WRAP_8011_ADDRESS 0x8011 + +// Type +#define D0F0xE4_WRAP_8011_TYPE TYPE_D0F0xE4 +// Field Data +#define D0F0xE4_WRAP_8011_TxclkDynGateLatency_OFFSET 0 +#define D0F0xE4_WRAP_8011_TxclkDynGateLatency_WIDTH 6 +#define D0F0xE4_WRAP_8011_TxclkDynGateLatency_MASK 0x3f +#define D0F0xE4_WRAP_8011_TxclkPermGateEven_OFFSET 6 +#define D0F0xE4_WRAP_8011_TxclkPermGateEven_WIDTH 1 +#define D0F0xE4_WRAP_8011_TxclkPermGateEven_MASK 0x40 +#define D0F0xE4_WRAP_8011_TxclkDynGateEnable_OFFSET 7 +#define D0F0xE4_WRAP_8011_TxclkDynGateEnable_WIDTH 1 +#define D0F0xE4_WRAP_8011_TxclkDynGateEnable_MASK 0x80 +#define D0F0xE4_WRAP_8011_TxclkPermStop_OFFSET 8 +#define D0F0xE4_WRAP_8011_TxclkPermStop_WIDTH 1 +#define D0F0xE4_WRAP_8011_TxclkPermStop_MASK 0x100 +#define D0F0xE4_WRAP_8011_TxclkRegsGateEnable_OFFSET 9 +#define D0F0xE4_WRAP_8011_TxclkRegsGateEnable_WIDTH 1 +#define D0F0xE4_WRAP_8011_TxclkRegsGateEnable_MASK 0x200 +#define D0F0xE4_WRAP_8011_TxclkRegsGateLatency_OFFSET 10 +#define D0F0xE4_WRAP_8011_TxclkRegsGateLatency_WIDTH 6 +#define D0F0xE4_WRAP_8011_TxclkRegsGateLatency_MASK 0xfc00 +#define D0F0xE4_WRAP_8011_RcvrDetClkEnable_OFFSET 16 +#define D0F0xE4_WRAP_8011_RcvrDetClkEnable_WIDTH 1 +#define D0F0xE4_WRAP_8011_RcvrDetClkEnable_MASK 0x10000 +#define D0F0xE4_WRAP_8011_TxclkPermGateLatency_OFFSET 17 +#define D0F0xE4_WRAP_8011_TxclkPermGateLatency_WIDTH 6 +#define D0F0xE4_WRAP_8011_TxclkPermGateLatency_MASK 0x7e0000 +#define D0F0xE4_WRAP_8011_Reserved_23_23_OFFSET 23 +#define D0F0xE4_WRAP_8011_Reserved_23_23_WIDTH 1 +#define D0F0xE4_WRAP_8011_Reserved_23_23_MASK 0x800000 +#define D0F0xE4_WRAP_8011_TxclkLcntGateEnable_OFFSET 24 +#define D0F0xE4_WRAP_8011_TxclkLcntGateEnable_WIDTH 1 +#define D0F0xE4_WRAP_8011_TxclkLcntGateEnable_MASK 0x1000000 +#define D0F0xE4_WRAP_8011_Reserved_30_25_OFFSET 25 +#define D0F0xE4_WRAP_8011_Reserved_30_25_WIDTH 6 +#define D0F0xE4_WRAP_8011_Reserved_30_25_MASK 0x7e000000 +#define D0F0xE4_WRAP_8011_StrapBifValid_OFFSET 31 +#define D0F0xE4_WRAP_8011_StrapBifValid_WIDTH 1 +#define D0F0xE4_WRAP_8011_StrapBifValid_MASK 0x80000000 + +/// D0F0xE4_WRAP_8011 +typedef union { + struct { ///< + UINT32 TxclkDynGateLatency:6 ; ///< + UINT32 TxclkPermGateEven:1 ; ///< + UINT32 TxclkDynGateEnable:1 ; ///< + UINT32 TxclkPermStop:1 ; ///< + UINT32 TxclkRegsGateEnable:1 ; ///< + UINT32 TxclkRegsGateLatency:6 ; ///< + UINT32 RcvrDetClkEnable:1 ; ///< + UINT32 TxclkPermGateLatency:6 ; ///< + UINT32 Reserved_23_23:1 ; ///< + UINT32 TxclkLcntGateEnable:1 ; ///< + UINT32 Reserved_30_25:6 ; ///< + UINT32 StrapBifValid:1 ; ///< + } Field; ///< + UINT32 Value; ///< +} D0F0xE4_WRAP_8011_STRUCT; + +// **** D0F0xE4_WRAP_8012 Register Definition **** +// Address +#define D0F0xE4_WRAP_8012_ADDRESS 0x8012 + +// Type +#define D0F0xE4_WRAP_8012_TYPE TYPE_D0F0xE4 +// Field Data +#define D0F0xE4_WRAP_8012_Pif1xIdleGateLatency_OFFSET 0 +#define D0F0xE4_WRAP_8012_Pif1xIdleGateLatency_WIDTH 6 +#define D0F0xE4_WRAP_8012_Pif1xIdleGateLatency_MASK 0x3f +#define D0F0xE4_WRAP_8012_Reserved_6_6_OFFSET 6 +#define D0F0xE4_WRAP_8012_Reserved_6_6_WIDTH 1 +#define D0F0xE4_WRAP_8012_Reserved_6_6_MASK 0x40 +#define D0F0xE4_WRAP_8012_Pif1xIdleGateEnable_OFFSET 7 +#define D0F0xE4_WRAP_8012_Pif1xIdleGateEnable_WIDTH 1 +#define D0F0xE4_WRAP_8012_Pif1xIdleGateEnable_MASK 0x80 +#define D0F0xE4_WRAP_8012_Pif1xIdleResumeLatency_OFFSET 8 +#define D0F0xE4_WRAP_8012_Pif1xIdleResumeLatency_WIDTH 6 +#define D0F0xE4_WRAP_8012_Pif1xIdleResumeLatency_MASK 0x3f00 +#define D0F0xE4_WRAP_8012_Reserved_15_14_OFFSET 14 +#define D0F0xE4_WRAP_8012_Reserved_15_14_WIDTH 2 +#define D0F0xE4_WRAP_8012_Reserved_15_14_MASK 0xc000 +#define D0F0xE4_WRAP_8012_Pif2p5xIdleGateLatency_OFFSET 16 +#define D0F0xE4_WRAP_8012_Pif2p5xIdleGateLatency_WIDTH 6 +#define D0F0xE4_WRAP_8012_Pif2p5xIdleGateLatency_MASK 0x3f0000 +#define D0F0xE4_WRAP_8012_Reserved_22_22_OFFSET 22 +#define D0F0xE4_WRAP_8012_Reserved_22_22_WIDTH 1 +#define D0F0xE4_WRAP_8012_Reserved_22_22_MASK 0x400000 +#define D0F0xE4_WRAP_8012_Pif2p5xIdleGateEnable_OFFSET 23 +#define D0F0xE4_WRAP_8012_Pif2p5xIdleGateEnable_WIDTH 1 +#define D0F0xE4_WRAP_8012_Pif2p5xIdleGateEnable_MASK 0x800000 +#define D0F0xE4_WRAP_8012_Pif2p5xIdleResumeLatency_OFFSET 24 +#define D0F0xE4_WRAP_8012_Pif2p5xIdleResumeLatency_WIDTH 6 +#define D0F0xE4_WRAP_8012_Pif2p5xIdleResumeLatency_MASK 0x3f000000 +#define D0F0xE4_WRAP_8012_Reserved_31_30_OFFSET 30 +#define D0F0xE4_WRAP_8012_Reserved_31_30_WIDTH 2 +#define D0F0xE4_WRAP_8012_Reserved_31_30_MASK 0xc0000000 + +/// D0F0xE4_WRAP_8012 +typedef union { + struct { ///< + UINT32 Pif1xIdleGateLatency:6 ; ///< + UINT32 Reserved_6_6:1 ; ///< + UINT32 Pif1xIdleGateEnable:1 ; ///< + UINT32 Pif1xIdleResumeLatency:6 ; ///< + UINT32 Reserved_15_14:2 ; ///< + UINT32 Pif2p5xIdleGateLatency:6 ; ///< + UINT32 Reserved_22_22:1 ; ///< + UINT32 Pif2p5xIdleGateEnable:1 ; ///< + UINT32 Pif2p5xIdleResumeLatency:6 ; ///< + UINT32 Reserved_31_30:2 ; ///< + } Field; ///< + UINT32 Value; ///< +} D0F0xE4_WRAP_8012_STRUCT; + + +// **** D0F0xE4_WRAP_8013 Register Definition **** +// Address +#define D0F0xE4_WRAP_8013_ADDRESS 0x8013 + +// Field Data +#define D0F0xE4_WRAP_8013_MasterPciePllA_OFFSET 0 +#define D0F0xE4_WRAP_8013_MasterPciePllA_WIDTH 1 +#define D0F0xE4_WRAP_8013_MasterPciePllA_MASK 0x1 +#define D0F0xE4_WRAP_8013_Reserved_1_1_OFFSET 1 +#define D0F0xE4_WRAP_8013_Reserved_1_1_WIDTH 1 +#define D0F0xE4_WRAP_8013_Reserved_1_1_MASK 0x2 +#define D0F0xE4_WRAP_8013_Reserved_2_2_OFFSET 2 +#define D0F0xE4_WRAP_8013_Reserved_2_2_WIDTH 1 +#define D0F0xE4_WRAP_8013_Reserved_2_2_MASK 0x4 +#define D0F0xE4_WRAP_8013_Reserved_3_3_OFFSET 3 +#define D0F0xE4_WRAP_8013_Reserved_3_3_WIDTH 1 +#define D0F0xE4_WRAP_8013_Reserved_3_3_MASK 0x8 +#define D0F0xE4_WRAP_8013_ClkDividerResetOverrideA_OFFSET 4 +#define D0F0xE4_WRAP_8013_ClkDividerResetOverrideA_WIDTH 1 +#define D0F0xE4_WRAP_8013_ClkDividerResetOverrideA_MASK 0x10 +#define D0F0xE4_WRAP_8013_Reserved_5_5_OFFSET 5 +#define D0F0xE4_WRAP_8013_Reserved_5_5_WIDTH 1 +#define D0F0xE4_WRAP_8013_Reserved_5_5_MASK 0x20 +#define D0F0xE4_WRAP_8013_Reserved_6_6_OFFSET 6 +#define D0F0xE4_WRAP_8013_Reserved_6_6_WIDTH 1 +#define D0F0xE4_WRAP_8013_Reserved_6_6_MASK 0x40 +#define D0F0xE4_WRAP_8013_Reserved_7_7_OFFSET 7 +#define D0F0xE4_WRAP_8013_Reserved_7_7_WIDTH 1 +#define D0F0xE4_WRAP_8013_Reserved_7_7_MASK 0x80 +#define D0F0xE4_WRAP_8013_TxclkSelCoreOverride_OFFSET 8 +#define D0F0xE4_WRAP_8013_TxclkSelCoreOverride_WIDTH 1 +#define D0F0xE4_WRAP_8013_TxclkSelCoreOverride_MASK 0x100 +#define D0F0xE4_WRAP_8013_TxclkSelPifAOverride_OFFSET 9 +#define D0F0xE4_WRAP_8013_TxclkSelPifAOverride_WIDTH 1 +#define D0F0xE4_WRAP_8013_TxclkSelPifAOverride_MASK 0x200 +#define D0F0xE4_WRAP_8013_Reserved_10_10_OFFSET 10 +#define D0F0xE4_WRAP_8013_Reserved_10_10_WIDTH 1 +#define D0F0xE4_WRAP_8013_Reserved_10_10_MASK 0x400 +#define D0F0xE4_WRAP_8013_Reserved_11_11_OFFSET 11 +#define D0F0xE4_WRAP_8013_Reserved_11_11_WIDTH 1 +#define D0F0xE4_WRAP_8013_Reserved_11_11_MASK 0x800 +#define D0F0xE4_WRAP_8013_Reserved_12_12_OFFSET 12 +#define D0F0xE4_WRAP_8013_Reserved_12_12_WIDTH 1 +#define D0F0xE4_WRAP_8013_Reserved_12_12_MASK 0x1000 +#define D0F0xE4_WRAP_8013_Reserved_15_13_OFFSET 13 +#define D0F0xE4_WRAP_8013_Reserved_15_13_WIDTH 3 +#define D0F0xE4_WRAP_8013_Reserved_15_13_MASK 0xe000 +#define D0F0xE4_WRAP_8013_Reserved_16_16_OFFSET 16 +#define D0F0xE4_WRAP_8013_Reserved_16_16_WIDTH 1 +#define D0F0xE4_WRAP_8013_Reserved_16_16_MASK 0x10000 +#define D0F0xE4_WRAP_8013_Reserved_19_17_OFFSET 17 +#define D0F0xE4_WRAP_8013_Reserved_19_17_WIDTH 3 +#define D0F0xE4_WRAP_8013_Reserved_19_17_MASK 0xe0000 +#define D0F0xE4_WRAP_8013_Reserved_20_20_OFFSET 20 +#define D0F0xE4_WRAP_8013_Reserved_20_20_WIDTH 1 +#define D0F0xE4_WRAP_8013_Reserved_20_20_MASK 0x100000 +#define D0F0xE4_WRAP_8013_Reserved_31_21_OFFSET 21 +#define D0F0xE4_WRAP_8013_Reserved_31_21_WIDTH 11 +#define D0F0xE4_WRAP_8013_Reserved_31_21_MASK 0xffe00000 + +/// D0F0xE4_WRAP_8013 +typedef union { + struct { ///< + UINT32 MasterPciePllA:1 ; ///< + UINT32 MasterPciePllB:1 ; ///< + UINT32 MasterPciePllC:1 ; ///< + UINT32 MasterPciePllD:1 ; ///< + UINT32 ClkDividerResetOverrideA:1 ; ///< + UINT32 Reserved_5_5:1 ; ///< + UINT32 Reserved_6_6:1 ; ///< + UINT32 Reserved_7_7:1 ; ///< + UINT32 TxclkSelCoreOverride:1 ; ///< + UINT32 TxclkSelPifAOverride:1 ; ///< + UINT32 Reserved_10_10:1 ; ///< + UINT32 Reserved_11_11:1 ; ///< + UINT32 Reserved_12_12:1 ; ///< + UINT32 Reserved_15_13:3 ; ///< + UINT32 Reserved_16_16:1 ; ///< + UINT32 Reserved_19_17:3 ; ///< + UINT32 Reserved_20_20:1 ; ///< + UINT32 Reserved_31_21:11; ///< + } Field; ///< + UINT32 Value; ///< +} D0F0xE4_WRAP_8013_STRUCT; + +// **** D0F0xE4_WRAP_8014 Register Definition **** +// Address +#define D0F0xE4_WRAP_8014_ADDRESS 0x8014 + +// Field Data +#define D0F0xE4_WRAP_8014_TxclkPermGateEnable_OFFSET 0 +#define D0F0xE4_WRAP_8014_TxclkPermGateEnable_WIDTH 1 +#define D0F0xE4_WRAP_8014_TxclkPermGateEnable_MASK 0x1 +#define D0F0xE4_WRAP_8014_TxclkPrbsGateEnable_OFFSET 1 +#define D0F0xE4_WRAP_8014_TxclkPrbsGateEnable_WIDTH 1 +#define D0F0xE4_WRAP_8014_TxclkPrbsGateEnable_MASK 0x2 +#define D0F0xE4_WRAP_8014_Reserved_2_2_OFFSET 2 +#define D0F0xE4_WRAP_8014_Reserved_2_2_WIDTH 1 +#define D0F0xE4_WRAP_8014_Reserved_2_2_MASK 0x4 +#define D0F0xE4_WRAP_8014_Reserved_3_3_OFFSET 3 +#define D0F0xE4_WRAP_8014_Reserved_3_3_WIDTH 1 +#define D0F0xE4_WRAP_8014_Reserved_3_3_MASK 0x8 +#define D0F0xE4_WRAP_8014_Reserved_4_4_OFFSET 4 +#define D0F0xE4_WRAP_8014_Reserved_4_4_WIDTH 1 +#define D0F0xE4_WRAP_8014_Reserved_4_4_MASK 0x10 +#define D0F0xE4_WRAP_8014_Reserved_5_5_OFFSET 5 +#define D0F0xE4_WRAP_8014_Reserved_5_5_WIDTH 1 +#define D0F0xE4_WRAP_8014_Reserved_5_5_MASK 0x20 +#define D0F0xE4_WRAP_8014_Reserved_6_6_OFFSET 6 +#define D0F0xE4_WRAP_8014_Reserved_6_6_WIDTH 1 +#define D0F0xE4_WRAP_8014_Reserved_6_6_MASK 0x40 +#define D0F0xE4_WRAP_8014_Reserved_7_7_OFFSET 7 +#define D0F0xE4_WRAP_8014_Reserved_7_7_WIDTH 1 +#define D0F0xE4_WRAP_8014_Reserved_7_7_MASK 0x80 +#define D0F0xE4_WRAP_8014_Reserved_8_8_OFFSET 8 +#define D0F0xE4_WRAP_8014_Reserved_8_8_WIDTH 1 +#define D0F0xE4_WRAP_8014_Reserved_8_8_MASK 0x100 +#define D0F0xE4_WRAP_8014_Reserved_9_9_OFFSET 9 +#define D0F0xE4_WRAP_8014_Reserved_9_9_WIDTH 1 +#define D0F0xE4_WRAP_8014_Reserved_9_9_MASK 0x200 +#define D0F0xE4_WRAP_8014_Reserved_10_10_OFFSET 10 +#define D0F0xE4_WRAP_8014_Reserved_10_10_WIDTH 1 +#define D0F0xE4_WRAP_8014_Reserved_10_10_MASK 0x400 +#define D0F0xE4_WRAP_8014_Reserved_11_11_OFFSET 11 +#define D0F0xE4_WRAP_8014_Reserved_11_11_WIDTH 1 +#define D0F0xE4_WRAP_8014_Reserved_11_11_MASK 0x800 +#define D0F0xE4_WRAP_8014_PcieGatePifA1xEnable_OFFSET 12 +#define D0F0xE4_WRAP_8014_PcieGatePifA1xEnable_WIDTH 1 +#define D0F0xE4_WRAP_8014_PcieGatePifA1xEnable_MASK 0x1000 +#define D0F0xE4_WRAP_8014_Reserved_13_13_OFFSET 13 +#define D0F0xE4_WRAP_8014_Reserved_13_13_WIDTH 1 +#define D0F0xE4_WRAP_8014_Reserved_13_13_MASK 0x2000 +#define D0F0xE4_WRAP_8014_Reserved_14_14_OFFSET 14 +#define D0F0xE4_WRAP_8014_Reserved_14_14_WIDTH 1 +#define D0F0xE4_WRAP_8014_Reserved_14_14_MASK 0x4000 +#define D0F0xE4_WRAP_8014_Reserved_15_15_OFFSET 15 +#define D0F0xE4_WRAP_8014_Reserved_15_15_WIDTH 1 +#define D0F0xE4_WRAP_8014_Reserved_15_15_MASK 0x8000 +#define D0F0xE4_WRAP_8014_PcieGatePifA2p5xEnable_OFFSET 16 +#define D0F0xE4_WRAP_8014_PcieGatePifA2p5xEnable_WIDTH 1 +#define D0F0xE4_WRAP_8014_PcieGatePifA2p5xEnable_MASK 0x10000 +#define D0F0xE4_WRAP_8014_Reserved_17_17_OFFSET 17 +#define D0F0xE4_WRAP_8014_Reserved_17_17_WIDTH 1 +#define D0F0xE4_WRAP_8014_Reserved_17_17_MASK 0x20000 +#define D0F0xE4_WRAP_8014_Reserved_18_18_OFFSET 18 +#define D0F0xE4_WRAP_8014_Reserved_18_18_WIDTH 1 +#define D0F0xE4_WRAP_8014_Reserved_18_18_MASK 0x40000 +#define D0F0xE4_WRAP_8014_Reserved_19_19_OFFSET 19 +#define D0F0xE4_WRAP_8014_Reserved_19_19_WIDTH 1 +#define D0F0xE4_WRAP_8014_Reserved_19_19_MASK 0x80000 +#define D0F0xE4_WRAP_8014_TxclkPermGateOnlyWhenPllPwrDn_OFFSET 20 +#define D0F0xE4_WRAP_8014_TxclkPermGateOnlyWhenPllPwrDn_WIDTH 1 +#define D0F0xE4_WRAP_8014_TxclkPermGateOnlyWhenPllPwrDn_MASK 0x100000 +#define D0F0xE4_WRAP_8014_Reserved_31_21_OFFSET 21 +#define D0F0xE4_WRAP_8014_Reserved_31_21_WIDTH 11 +#define D0F0xE4_WRAP_8014_Reserved_31_21_MASK 0xffe00000 + +/// D0F0xE4_WRAP_8014 +typedef union { + struct { + UINT32 TxclkPermGateEnable:1 ; ///< + UINT32 TxclkPrbsGateEnable:1 ; ///< + UINT32 DdiGatePifA1xEnable:1 ; ///< + UINT32 DdiGatePifB1xEnable:1 ; ///< + UINT32 DdiGatePifC1xEnable:1 ; ///< + UINT32 DdiGatePifD1xEnable:1 ; ///< + UINT32 DdiGateDigAEnable:1 ; ///< + UINT32 DdiGateDigBEnable:1 ; ///< + UINT32 DdiGatePifA2p5xEnable:1 ; ///< + UINT32 DdiGatePifB2p5xEnable:1 ; ///< + UINT32 DdiGatePifC2p5xEnable:1 ; ///< + UINT32 DdiGatePifD2p5xEnable:1 ; ///< + UINT32 PcieGatePifA1xEnable:1 ; ///< + UINT32 PcieGatePifB1xEnable:1 ; ///< + UINT32 PcieGatePifC1xEnable:1 ; ///< + UINT32 PcieGatePifD1xEnable:1 ; ///< + UINT32 PcieGatePifA2p5xEnable:1 ; ///< + UINT32 PcieGatePifB2p5xEnable:1 ; ///< + UINT32 PcieGatePifC2p5xEnable:1 ; ///< + UINT32 PcieGatePifD2p5xEnable:1 ; ///< + UINT32 TxclkPermGateOnlyWhenPllPwrDn:1 ; ///< + UINT32 Reserved_31_21:11; ///< + } Field; ///< + UINT32 Value; ///< +} D0F0xE4_WRAP_8014_STRUCT; + +// **** D0F0xE4_WRAP_8016 Register Definition **** +// Address +#define D0F0xE4_WRAP_8016_ADDRESS 0x8016 + +// Type +#define D0F0xE4_WRAP_8016_TYPE TYPE_D0F0xE4 +// Field Data +#define D0F0xE4_WRAP_8016_CalibAckLatency_OFFSET 0 +#define D0F0xE4_WRAP_8016_CalibAckLatency_WIDTH 6 +#define D0F0xE4_WRAP_8016_CalibAckLatency_MASK 0x3f +#define D0F0xE4_WRAP_8016_Reserved_21_6_OFFSET 6 +#define D0F0xE4_WRAP_8016_Reserved_21_6_WIDTH 16 +#define D0F0xE4_WRAP_8016_Reserved_21_6_MASK 0x3fffc0 +#define D0F0xE4_WRAP_8016_LclkGateFree_OFFSET 22 +#define D0F0xE4_WRAP_8016_LclkGateFree_WIDTH 1 +#define D0F0xE4_WRAP_8016_LclkGateFree_MASK 0x400000 +#define D0F0xE4_WRAP_8016_LclkDynGateEnable_OFFSET 23 +#define D0F0xE4_WRAP_8016_LclkDynGateEnable_WIDTH 1 +#define D0F0xE4_WRAP_8016_LclkDynGateEnable_MASK 0x800000 +#define D0F0xE4_WRAP_8016_Reserved_31_24_OFFSET 24 +#define D0F0xE4_WRAP_8016_Reserved_31_24_WIDTH 8 +#define D0F0xE4_WRAP_8016_Reserved_31_24_MASK 0xff000000 + +/// D0F0xE4_WRAP_8016 +typedef union { + struct { ///< + UINT32 CalibAckLatency:6 ; ///< + UINT32 Reserved_21_6:16; ///< + UINT32 LclkGateFree:1 ; ///< + UINT32 LclkDynGateEnable:1 ; ///< + UINT32 Reserved_31_24:8 ; ///< + } Field; ///< + UINT32 Value; ///< +} D0F0xE4_WRAP_8016_STRUCT; + // **** D0F0xE4_WRAP_8021 Register Definition **** // Address #define D0F0xE4_WRAP_8021_ADDRESS 0x8021 @@ -4905,9 +6620,18 @@ typedef union { #define D0F0xE4_WRAP_8060_ResetComplete_OFFSET 2 #define D0F0xE4_WRAP_8060_ResetComplete_WIDTH 1 #define D0F0xE4_WRAP_8060_ResetComplete_MASK 0x4 -#define D0F0xE4_WRAP_8060_Reserved_31_3_OFFSET 3 -#define D0F0xE4_WRAP_8060_Reserved_31_3_WIDTH 29 -#define D0F0xE4_WRAP_8060_Reserved_31_3_MASK 0xfffffff8 +#define D0F0xE4_WRAP_8060_Reserved_15_3_OFFSET 3 +#define D0F0xE4_WRAP_8060_Reserved_15_3_WIDTH 13 +#define D0F0xE4_WRAP_8060_Reserved_15_3_MASK 0xfff8 +#define D0F0xE4_WRAP_8060_BifGlobalReset_OFFSET 16 +#define D0F0xE4_WRAP_8060_BifGlobalReset_WIDTH 1 +#define D0F0xE4_WRAP_8060_BifGlobalReset_MASK 0x10000 +#define D0F0xE4_WRAP_8060_BifCalibrationReset_OFFSET 17 +#define D0F0xE4_WRAP_8060_BifCalibrationReset_WIDTH 1 +#define D0F0xE4_WRAP_8060_BifCalibrationReset_MASK 0x20000 +#define D0F0xE4_WRAP_8060_Reserved_31_18_OFFSET 18 +#define D0F0xE4_WRAP_8060_Reserved_31_18_WIDTH 14 +#define D0F0xE4_WRAP_8060_Reserved_31_18_MASK 0xfffc0000 /// D0F0xE4_WRAP_8060 typedef union { @@ -4915,7 +6639,10 @@ typedef union { UINT32 Reconfigure:1 ; ///< UINT32 Reserved_1_1:1 ; ///< UINT32 ResetComplete:1 ; ///< - UINT32 Reserved_31_3:29; ///< + UINT32 Reserved_15_3:13; ///< + UINT32 BifGlobalReset:1 ; ///< + UINT32 BifCalibrationReset:1 ; ///< + UINT32 Reserved_31_18:14; ///< } Field; ///< UINT32 Value; ///< } D0F0xE4_WRAP_8060_STRUCT; @@ -5002,6 +6729,25 @@ typedef union { UINT32 Value; ///< } D0F0xE4_WRAP_8062_STRUCT; +// **** D0F0xE4_WRAP_80F0 Register Definition **** +// Address +#define D0F0xE4_WRAP_80F0_ADDRESS 0x80f0 + +// Type +#define D0F0xE4_WRAP_80F0_TYPE TYPE_D0F0xE4 +// Field Data +#define D0F0xE4_WRAP_80F0_MicroSeconds_OFFSET 0 +#define D0F0xE4_WRAP_80F0_MicroSeconds_WIDTH 32 +#define D0F0xE4_WRAP_80F0_MicroSeconds_MASK 0xffffffff + +/// D0F0xE4_WRAP_80F0 +typedef union { + struct { ///< + UINT32 MicroSeconds:32; ///< + } Field; ///< + UINT32 Value; ///< +} D0F0xE4_WRAP_80F0_STRUCT; + // **** D0F0xE4_x0108_8071 Register Definition **** // Address #define D0F0xE4_x0108_8071_ADDRESS 0x1088071 @@ -5370,6 +7116,41 @@ typedef union { UINT32 Value; ///< } D0F0xE4_CORE_0002_STRUCT; +// **** D0F0xE4_CORE_0010 Register Definition **** +// Address +#define D0F0xE4_CORE_0010_ADDRESS 0x10 + +// Type +#define D0F0xE4_CORE_0010_TYPE TYPE_D0F0xE4 +// Field Data +#define D0F0xE4_CORE_0010_HwInitWrLock_OFFSET 0 +#define D0F0xE4_CORE_0010_HwInitWrLock_WIDTH 1 +#define D0F0xE4_CORE_0010_HwInitWrLock_MASK 0x1 +#define D0F0xE4_CORE_0010_Reserved_8_1_OFFSET 1 +#define D0F0xE4_CORE_0010_Reserved_8_1_WIDTH 8 +#define D0F0xE4_CORE_0010_Reserved_8_1_MASK 0x1fe +#define D0F0xE4_CORE_0010_UmiNpMemWrite_OFFSET 9 +#define D0F0xE4_CORE_0010_UmiNpMemWrite_WIDTH 1 +#define D0F0xE4_CORE_0010_UmiNpMemWrite_MASK 0x200 +#define D0F0xE4_CORE_0010_RxSbAdjPayloadSize_OFFSET 10 +#define D0F0xE4_CORE_0010_RxSbAdjPayloadSize_WIDTH 3 +#define D0F0xE4_CORE_0010_RxSbAdjPayloadSize_MASK 0x1c00 +#define D0F0xE4_CORE_0010_Reserved_31_13_OFFSET 13 +#define D0F0xE4_CORE_0010_Reserved_31_13_WIDTH 19 +#define D0F0xE4_CORE_0010_Reserved_31_13_MASK 0xffffe000 + +/// D0F0xE4_CORE_0010 +typedef union { + struct { ///< + UINT32 HwInitWrLock:1 ; ///< + UINT32 Reserved_8_1:8 ; ///< + UINT32 UmiNpMemWrite:1 ; ///< + UINT32 RxSbAdjPayloadSize:3 ; ///< + UINT32 Reserved_31_13:19; ///< + } Field; ///< + UINT32 Value; ///< +} D0F0xE4_CORE_0010_STRUCT; + // **** D0F0xE4_CORE_0011 Register Definition **** // Address #define D0F0xE4_CORE_0011_ADDRESS 0x11 @@ -5424,6 +7205,33 @@ typedef union { UINT32 Value; ///< } D0F0xE4_CORE_001C_STRUCT; +// **** D0F0xE4_CORE_0020 Register Definition **** +// Address +#define D0F0xE4_CORE_0020_ADDRESS 0x20 + +// Type +#define D0F0xE4_CORE_0020_TYPE TYPE_D0F0xE4 +// Field Data +#define D0F0xE4_CORE_0020_Reserved_8_0_OFFSET 0 +#define D0F0xE4_CORE_0020_Reserved_8_0_WIDTH 9 +#define D0F0xE4_CORE_0020_Reserved_8_0_MASK 0x1ff +#define D0F0xE4_CORE_0020_CiRcOrderingDis_OFFSET 9 +#define D0F0xE4_CORE_0020_CiRcOrderingDis_WIDTH 1 +#define D0F0xE4_CORE_0020_CiRcOrderingDis_MASK 0x200 +#define D0F0xE4_CORE_0020_Reserved_31_10_OFFSET 10 +#define D0F0xE4_CORE_0020_Reserved_31_10_WIDTH 22 +#define D0F0xE4_CORE_0020_Reserved_31_10_MASK 0xfffffc00 + +/// D0F0xE4_CORE_0020 +typedef union { + struct { ///< + UINT32 Reserved_8_0:9 ; ///< + UINT32 CiRcOrderingDis:1 ; ///< + UINT32 Reserved_31_10:22; ///< + } Field; ///< + UINT32 Value; ///< +} D0F0xE4_CORE_0020_STRUCT; + // **** D0F0xE4_CORE_0040 Register Definition **** // Address #define D0F0xE4_CORE_0040_ADDRESS 0x40 @@ -5451,6 +7259,33 @@ typedef union { UINT32 Value; ///< } D0F0xE4_CORE_0040_STRUCT; +// **** D0F0xE4_CORE_00B0 Register Definition **** +// Address +#define D0F0xE4_CORE_00B0_ADDRESS 0xb0 + +// Type +#define D0F0xE4_CORE_00B0_TYPE TYPE_D0F0xE4 +// Field Data +#define D0F0xE4_CORE_00B0_Reserved_1_0_OFFSET 0 +#define D0F0xE4_CORE_00B0_Reserved_1_0_WIDTH 2 +#define D0F0xE4_CORE_00B0_Reserved_1_0_MASK 0x3 +#define D0F0xE4_CORE_00B0_StrapF0MsiEn_OFFSET 2 +#define D0F0xE4_CORE_00B0_StrapF0MsiEn_WIDTH 1 +#define D0F0xE4_CORE_00B0_StrapF0MsiEn_MASK 0x4 +#define D0F0xE4_CORE_00B0_Reserved_31_3_OFFSET 3 +#define D0F0xE4_CORE_00B0_Reserved_31_3_WIDTH 29 +#define D0F0xE4_CORE_00B0_Reserved_31_3_MASK 0xfffffff8 + +/// D0F0xE4_CORE_00B0 +typedef union { + struct { ///< + UINT32 Reserved_1_0:2 ; ///< + UINT32 StrapF0MsiEn:1 ; ///< + UINT32 Reserved_31_3:29; ///< + } Field; ///< + UINT32 Value; ///< +} D0F0xE4_CORE_00B0_STRUCT; + // **** D0F0xE4_CORE_00C0 Register Definition **** // Address #define D0F0xE4_CORE_00C0_ADDRESS 0xc0 @@ -5891,6 +7726,53 @@ typedef union { UINT32 Value; ///< } DxF0xE4_xA4_STRUCT; +// **** DxF0xE4_xA5 Register Definition **** +// Address +#define DxF0xE4_xA5_ADDRESS 0xa5 + +// Type +#define DxF0xE4_xA5_TYPE TYPE_D4F0xE4 +// Field Data +#define DxF0xE4_xA5_LcCurrentState_OFFSET 0 +#define DxF0xE4_xA5_LcCurrentState_WIDTH 6 +#define DxF0xE4_xA5_LcCurrentState_MASK 0x3f +#define DxF0xE4_xA5_Reserved_7_6_OFFSET 6 +#define DxF0xE4_xA5_Reserved_7_6_WIDTH 2 +#define DxF0xE4_xA5_Reserved_7_6_MASK 0xc0 +#define DxF0xE4_xA5_LcPrevState1_OFFSET 8 +#define DxF0xE4_xA5_LcPrevState1_WIDTH 6 +#define DxF0xE4_xA5_LcPrevState1_MASK 0x3f00 +#define DxF0xE4_xA5_Reserved_15_14_OFFSET 14 +#define DxF0xE4_xA5_Reserved_15_14_WIDTH 2 +#define DxF0xE4_xA5_Reserved_15_14_MASK 0xc000 +#define DxF0xE4_xA5_LcPrevState2_OFFSET 16 +#define DxF0xE4_xA5_LcPrevState2_WIDTH 6 +#define DxF0xE4_xA5_LcPrevState2_MASK 0x3f0000 +#define DxF0xE4_xA5_Reserved_23_22_OFFSET 22 +#define DxF0xE4_xA5_Reserved_23_22_WIDTH 2 +#define DxF0xE4_xA5_Reserved_23_22_MASK 0xc00000 +#define DxF0xE4_xA5_LcPrevState3_OFFSET 24 +#define DxF0xE4_xA5_LcPrevState3_WIDTH 6 +#define DxF0xE4_xA5_LcPrevState3_MASK 0x3f000000 +#define DxF0xE4_xA5_Reserved_31_30_OFFSET 30 +#define DxF0xE4_xA5_Reserved_31_30_WIDTH 2 +#define DxF0xE4_xA5_Reserved_31_30_MASK 0xc0000000 + +/// DxF0xE4_xA5 +typedef union { + struct { ///< + UINT32 LcCurrentState:6 ; ///< + UINT32 Reserved_7_6:2 ; ///< + UINT32 LcPrevState1:6 ; ///< + UINT32 Reserved_15_14:2 ; ///< + UINT32 LcPrevState2:6 ; ///< + UINT32 Reserved_23_22:2 ; ///< + UINT32 LcPrevState3:6 ; ///< + UINT32 Reserved_31_30:2 ; ///< + } Field; ///< + UINT32 Value; ///< +} DxF0xE4_xA5_STRUCT; + // **** DxF0xE4_xB1 Register Definition **** // Address #define DxF0xE4_xB1_ADDRESS 0xb1 @@ -5922,6 +7804,57 @@ typedef union { UINT32 Value; ///< } DxF0xE4_xB1_STRUCT; +// **** DxF0xE4_xB5 Register Definition **** +// Address +#define DxF0xE4_xB5_ADDRESS 0xb5 + +// Type +#define DxF0xE4_xB5_TYPE TYPE_D4F0xE4 +// Field Data +#define DxF0xE4_xB5_LcSelectDeemphasis_OFFSET 0 +#define DxF0xE4_xB5_LcSelectDeemphasis_WIDTH 1 +#define DxF0xE4_xB5_LcSelectDeemphasis_MASK 0x1 +#define DxF0xE4_xB5_LcSelectDeemphasisCntl_OFFSET 1 +#define DxF0xE4_xB5_LcSelectDeemphasisCntl_WIDTH 2 +#define DxF0xE4_xB5_LcSelectDeemphasisCntl_MASK 0x6 +#define DxF0xE4_xB5_LcRcvdDeemphasis_OFFSET 3 +#define DxF0xE4_xB5_LcRcvdDeemphasis_WIDTH 1 +#define DxF0xE4_xB5_LcRcvdDeemphasis_MASK 0x8 +#define DxF0xE4_xB5_Reserved_9_4_OFFSET 4 +#define DxF0xE4_xB5_Reserved_9_4_WIDTH 6 +#define DxF0xE4_xB5_Reserved_9_4_MASK 0x3f0 +#define DxF0xE4_xB5_LcEnhancedHotPlugEn_OFFSET 10 +#define DxF0xE4_xB5_LcEnhancedHotPlugEn_WIDTH 1 +#define DxF0xE4_xB5_LcEnhancedHotPlugEn_MASK 0x400 +#define DxF0xE4_xB5_Reserved_11_11_OFFSET 11 +#define DxF0xE4_xB5_Reserved_11_11_WIDTH 1 +#define DxF0xE4_xB5_Reserved_11_11_MASK 0x800 +#define DxF0xE4_xB5_LcEhpRxPhyCmd_OFFSET 12 +#define DxF0xE4_xB5_LcEhpRxPhyCmd_WIDTH 2 +#define DxF0xE4_xB5_LcEhpRxPhyCmd_MASK 0x3000 +#define DxF0xE4_xB5_LcEhpTxPhyCmd_OFFSET 14 +#define DxF0xE4_xB5_LcEhpTxPhyCmd_WIDTH 2 +#define DxF0xE4_xB5_LcEhpTxPhyCmd_MASK 0xc000 +#define DxF0xE4_xB5_Reserved_31_16_OFFSET 16 +#define DxF0xE4_xB5_Reserved_31_16_WIDTH 16 +#define DxF0xE4_xB5_Reserved_31_16_MASK 0xffff0000 + +/// DxF0xE4_xB5 +typedef union { + struct { ///< + UINT32 LcSelectDeemphasis:1 ; ///< + UINT32 LcSelectDeemphasisCntl:2 ; ///< + UINT32 LcRcvdDeemphasis:1 ; ///< + UINT32 Reserved_9_4:6 ; ///< + UINT32 LcEnhancedHotPlugEn:1 ; ///< + UINT32 Reserved_11_11:1 ; ///< + UINT32 LcEhpRxPhyCmd:2 ; ///< + UINT32 LcEhpTxPhyCmd:2 ; ///< + UINT32 Reserved_31_16:16; ///< + } Field; ///< + UINT32 Value; ///< +} DxF0xE4_xB5_STRUCT; + // **** DxF0xE4_xC0 Register Definition **** // Address #define DxF0xE4_xC0_ADDRESS 0xc0 @@ -5984,6 +7917,134 @@ typedef union { UINT32 Value; ///< } DxF0xE4_xC1_STRUCT; +// **** SMUx01 Register Definition **** +// Address +#define SMUx01_ADDRESS 0x1 + +// Type +#define SMUx01_TYPE TYPE_SMU +// Field Data +#define SMUx01_RamSwitch_OFFSET 0 +#define SMUx01_RamSwitch_WIDTH 1 +#define SMUx01_RamSwitch_MASK 0x1 +#define SMUx01_Reset_OFFSET 1 +#define SMUx01_Reset_WIDTH 1 +#define SMUx01_Reset_MASK 0x2 +#define SMUx01_Reserved_17_2_OFFSET 2 +#define SMUx01_Reserved_17_2_WIDTH 16 +#define SMUx01_Reserved_17_2_MASK 0x3fffc +#define SMUx01_VectorOverride_OFFSET 18 +#define SMUx01_VectorOverride_WIDTH 1 +#define SMUx01_VectorOverride_MASK 0x40000 +#define SMUx01_Reserved_31_19_OFFSET 19 +#define SMUx01_Reserved_31_19_WIDTH 13 +#define SMUx01_Reserved_31_19_MASK 0xfff80000 + +/// SMUx01 +typedef union { + struct { ///< + UINT32 RamSwitch:1 ; ///< + UINT32 Reset:1 ; ///< + UINT32 Reserved_17_2:16; ///< + UINT32 VectorOverride:1 ; ///< + UINT32 Reserved_31_19:13; ///< + } Field; ///< + UINT32 Value; ///< +} SMUx01_STRUCT; + +// **** SMUx03 Register Definition **** +// Address +#define SMUx03_ADDRESS 0x3 + +// Type +#define SMUx03_TYPE TYPE_SMU +// Field Data +#define SMUx03_IntReq_OFFSET 0 +#define SMUx03_IntReq_WIDTH 1 +#define SMUx03_IntReq_MASK 0x1 +#define SMUx03_IntAck_OFFSET 1 +#define SMUx03_IntAck_WIDTH 1 +#define SMUx03_IntAck_MASK 0x2 +#define SMUx03_IntDone_OFFSET 2 +#define SMUx03_IntDone_WIDTH 1 +#define SMUx03_IntDone_MASK 0x4 +#define SMUx03_ServiceIndex_OFFSET 3 +#define SMUx03_ServiceIndex_WIDTH 8 +#define SMUx03_ServiceIndex_MASK 0x7f8 +#define SMUx03_Reserved_31_11_OFFSET 11 +#define SMUx03_Reserved_31_11_WIDTH 21 +#define SMUx03_Reserved_31_11_MASK 0xfffff800 + +/// SMUx03 +typedef union { + struct { ///< + UINT32 IntReq:1 ; ///< + UINT32 IntAck:1 ; ///< + UINT32 IntDone:1 ; ///< + UINT32 ServiceIndex:8 ; ///< + UINT32 Reserved_31_11:21; ///< + } Field; ///< + UINT32 Value; ///< +} SMUx03_STRUCT; + +// **** SMUx05 Register Definition **** +// Address +#define SMUx05_ADDRESS 0x5 + +// Type +#define SMUx05_TYPE TYPE_SMU +// Field Data +#define SMUx05_McuRam_OFFSET 0 +#define SMUx05_McuRam_WIDTH 32 +#define SMUx05_McuRam_MASK 0xffffffff + +/// SMUx05 +typedef union { + struct { ///< + UINT32 McuRam:32; ///< + } Field; ///< + UINT32 Value; ///< +} SMUx05_STRUCT; + +// **** SMUx0B_x8580 Register Definition **** +// Address +#define SMUx0B_x8580_ADDRESS 0x8580 + +// Type +#define SMUx0B_x8580_TYPE TYPE_SMUx0B +// Field Data +#define SMUx0B_x8580_Reserved_0_0_OFFSET 0 +#define SMUx0B_x8580_Reserved_0_0_WIDTH 1 +#define SMUx0B_x8580_Reserved_0_0_MASK 0x1 +#define SMUx0B_x8580_Reserved_9_1_OFFSET 1 +#define SMUx0B_x8580_Reserved_9_1_WIDTH 9 +#define SMUx0B_x8580_Reserved_9_1_MASK 0x3fe +#define SMUx0B_x8580_Reserved_10_10_OFFSET 10 +#define SMUx0B_x8580_Reserved_10_10_WIDTH 1 +#define SMUx0B_x8580_Reserved_10_10_MASK 0x400 +#define SMUx0B_x8580_Reserved_11_11_OFFSET 11 +#define SMUx0B_x8580_Reserved_11_11_WIDTH 1 +#define SMUx0B_x8580_Reserved_11_11_MASK 0x800 +#define SMUx0B_x8580_Reserved_15_12_OFFSET 12 +#define SMUx0B_x8580_Reserved_15_12_WIDTH 4 +#define SMUx0B_x8580_Reserved_15_12_MASK 0xf000 +#define SMUx0B_x8580_Reserved_31_16_OFFSET 16 +#define SMUx0B_x8580_Reserved_31_16_WIDTH 16 +#define SMUx0B_x8580_Reserved_31_16_MASK 0xffff0000 + +/// SMUx0B_x8580 +typedef union { + struct { ///< + UINT32 PdmEn:1 ; ///< + UINT32 Reserved_9_1:9 ; ///< + UINT32 PdmCacEn:1 ; ///< + UINT32 PdmParamLoc:1 ; ///< + UINT32 PdmUnit:4 ; ///< + UINT32 PdmPeriod:16; ///< + } Field; ///< + UINT32 Value; ///< +} SMUx0B_x8580_STRUCT; + // **** SMUx0B_x8600 Register Definition **** // Address #define SMUx0B_x8600_ADDRESS 0x8600 @@ -7054,6 +9115,173 @@ typedef union { UINT32 Value; ///< } SMUx0B_x86A0_STRUCT; +// **** SMUx1B Register Definition **** +// Address +#define SMUx1B_ADDRESS 0x1b + +// Type +#define SMUx1B_TYPE TYPE_SMU +// Field Data +#define SMUx1B_LclkDpSlpDiv_OFFSET 0 +#define SMUx1B_LclkDpSlpDiv_WIDTH 3 +#define SMUx1B_LclkDpSlpDiv_MASK 0x7 +#define SMUx1B_RampDis_OFFSET 3 +#define SMUx1B_RampDis_WIDTH 1 +#define SMUx1B_RampDis_MASK 0x8 +#define SMUx1B_Reserved_7_4_OFFSET 4 +#define SMUx1B_Reserved_7_4_WIDTH 4 +#define SMUx1B_Reserved_7_4_MASK 0xf0 +#define SMUx1B_LclkDpSlpMask_OFFSET 8 +#define SMUx1B_LclkDpSlpMask_WIDTH 8 +#define SMUx1B_LclkDpSlpMask_MASK 0xff00 + +/// SMUx1B +typedef union { + struct { ///< + UINT32 LclkDpSlpDiv:3 ; ///< + UINT32 RampDis:1 ; ///< + UINT32 Reserved_7_4:4 ; ///< + UINT32 LclkDpSlpMask:8 ; ///< + } Field; ///< + UINT32 Value; ///< +} SMUx1B_STRUCT; + +// **** SMUx1D Register Definition **** +// Address +#define SMUx1D_ADDRESS 0x1d + +// Type +#define SMUx1D_TYPE TYPE_SMU +// Field Data +#define SMUx1D_LclkDpSlpHyst_OFFSET 0 +#define SMUx1D_LclkDpSlpHyst_WIDTH 12 +#define SMUx1D_LclkDpSlpHyst_MASK 0xfff +#define SMUx1D_LclkDpSlpEn_OFFSET 12 +#define SMUx1D_LclkDpSlpEn_WIDTH 1 +#define SMUx1D_LclkDpSlpEn_MASK 0x1000 +#define SMUx1D_Reserved_15_13_OFFSET 13 +#define SMUx1D_Reserved_15_13_WIDTH 3 +#define SMUx1D_Reserved_15_13_MASK 0xe000 + +/// SMUx1D +typedef union { + struct { ///< + UINT32 LclkDpSlpHyst:12; ///< + UINT32 LclkDpSlpEn:1 ; ///< + UINT32 Reserved_15_13:3 ; ///< + } Field; ///< + UINT32 Value; ///< +} SMUx1D_STRUCT; + +// **** SMUx6F Register Definition **** +// Address +#define SMUx6F_ADDRESS 0x6f + +// Type +#define SMUx6F_TYPE TYPE_SMU +// Field Data +#define SMUx6F_OnDelay_OFFSET 0 +#define SMUx6F_OnDelay_WIDTH 4 +#define SMUx6F_OnDelay_MASK 0xf +#define SMUx6F_OffDelay_OFFSET 4 +#define SMUx6F_OffDelay_WIDTH 8 +#define SMUx6F_OffDelay_MASK 0xff0 +#define SMUx6F_Reserved_20_12_OFFSET 12 +#define SMUx6F_Reserved_20_12_WIDTH 9 +#define SMUx6F_Reserved_20_12_MASK 0x1ff000 +#define SMUx6F_RampDis0_OFFSET 21 +#define SMUx6F_RampDis0_WIDTH 1 +#define SMUx6F_RampDis0_MASK 0x200000 +#define SMUx6F_RampDisReg_OFFSET 22 +#define SMUx6F_RampDisReg_WIDTH 1 +#define SMUx6F_RampDisReg_MASK 0x400000 +#define SMUx6F_Reserved_31_23_OFFSET 23 +#define SMUx6F_Reserved_31_23_WIDTH 9 +#define SMUx6F_Reserved_31_23_MASK 0xff800000 + +/// SMUx6F +typedef union { + struct { ///< + UINT32 OnDelay:4 ; ///< + UINT32 OffDelay:8 ; ///< + UINT32 Reserved_20_12:9 ; ///< + UINT32 RampDis0:1 ; ///< + UINT32 RampDisReg:1 ; ///< + UINT32 Reserved_31_23:9 ; ///< + } Field; ///< + UINT32 Value; ///< +} SMUx6F_STRUCT; + +// **** SMUx71 Register Definition **** +// Address +#define SMUx71_ADDRESS 0x71 + +// Type +#define SMUx71_TYPE TYPE_SMU +// Field Data +#define SMUx71_OnDelay_OFFSET 0 +#define SMUx71_OnDelay_WIDTH 4 +#define SMUx71_OnDelay_MASK 0xf +#define SMUx71_OffDelay_OFFSET 4 +#define SMUx71_OffDelay_WIDTH 8 +#define SMUx71_OffDelay_MASK 0xff0 +#define SMUx71_Reserved_19_12_OFFSET 12 +#define SMUx71_Reserved_19_12_WIDTH 8 +#define SMUx71_Reserved_19_12_MASK 0xff000 +#define SMUx71_RampDis1_OFFSET 20 +#define SMUx71_RampDis1_WIDTH 1 +#define SMUx71_RampDis1_MASK 0x100000 +#define SMUx71_RampDis0_OFFSET 21 +#define SMUx71_RampDis0_WIDTH 1 +#define SMUx71_RampDis0_MASK 0x200000 +#define SMUx71_RampDisReg_OFFSET 22 +#define SMUx71_RampDisReg_WIDTH 1 +#define SMUx71_RampDisReg_MASK 0x400000 +#define SMUx71_Reserved_31_23_OFFSET 23 +#define SMUx71_Reserved_31_23_WIDTH 9 +#define SMUx71_Reserved_31_23_MASK 0xff800000 + +/// SMUx71 +typedef union { + struct { ///< + UINT32 OnDelay:4 ; ///< + UINT32 OffDelay:8 ; ///< + UINT32 Reserved_19_12:8 ; ///< + UINT32 RampDis1:1 ; ///< + UINT32 RampDis0:1 ; ///< + UINT32 RampDisReg:1 ; ///< + UINT32 Reserved_31_23:9 ; ///< + } Field; ///< + UINT32 Value; ///< +} SMUx71_STRUCT; + +// **** SMUx73 Register Definition **** +// Address +#define SMUx73_ADDRESS 0x73 + +// Type +#define SMUx73_TYPE TYPE_SMU +// Field Data +#define SMUx73_DisLclkGating_OFFSET 0 +#define SMUx73_DisLclkGating_WIDTH 1 +#define SMUx73_DisLclkGating_MASK 0x1 +#define SMUx73_DisSclkGating_OFFSET 1 +#define SMUx73_DisSclkGating_WIDTH 1 +#define SMUx73_DisSclkGating_MASK 0x2 +#define SMUx73_Reserved_15_2_OFFSET 2 +#define SMUx73_Reserved_15_2_WIDTH 14 +#define SMUx73_Reserved_15_2_MASK 0xfffc + +/// SMUx73 +typedef union { + struct { ///< + UINT32 DisLclkGating:1 ; ///< + UINT32 DisSclkGating:1 ; ///< + UINT32 Reserved_15_2:14; ///< + } Field; ///< + UINT32 Value; ///< +} SMUx73_STRUCT; + // **** GMMx00 Register Definition **** // Address #define GMMx00_ADDRESS 0x0 @@ -7255,6 +9483,53 @@ typedef union { UINT32 Value; ///< } GMMx2018_STRUCT; +// **** GMMx201C Register Definition **** +// Address +#define GMMx201C_ADDRESS 0x201c + +// Type +#define GMMx201C_TYPE TYPE_GMM +// Field Data +#define GMMx201C_UvdExt0_OFFSET 0 +#define GMMx201C_UvdExt0_WIDTH 4 +#define GMMx201C_UvdExt0_MASK 0xf +#define GMMx201C_DrmDma_OFFSET 4 +#define GMMx201C_DrmDma_WIDTH 4 +#define GMMx201C_DrmDma_MASK 0xf0 +#define GMMx201C_Hdp_OFFSET 8 +#define GMMx201C_Hdp_WIDTH 4 +#define GMMx201C_Hdp_MASK 0xf00 +#define GMMx201C_Sem_OFFSET 12 +#define GMMx201C_Sem_WIDTH 4 +#define GMMx201C_Sem_MASK 0xf000 +#define GMMx201C_Umc_OFFSET 16 +#define GMMx201C_Umc_WIDTH 4 +#define GMMx201C_Umc_MASK 0xf0000 +#define GMMx201C_Uvd_OFFSET 20 +#define GMMx201C_Uvd_WIDTH 4 +#define GMMx201C_Uvd_MASK 0xf00000 +#define GMMx201C_UvdExt1_OFFSET 24 +#define GMMx201C_UvdExt1_WIDTH 4 +#define GMMx201C_UvdExt1_MASK 0xf000000 +#define GMMx201C_Reserved_31_28_OFFSET 28 +#define GMMx201C_Reserved_31_28_WIDTH 4 +#define GMMx201C_Reserved_31_28_MASK 0xf0000000 + +/// GMMx201C +typedef union { + struct { ///< + UINT32 UvdExt0:4 ; ///< + UINT32 DrmDma:4 ; ///< + UINT32 Hdp:4 ; ///< + UINT32 Sem:4 ; ///< + UINT32 Umc:4 ; ///< + UINT32 Uvd:4 ; ///< + UINT32 UvdExt1:4 ; ///< + UINT32 Reserved_31_28:4 ; ///< + } Field; ///< + UINT32 Value; ///< +} GMMx201C_STRUCT; + // **** GMMx2020 Register Definition **** // Address #define GMMx2020_ADDRESS 0x2020 @@ -7529,6 +9804,854 @@ typedef union { UINT32 Value; ///< } GMMx20EC_STRUCT; +// **** GMMx2160 Register Definition **** +// Address +#define GMMx2160_ADDRESS 0x2160 + +// Type +#define GMMx2160_TYPE TYPE_GMM +// Field Data +#define GMMx2160_Enable_OFFSET 0 +#define GMMx2160_Enable_WIDTH 1 +#define GMMx2160_Enable_MASK 0x1 +#define GMMx2160_Prescale_OFFSET 1 +#define GMMx2160_Prescale_WIDTH 2 +#define GMMx2160_Prescale_MASK 0x6 +#define GMMx2160_BlackoutExempt_OFFSET 3 +#define GMMx2160_BlackoutExempt_WIDTH 1 +#define GMMx2160_BlackoutExempt_MASK 0x8 +#define GMMx2160_StallMode_OFFSET 4 +#define GMMx2160_StallMode_WIDTH 2 +#define GMMx2160_StallMode_MASK 0x30 +#define GMMx2160_StallOverride_OFFSET 6 +#define GMMx2160_StallOverride_WIDTH 1 +#define GMMx2160_StallOverride_MASK 0x40 +#define GMMx2160_MaxBurst_OFFSET 7 +#define GMMx2160_MaxBurst_WIDTH 4 +#define GMMx2160_MaxBurst_MASK 0x780 +#define GMMx2160_LazyTimer_OFFSET 11 +#define GMMx2160_LazyTimer_WIDTH 4 +#define GMMx2160_LazyTimer_MASK 0x7800 +#define GMMx2160_StallOverrideWtm_OFFSET 15 +#define GMMx2160_StallOverrideWtm_WIDTH 1 +#define GMMx2160_StallOverrideWtm_MASK 0x8000 +#define GMMx2160_Reserved_19_16_OFFSET 16 +#define GMMx2160_Reserved_19_16_WIDTH 4 +#define GMMx2160_Reserved_19_16_MASK 0xf0000 +#define GMMx2160_Reserved_31_20_OFFSET 20 +#define GMMx2160_Reserved_31_20_WIDTH 12 +#define GMMx2160_Reserved_31_20_MASK 0xfff00000 + +/// GMMx2160 +typedef union { + struct { ///< + UINT32 Enable:1 ; ///< + UINT32 Prescale:2 ; ///< + UINT32 BlackoutExempt:1 ; ///< + UINT32 StallMode:2 ; ///< + UINT32 StallOverride:1 ; ///< + UINT32 MaxBurst:4 ; ///< + UINT32 LazyTimer:4 ; ///< + UINT32 StallOverrideWtm:1 ; ///< + UINT32 Reserved_19_16:4 ; ///< + UINT32 Reserved_31_20:12; ///< + } Field; ///< + UINT32 Value; ///< +} GMMx2160_STRUCT; + +// **** GMMx2164 Register Definition **** +// Address +#define GMMx2164_ADDRESS 0x2164 + +// Type +#define GMMx2164_TYPE TYPE_GMM +// Field Data +#define GMMx2164_Enable_OFFSET 0 +#define GMMx2164_Enable_WIDTH 1 +#define GMMx2164_Enable_MASK 0x1 +#define GMMx2164_Prescale_OFFSET 1 +#define GMMx2164_Prescale_WIDTH 2 +#define GMMx2164_Prescale_MASK 0x6 +#define GMMx2164_BlackoutExempt_OFFSET 3 +#define GMMx2164_BlackoutExempt_WIDTH 1 +#define GMMx2164_BlackoutExempt_MASK 0x8 +#define GMMx2164_StallMode_OFFSET 4 +#define GMMx2164_StallMode_WIDTH 2 +#define GMMx2164_StallMode_MASK 0x30 +#define GMMx2164_StallOverride_OFFSET 6 +#define GMMx2164_StallOverride_WIDTH 1 +#define GMMx2164_StallOverride_MASK 0x40 +#define GMMx2164_MaxBurst_OFFSET 7 +#define GMMx2164_MaxBurst_WIDTH 4 +#define GMMx2164_MaxBurst_MASK 0x780 +#define GMMx2164_LazyTimer_OFFSET 11 +#define GMMx2164_LazyTimer_WIDTH 4 +#define GMMx2164_LazyTimer_MASK 0x7800 +#define GMMx2164_StallOverrideWtm_OFFSET 15 +#define GMMx2164_StallOverrideWtm_WIDTH 1 +#define GMMx2164_StallOverrideWtm_MASK 0x8000 +#define GMMx2164_Reserved_19_16_OFFSET 16 +#define GMMx2164_Reserved_19_16_WIDTH 4 +#define GMMx2164_Reserved_19_16_MASK 0xf0000 +#define GMMx2164_Reserved_31_20_OFFSET 20 +#define GMMx2164_Reserved_31_20_WIDTH 12 +#define GMMx2164_Reserved_31_20_MASK 0xfff00000 + +/// GMMx2164 +typedef union { + struct { ///< + UINT32 Enable:1 ; ///< + UINT32 Prescale:2 ; ///< + UINT32 BlackoutExempt:1 ; ///< + UINT32 StallMode:2 ; ///< + UINT32 StallOverride:1 ; ///< + UINT32 MaxBurst:4 ; ///< + UINT32 LazyTimer:4 ; ///< + UINT32 StallOverrideWtm:1 ; ///< + UINT32 Reserved_19_16:4 ; ///< + UINT32 Reserved_31_20:12; ///< + } Field; ///< + UINT32 Value; ///< +} GMMx2164_STRUCT; + +// **** GMMx2168 Register Definition **** +// Address +#define GMMx2168_ADDRESS 0x2168 + +// Type +#define GMMx2168_TYPE TYPE_GMM +// Field Data +#define GMMx2168_Enable_OFFSET 0 +#define GMMx2168_Enable_WIDTH 1 +#define GMMx2168_Enable_MASK 0x1 +#define GMMx2168_Prescale_OFFSET 1 +#define GMMx2168_Prescale_WIDTH 2 +#define GMMx2168_Prescale_MASK 0x6 +#define GMMx2168_BlackoutExempt_OFFSET 3 +#define GMMx2168_BlackoutExempt_WIDTH 1 +#define GMMx2168_BlackoutExempt_MASK 0x8 +#define GMMx2168_StallMode_OFFSET 4 +#define GMMx2168_StallMode_WIDTH 2 +#define GMMx2168_StallMode_MASK 0x30 +#define GMMx2168_StallOverride_OFFSET 6 +#define GMMx2168_StallOverride_WIDTH 1 +#define GMMx2168_StallOverride_MASK 0x40 +#define GMMx2168_MaxBurst_OFFSET 7 +#define GMMx2168_MaxBurst_WIDTH 4 +#define GMMx2168_MaxBurst_MASK 0x780 +#define GMMx2168_LazyTimer_OFFSET 11 +#define GMMx2168_LazyTimer_WIDTH 4 +#define GMMx2168_LazyTimer_MASK 0x7800 +#define GMMx2168_StallOverrideWtm_OFFSET 15 +#define GMMx2168_StallOverrideWtm_WIDTH 1 +#define GMMx2168_StallOverrideWtm_MASK 0x8000 +#define GMMx2168_Reserved_19_16_OFFSET 16 +#define GMMx2168_Reserved_19_16_WIDTH 4 +#define GMMx2168_Reserved_19_16_MASK 0xf0000 +#define GMMx2168_Reserved_31_20_OFFSET 20 +#define GMMx2168_Reserved_31_20_WIDTH 12 +#define GMMx2168_Reserved_31_20_MASK 0xfff00000 + +/// GMMx2168 +typedef union { + struct { ///< + UINT32 Enable:1 ; ///< + UINT32 Prescale:2 ; ///< + UINT32 BlackoutExempt:1 ; ///< + UINT32 StallMode:2 ; ///< + UINT32 StallOverride:1 ; ///< + UINT32 MaxBurst:4 ; ///< + UINT32 LazyTimer:4 ; ///< + UINT32 StallOverrideWtm:1 ; ///< + UINT32 Reserved_19_16:4 ; ///< + UINT32 Reserved_31_20:12; ///< + } Field; ///< + UINT32 Value; ///< +} GMMx2168_STRUCT; + +// **** GMMx216C Register Definition **** +// Address +#define GMMx216C_ADDRESS 0x216c + +// Type +#define GMMx216C_TYPE TYPE_GMM +// Field Data +#define GMMx216C_Enable_OFFSET 0 +#define GMMx216C_Enable_WIDTH 1 +#define GMMx216C_Enable_MASK 0x1 +#define GMMx216C_Prescale_OFFSET 1 +#define GMMx216C_Prescale_WIDTH 2 +#define GMMx216C_Prescale_MASK 0x6 +#define GMMx216C_BlackoutExempt_OFFSET 3 +#define GMMx216C_BlackoutExempt_WIDTH 1 +#define GMMx216C_BlackoutExempt_MASK 0x8 +#define GMMx216C_StallMode_OFFSET 4 +#define GMMx216C_StallMode_WIDTH 2 +#define GMMx216C_StallMode_MASK 0x30 +#define GMMx216C_StallOverride_OFFSET 6 +#define GMMx216C_StallOverride_WIDTH 1 +#define GMMx216C_StallOverride_MASK 0x40 +#define GMMx216C_MaxBurst_OFFSET 7 +#define GMMx216C_MaxBurst_WIDTH 4 +#define GMMx216C_MaxBurst_MASK 0x780 +#define GMMx216C_LazyTimer_OFFSET 11 +#define GMMx216C_LazyTimer_WIDTH 4 +#define GMMx216C_LazyTimer_MASK 0x7800 +#define GMMx216C_StallOverrideWtm_OFFSET 15 +#define GMMx216C_StallOverrideWtm_WIDTH 1 +#define GMMx216C_StallOverrideWtm_MASK 0x8000 +#define GMMx216C_Reserved_19_16_OFFSET 16 +#define GMMx216C_Reserved_19_16_WIDTH 4 +#define GMMx216C_Reserved_19_16_MASK 0xf0000 +#define GMMx216C_Reserved_31_20_OFFSET 20 +#define GMMx216C_Reserved_31_20_WIDTH 12 +#define GMMx216C_Reserved_31_20_MASK 0xfff00000 + +/// GMMx216C +typedef union { + struct { ///< + UINT32 Enable:1 ; ///< + UINT32 Prescale:2 ; ///< + UINT32 BlackoutExempt:1 ; ///< + UINT32 StallMode:2 ; ///< + UINT32 StallOverride:1 ; ///< + UINT32 MaxBurst:4 ; ///< + UINT32 LazyTimer:4 ; ///< + UINT32 StallOverrideWtm:1 ; ///< + UINT32 Reserved_19_16:4 ; ///< + UINT32 Reserved_31_20:12; ///< + } Field; ///< + UINT32 Value; ///< +} GMMx216C_STRUCT; + +// **** GMMx2170 Register Definition **** +// Address +#define GMMx2170_ADDRESS 0x2170 + +// Type +#define GMMx2170_TYPE TYPE_GMM +// Field Data +#define GMMx2170_Enable_OFFSET 0 +#define GMMx2170_Enable_WIDTH 1 +#define GMMx2170_Enable_MASK 0x1 +#define GMMx2170_Prescale_OFFSET 1 +#define GMMx2170_Prescale_WIDTH 2 +#define GMMx2170_Prescale_MASK 0x6 +#define GMMx2170_BlackoutExempt_OFFSET 3 +#define GMMx2170_BlackoutExempt_WIDTH 1 +#define GMMx2170_BlackoutExempt_MASK 0x8 +#define GMMx2170_StallMode_OFFSET 4 +#define GMMx2170_StallMode_WIDTH 2 +#define GMMx2170_StallMode_MASK 0x30 +#define GMMx2170_StallOverride_OFFSET 6 +#define GMMx2170_StallOverride_WIDTH 1 +#define GMMx2170_StallOverride_MASK 0x40 +#define GMMx2170_MaxBurst_OFFSET 7 +#define GMMx2170_MaxBurst_WIDTH 4 +#define GMMx2170_MaxBurst_MASK 0x780 +#define GMMx2170_LazyTimer_OFFSET 11 +#define GMMx2170_LazyTimer_WIDTH 4 +#define GMMx2170_LazyTimer_MASK 0x7800 +#define GMMx2170_StallOverrideWtm_OFFSET 15 +#define GMMx2170_StallOverrideWtm_WIDTH 1 +#define GMMx2170_StallOverrideWtm_MASK 0x8000 +#define GMMx2170_Reserved_19_16_OFFSET 16 +#define GMMx2170_Reserved_19_16_WIDTH 4 +#define GMMx2170_Reserved_19_16_MASK 0xf0000 +#define GMMx2170_Reserved_31_20_OFFSET 20 +#define GMMx2170_Reserved_31_20_WIDTH 12 +#define GMMx2170_Reserved_31_20_MASK 0xfff00000 + +/// GMMx2170 +typedef union { + struct { ///< + UINT32 Enable:1 ; ///< + UINT32 Prescale:2 ; ///< + UINT32 BlackoutExempt:1 ; ///< + UINT32 StallMode:2 ; ///< + UINT32 StallOverride:1 ; ///< + UINT32 MaxBurst:4 ; ///< + UINT32 LazyTimer:4 ; ///< + UINT32 StallOverrideWtm:1 ; ///< + UINT32 Reserved_19_16:4 ; ///< + UINT32 Reserved_31_20:12; ///< + } Field; ///< + UINT32 Value; ///< +} GMMx2170_STRUCT; + +// **** GMMx2174 Register Definition **** +// Address +#define GMMx2174_ADDRESS 0x2174 + +// Type +#define GMMx2174_TYPE TYPE_GMM +// Field Data +#define GMMx2174_Enable_OFFSET 0 +#define GMMx2174_Enable_WIDTH 1 +#define GMMx2174_Enable_MASK 0x1 +#define GMMx2174_Prescale_OFFSET 1 +#define GMMx2174_Prescale_WIDTH 2 +#define GMMx2174_Prescale_MASK 0x6 +#define GMMx2174_BlackoutExempt_OFFSET 3 +#define GMMx2174_BlackoutExempt_WIDTH 1 +#define GMMx2174_BlackoutExempt_MASK 0x8 +#define GMMx2174_StallMode_OFFSET 4 +#define GMMx2174_StallMode_WIDTH 2 +#define GMMx2174_StallMode_MASK 0x30 +#define GMMx2174_StallOverride_OFFSET 6 +#define GMMx2174_StallOverride_WIDTH 1 +#define GMMx2174_StallOverride_MASK 0x40 +#define GMMx2174_MaxBurst_OFFSET 7 +#define GMMx2174_MaxBurst_WIDTH 4 +#define GMMx2174_MaxBurst_MASK 0x780 +#define GMMx2174_LazyTimer_OFFSET 11 +#define GMMx2174_LazyTimer_WIDTH 4 +#define GMMx2174_LazyTimer_MASK 0x7800 +#define GMMx2174_StallOverrideWtm_OFFSET 15 +#define GMMx2174_StallOverrideWtm_WIDTH 1 +#define GMMx2174_StallOverrideWtm_MASK 0x8000 +#define GMMx2174_Reserved_19_16_OFFSET 16 +#define GMMx2174_Reserved_19_16_WIDTH 4 +#define GMMx2174_Reserved_19_16_MASK 0xf0000 +#define GMMx2174_Reserved_31_20_OFFSET 20 +#define GMMx2174_Reserved_31_20_WIDTH 12 +#define GMMx2174_Reserved_31_20_MASK 0xfff00000 + +/// GMMx2174 +typedef union { + struct { ///< + UINT32 Enable:1 ; ///< + UINT32 Prescale:2 ; ///< + UINT32 BlackoutExempt:1 ; ///< + UINT32 StallMode:2 ; ///< + UINT32 StallOverride:1 ; ///< + UINT32 MaxBurst:4 ; ///< + UINT32 LazyTimer:4 ; ///< + UINT32 StallOverrideWtm:1 ; ///< + UINT32 Reserved_19_16:4 ; ///< + UINT32 Reserved_31_20:12; ///< + } Field; ///< + UINT32 Value; ///< +} GMMx2174_STRUCT; + +// **** GMMx2178 Register Definition **** +// Address +#define GMMx2178_ADDRESS 0x2178 + +// Type +#define GMMx2178_TYPE TYPE_GMM +// Field Data +#define GMMx2178_Enable_OFFSET 0 +#define GMMx2178_Enable_WIDTH 1 +#define GMMx2178_Enable_MASK 0x1 +#define GMMx2178_Prescale_OFFSET 1 +#define GMMx2178_Prescale_WIDTH 2 +#define GMMx2178_Prescale_MASK 0x6 +#define GMMx2178_BlackoutExempt_OFFSET 3 +#define GMMx2178_BlackoutExempt_WIDTH 1 +#define GMMx2178_BlackoutExempt_MASK 0x8 +#define GMMx2178_StallMode_OFFSET 4 +#define GMMx2178_StallMode_WIDTH 2 +#define GMMx2178_StallMode_MASK 0x30 +#define GMMx2178_StallOverride_OFFSET 6 +#define GMMx2178_StallOverride_WIDTH 1 +#define GMMx2178_StallOverride_MASK 0x40 +#define GMMx2178_MaxBurst_OFFSET 7 +#define GMMx2178_MaxBurst_WIDTH 4 +#define GMMx2178_MaxBurst_MASK 0x780 +#define GMMx2178_LazyTimer_OFFSET 11 +#define GMMx2178_LazyTimer_WIDTH 4 +#define GMMx2178_LazyTimer_MASK 0x7800 +#define GMMx2178_StallOverrideWtm_OFFSET 15 +#define GMMx2178_StallOverrideWtm_WIDTH 1 +#define GMMx2178_StallOverrideWtm_MASK 0x8000 +#define GMMx2178_Reserved_19_16_OFFSET 16 +#define GMMx2178_Reserved_19_16_WIDTH 4 +#define GMMx2178_Reserved_19_16_MASK 0xf0000 +#define GMMx2178_Reserved_31_20_OFFSET 20 +#define GMMx2178_Reserved_31_20_WIDTH 12 +#define GMMx2178_Reserved_31_20_MASK 0xfff00000 + +/// GMMx2178 +typedef union { + struct { ///< + UINT32 Enable:1 ; ///< + UINT32 Prescale:2 ; ///< + UINT32 BlackoutExempt:1 ; ///< + UINT32 StallMode:2 ; ///< + UINT32 StallOverride:1 ; ///< + UINT32 MaxBurst:4 ; ///< + UINT32 LazyTimer:4 ; ///< + UINT32 StallOverrideWtm:1 ; ///< + UINT32 Reserved_19_16:4 ; ///< + UINT32 Reserved_31_20:12; ///< + } Field; ///< + UINT32 Value; ///< +} GMMx2178_STRUCT; + +// **** GMMx217C Register Definition **** +// Address +#define GMMx217C_ADDRESS 0x217c + +// Type +#define GMMx217C_TYPE TYPE_GMM +// Field Data +#define GMMx217C_Enable_OFFSET 0 +#define GMMx217C_Enable_WIDTH 1 +#define GMMx217C_Enable_MASK 0x1 +#define GMMx217C_Prescale_OFFSET 1 +#define GMMx217C_Prescale_WIDTH 2 +#define GMMx217C_Prescale_MASK 0x6 +#define GMMx217C_BlackoutExempt_OFFSET 3 +#define GMMx217C_BlackoutExempt_WIDTH 1 +#define GMMx217C_BlackoutExempt_MASK 0x8 +#define GMMx217C_StallMode_OFFSET 4 +#define GMMx217C_StallMode_WIDTH 2 +#define GMMx217C_StallMode_MASK 0x30 +#define GMMx217C_StallOverride_OFFSET 6 +#define GMMx217C_StallOverride_WIDTH 1 +#define GMMx217C_StallOverride_MASK 0x40 +#define GMMx217C_MaxBurst_OFFSET 7 +#define GMMx217C_MaxBurst_WIDTH 4 +#define GMMx217C_MaxBurst_MASK 0x780 +#define GMMx217C_LazyTimer_OFFSET 11 +#define GMMx217C_LazyTimer_WIDTH 4 +#define GMMx217C_LazyTimer_MASK 0x7800 +#define GMMx217C_StallOverrideWtm_OFFSET 15 +#define GMMx217C_StallOverrideWtm_WIDTH 1 +#define GMMx217C_StallOverrideWtm_MASK 0x8000 +#define GMMx217C_Reserved_19_16_OFFSET 16 +#define GMMx217C_Reserved_19_16_WIDTH 4 +#define GMMx217C_Reserved_19_16_MASK 0xf0000 +#define GMMx217C_Reserved_31_20_OFFSET 20 +#define GMMx217C_Reserved_31_20_WIDTH 12 +#define GMMx217C_Reserved_31_20_MASK 0xfff00000 + +/// GMMx217C +typedef union { + struct { ///< + UINT32 Enable:1 ; ///< + UINT32 Prescale:2 ; ///< + UINT32 BlackoutExempt:1 ; ///< + UINT32 StallMode:2 ; ///< + UINT32 StallOverride:1 ; ///< + UINT32 MaxBurst:4 ; ///< + UINT32 LazyTimer:4 ; ///< + UINT32 StallOverrideWtm:1 ; ///< + UINT32 Reserved_19_16:4 ; ///< + UINT32 Reserved_31_20:12; ///< + } Field; ///< + UINT32 Value; ///< +} GMMx217C_STRUCT; + +// **** GMMx2180 Register Definition **** +// Address +#define GMMx2180_ADDRESS 0x2180 + +// Type +#define GMMx2180_TYPE TYPE_GMM +// Field Data +#define GMMx2180_Enable_OFFSET 0 +#define GMMx2180_Enable_WIDTH 1 +#define GMMx2180_Enable_MASK 0x1 +#define GMMx2180_Prescale_OFFSET 1 +#define GMMx2180_Prescale_WIDTH 2 +#define GMMx2180_Prescale_MASK 0x6 +#define GMMx2180_BlackoutExempt_OFFSET 3 +#define GMMx2180_BlackoutExempt_WIDTH 1 +#define GMMx2180_BlackoutExempt_MASK 0x8 +#define GMMx2180_StallMode_OFFSET 4 +#define GMMx2180_StallMode_WIDTH 2 +#define GMMx2180_StallMode_MASK 0x30 +#define GMMx2180_StallOverride_OFFSET 6 +#define GMMx2180_StallOverride_WIDTH 1 +#define GMMx2180_StallOverride_MASK 0x40 +#define GMMx2180_MaxBurst_OFFSET 7 +#define GMMx2180_MaxBurst_WIDTH 4 +#define GMMx2180_MaxBurst_MASK 0x780 +#define GMMx2180_LazyTimer_OFFSET 11 +#define GMMx2180_LazyTimer_WIDTH 4 +#define GMMx2180_LazyTimer_MASK 0x7800 +#define GMMx2180_StallOverrideWtm_OFFSET 15 +#define GMMx2180_StallOverrideWtm_WIDTH 1 +#define GMMx2180_StallOverrideWtm_MASK 0x8000 +#define GMMx2180_Reserved_19_16_OFFSET 16 +#define GMMx2180_Reserved_19_16_WIDTH 4 +#define GMMx2180_Reserved_19_16_MASK 0xf0000 +#define GMMx2180_Reserved_31_20_OFFSET 20 +#define GMMx2180_Reserved_31_20_WIDTH 12 +#define GMMx2180_Reserved_31_20_MASK 0xfff00000 + +/// GMMx2180 +typedef union { + struct { ///< + UINT32 Enable:1 ; ///< + UINT32 Prescale:2 ; ///< + UINT32 BlackoutExempt:1 ; ///< + UINT32 StallMode:2 ; ///< + UINT32 StallOverride:1 ; ///< + UINT32 MaxBurst:4 ; ///< + UINT32 LazyTimer:4 ; ///< + UINT32 StallOverrideWtm:1 ; ///< + UINT32 Reserved_19_16:4 ; ///< + UINT32 Reserved_31_20:12; ///< + } Field; ///< + UINT32 Value; ///< +} GMMx2180_STRUCT; + +// **** GMMx2184 Register Definition **** +// Address +#define GMMx2184_ADDRESS 0x2184 + +// Type +#define GMMx2184_TYPE TYPE_GMM +// Field Data +#define GMMx2184_Enable_OFFSET 0 +#define GMMx2184_Enable_WIDTH 1 +#define GMMx2184_Enable_MASK 0x1 +#define GMMx2184_Prescale_OFFSET 1 +#define GMMx2184_Prescale_WIDTH 2 +#define GMMx2184_Prescale_MASK 0x6 +#define GMMx2184_BlackoutExempt_OFFSET 3 +#define GMMx2184_BlackoutExempt_WIDTH 1 +#define GMMx2184_BlackoutExempt_MASK 0x8 +#define GMMx2184_StallMode_OFFSET 4 +#define GMMx2184_StallMode_WIDTH 2 +#define GMMx2184_StallMode_MASK 0x30 +#define GMMx2184_StallOverride_OFFSET 6 +#define GMMx2184_StallOverride_WIDTH 1 +#define GMMx2184_StallOverride_MASK 0x40 +#define GMMx2184_MaxBurst_OFFSET 7 +#define GMMx2184_MaxBurst_WIDTH 4 +#define GMMx2184_MaxBurst_MASK 0x780 +#define GMMx2184_LazyTimer_OFFSET 11 +#define GMMx2184_LazyTimer_WIDTH 4 +#define GMMx2184_LazyTimer_MASK 0x7800 +#define GMMx2184_StallOverrideWtm_OFFSET 15 +#define GMMx2184_StallOverrideWtm_WIDTH 1 +#define GMMx2184_StallOverrideWtm_MASK 0x8000 +#define GMMx2184_Reserved_19_16_OFFSET 16 +#define GMMx2184_Reserved_19_16_WIDTH 4 +#define GMMx2184_Reserved_19_16_MASK 0xf0000 +#define GMMx2184_Reserved_31_20_OFFSET 20 +#define GMMx2184_Reserved_31_20_WIDTH 12 +#define GMMx2184_Reserved_31_20_MASK 0xfff00000 + +/// GMMx2184 +typedef union { + struct { ///< + UINT32 Enable:1 ; ///< + UINT32 Prescale:2 ; ///< + UINT32 BlackoutExempt:1 ; ///< + UINT32 StallMode:2 ; ///< + UINT32 StallOverride:1 ; ///< + UINT32 MaxBurst:4 ; ///< + UINT32 LazyTimer:4 ; ///< + UINT32 StallOverrideWtm:1 ; ///< + UINT32 Reserved_19_16:4 ; ///< + UINT32 Reserved_31_20:12; ///< + } Field; ///< + UINT32 Value; ///< +} GMMx2184_STRUCT; + +// **** GMMx2188 Register Definition **** +// Address +#define GMMx2188_ADDRESS 0x2188 + +// Type +#define GMMx2188_TYPE TYPE_GMM +// Field Data +#define GMMx2188_Enable_OFFSET 0 +#define GMMx2188_Enable_WIDTH 1 +#define GMMx2188_Enable_MASK 0x1 +#define GMMx2188_Prescale_OFFSET 1 +#define GMMx2188_Prescale_WIDTH 2 +#define GMMx2188_Prescale_MASK 0x6 +#define GMMx2188_BlackoutExempt_OFFSET 3 +#define GMMx2188_BlackoutExempt_WIDTH 1 +#define GMMx2188_BlackoutExempt_MASK 0x8 +#define GMMx2188_StallMode_OFFSET 4 +#define GMMx2188_StallMode_WIDTH 2 +#define GMMx2188_StallMode_MASK 0x30 +#define GMMx2188_StallOverride_OFFSET 6 +#define GMMx2188_StallOverride_WIDTH 1 +#define GMMx2188_StallOverride_MASK 0x40 +#define GMMx2188_MaxBurst_OFFSET 7 +#define GMMx2188_MaxBurst_WIDTH 4 +#define GMMx2188_MaxBurst_MASK 0x780 +#define GMMx2188_LazyTimer_OFFSET 11 +#define GMMx2188_LazyTimer_WIDTH 4 +#define GMMx2188_LazyTimer_MASK 0x7800 +#define GMMx2188_StallOverrideWtm_OFFSET 15 +#define GMMx2188_StallOverrideWtm_WIDTH 1 +#define GMMx2188_StallOverrideWtm_MASK 0x8000 +#define GMMx2188_ReqLimit_OFFSET 16 +#define GMMx2188_ReqLimit_WIDTH 4 +#define GMMx2188_ReqLimit_MASK 0xf0000 +#define GMMx2188_Reserved_31_20_OFFSET 20 +#define GMMx2188_Reserved_31_20_WIDTH 12 +#define GMMx2188_Reserved_31_20_MASK 0xfff00000 + +/// GMMx2188 +typedef union { + struct { ///< + UINT32 Enable:1 ; ///< + UINT32 Prescale:2 ; ///< + UINT32 BlackoutExempt:1 ; ///< + UINT32 StallMode:2 ; ///< + UINT32 StallOverride:1 ; ///< + UINT32 MaxBurst:4 ; ///< + UINT32 LazyTimer:4 ; ///< + UINT32 StallOverrideWtm:1 ; ///< + UINT32 ReqLimit:4 ; ///< + UINT32 Reserved_31_20:12; ///< + } Field; ///< + UINT32 Value; ///< +} GMMx2188_STRUCT; + +// **** GMMx218C Register Definition **** +// Address +#define GMMx218C_ADDRESS 0x218c + +// Type +#define GMMx218C_TYPE TYPE_GMM +// Field Data +#define GMMx218C_Enable_OFFSET 0 +#define GMMx218C_Enable_WIDTH 1 +#define GMMx218C_Enable_MASK 0x1 +#define GMMx218C_Prescale_OFFSET 1 +#define GMMx218C_Prescale_WIDTH 2 +#define GMMx218C_Prescale_MASK 0x6 +#define GMMx218C_BlackoutExempt_OFFSET 3 +#define GMMx218C_BlackoutExempt_WIDTH 1 +#define GMMx218C_BlackoutExempt_MASK 0x8 +#define GMMx218C_StallMode_OFFSET 4 +#define GMMx218C_StallMode_WIDTH 2 +#define GMMx218C_StallMode_MASK 0x30 +#define GMMx218C_StallOverride_OFFSET 6 +#define GMMx218C_StallOverride_WIDTH 1 +#define GMMx218C_StallOverride_MASK 0x40 +#define GMMx218C_MaxBurst_OFFSET 7 +#define GMMx218C_MaxBurst_WIDTH 4 +#define GMMx218C_MaxBurst_MASK 0x780 +#define GMMx218C_LazyTimer_OFFSET 11 +#define GMMx218C_LazyTimer_WIDTH 4 +#define GMMx218C_LazyTimer_MASK 0x7800 +#define GMMx218C_StallOverrideWtm_OFFSET 15 +#define GMMx218C_StallOverrideWtm_WIDTH 1 +#define GMMx218C_StallOverrideWtm_MASK 0x8000 +#define GMMx218C_Reserved_19_16_OFFSET 16 +#define GMMx218C_Reserved_19_16_WIDTH 4 +#define GMMx218C_Reserved_19_16_MASK 0xf0000 +#define GMMx218C_Reserved_31_20_OFFSET 20 +#define GMMx218C_Reserved_31_20_WIDTH 12 +#define GMMx218C_Reserved_31_20_MASK 0xfff00000 + +/// GMMx218C +typedef union { + struct { ///< + UINT32 Enable:1 ; ///< + UINT32 Prescale:2 ; ///< + UINT32 BlackoutExempt:1 ; ///< + UINT32 StallMode:2 ; ///< + UINT32 StallOverride:1 ; ///< + UINT32 MaxBurst:4 ; ///< + UINT32 LazyTimer:4 ; ///< + UINT32 StallOverrideWtm:1 ; ///< + UINT32 Reserved_19_16:4 ; ///< + UINT32 Reserved_31_20:12; ///< + } Field; ///< + UINT32 Value; ///< +} GMMx218C_STRUCT; + +// **** GMMx2190 Register Definition **** +// Address +#define GMMx2190_ADDRESS 0x2190 + +// Type +#define GMMx2190_TYPE TYPE_GMM +// Field Data +#define GMMx2190_Enable_OFFSET 0 +#define GMMx2190_Enable_WIDTH 1 +#define GMMx2190_Enable_MASK 0x1 +#define GMMx2190_Reserved_1_1_OFFSET 1 +#define GMMx2190_Reserved_1_1_WIDTH 1 +#define GMMx2190_Reserved_1_1_MASK 0x2 +#define GMMx2190_StallMode_OFFSET 2 +#define GMMx2190_StallMode_WIDTH 1 +#define GMMx2190_StallMode_MASK 0x4 +#define GMMx2190_MaxBurst_OFFSET 3 +#define GMMx2190_MaxBurst_WIDTH 4 +#define GMMx2190_MaxBurst_MASK 0x78 +#define GMMx2190_AskCredits_OFFSET 7 +#define GMMx2190_AskCredits_WIDTH 6 +#define GMMx2190_AskCredits_MASK 0x1f80 +#define GMMx2190_LazyTimer_OFFSET 13 +#define GMMx2190_LazyTimer_WIDTH 4 +#define GMMx2190_LazyTimer_MASK 0x1e000 +#define GMMx2190_StallThreshold_OFFSET 17 +#define GMMx2190_StallThreshold_WIDTH 6 +#define GMMx2190_StallThreshold_MASK 0x7e0000 +#define GMMx2190_Reserved_31_23_OFFSET 23 +#define GMMx2190_Reserved_31_23_WIDTH 9 +#define GMMx2190_Reserved_31_23_MASK 0xff800000 + +/// GMMx2190 +typedef union { + struct { ///< + UINT32 Enable:1 ; ///< + UINT32 Reserved_1_1:1 ; ///< + UINT32 StallMode:1 ; ///< + UINT32 MaxBurst:4 ; ///< + UINT32 AskCredits:6 ; ///< + UINT32 LazyTimer:4 ; ///< + UINT32 StallThreshold:6 ; ///< + UINT32 Reserved_31_23:9 ; ///< + } Field; ///< + UINT32 Value; ///< +} GMMx2190_STRUCT; + +// **** GMMx2194 Register Definition **** +// Address +#define GMMx2194_ADDRESS 0x2194 + +// Type +#define GMMx2194_TYPE TYPE_GMM +// Field Data +#define GMMx2194_Enable_OFFSET 0 +#define GMMx2194_Enable_WIDTH 1 +#define GMMx2194_Enable_MASK 0x1 +#define GMMx2194_Reserved_1_1_OFFSET 1 +#define GMMx2194_Reserved_1_1_WIDTH 1 +#define GMMx2194_Reserved_1_1_MASK 0x2 +#define GMMx2194_StallMode_OFFSET 2 +#define GMMx2194_StallMode_WIDTH 1 +#define GMMx2194_StallMode_MASK 0x4 +#define GMMx2194_MaxBurst_OFFSET 3 +#define GMMx2194_MaxBurst_WIDTH 4 +#define GMMx2194_MaxBurst_MASK 0x78 +#define GMMx2194_AskCredits_OFFSET 7 +#define GMMx2194_AskCredits_WIDTH 6 +#define GMMx2194_AskCredits_MASK 0x1f80 +#define GMMx2194_LazyTimer_OFFSET 13 +#define GMMx2194_LazyTimer_WIDTH 4 +#define GMMx2194_LazyTimer_MASK 0x1e000 +#define GMMx2194_StallThreshold_OFFSET 17 +#define GMMx2194_StallThreshold_WIDTH 6 +#define GMMx2194_StallThreshold_MASK 0x7e0000 +#define GMMx2194_Reserved_31_23_OFFSET 23 +#define GMMx2194_Reserved_31_23_WIDTH 9 +#define GMMx2194_Reserved_31_23_MASK 0xff800000 + +/// GMMx2194 +typedef union { + struct { ///< + UINT32 Enable:1 ; ///< + UINT32 Reserved_1_1:1 ; ///< + UINT32 StallMode:1 ; ///< + UINT32 MaxBurst:4 ; ///< + UINT32 AskCredits:6 ; ///< + UINT32 LazyTimer:4 ; ///< + UINT32 StallThreshold:6 ; ///< + UINT32 Reserved_31_23:9 ; ///< + } Field; ///< + UINT32 Value; ///< +} GMMx2194_STRUCT; + +// **** GMMx2198 Register Definition **** +// Address +#define GMMx2198_ADDRESS 0x2198 + +// Type +#define GMMx2198_TYPE TYPE_GMM +// Field Data +#define GMMx2198_Enable_OFFSET 0 +#define GMMx2198_Enable_WIDTH 1 +#define GMMx2198_Enable_MASK 0x1 +#define GMMx2198_Reserved_1_1_OFFSET 1 +#define GMMx2198_Reserved_1_1_WIDTH 1 +#define GMMx2198_Reserved_1_1_MASK 0x2 +#define GMMx2198_StallMode_OFFSET 2 +#define GMMx2198_StallMode_WIDTH 1 +#define GMMx2198_StallMode_MASK 0x4 +#define GMMx2198_MaxBurst_OFFSET 3 +#define GMMx2198_MaxBurst_WIDTH 4 +#define GMMx2198_MaxBurst_MASK 0x78 +#define GMMx2198_AskCredits_OFFSET 7 +#define GMMx2198_AskCredits_WIDTH 6 +#define GMMx2198_AskCredits_MASK 0x1f80 +#define GMMx2198_LazyTimer_OFFSET 13 +#define GMMx2198_LazyTimer_WIDTH 4 +#define GMMx2198_LazyTimer_MASK 0x1e000 +#define GMMx2198_StallThreshold_OFFSET 17 +#define GMMx2198_StallThreshold_WIDTH 6 +#define GMMx2198_StallThreshold_MASK 0x7e0000 +#define GMMx2198_Reserved_31_23_OFFSET 23 +#define GMMx2198_Reserved_31_23_WIDTH 9 +#define GMMx2198_Reserved_31_23_MASK 0xff800000 + +/// GMMx2198 +typedef union { + struct { ///< + UINT32 Enable:1 ; ///< + UINT32 Reserved_1_1:1 ; ///< + UINT32 StallMode:1 ; ///< + UINT32 MaxBurst:4 ; ///< + UINT32 AskCredits:6 ; ///< + UINT32 LazyTimer:4 ; ///< + UINT32 StallThreshold:6 ; ///< + UINT32 Reserved_31_23:9 ; ///< + } Field; ///< + UINT32 Value; ///< +} GMMx2198_STRUCT; + +// **** GMMx219C Register Definition **** +// Address +#define GMMx219C_ADDRESS 0x219c + +// Type +#define GMMx219C_TYPE TYPE_GMM +// Field Data +#define GMMx219C_Enable_OFFSET 0 +#define GMMx219C_Enable_WIDTH 1 +#define GMMx219C_Enable_MASK 0x1 +#define GMMx219C_Reserved_1_1_OFFSET 1 +#define GMMx219C_Reserved_1_1_WIDTH 1 +#define GMMx219C_Reserved_1_1_MASK 0x2 +#define GMMx219C_StallMode_OFFSET 2 +#define GMMx219C_StallMode_WIDTH 1 +#define GMMx219C_StallMode_MASK 0x4 +#define GMMx219C_MaxBurst_OFFSET 3 +#define GMMx219C_MaxBurst_WIDTH 4 +#define GMMx219C_MaxBurst_MASK 0x78 +#define GMMx219C_AskCredits_OFFSET 7 +#define GMMx219C_AskCredits_WIDTH 6 +#define GMMx219C_AskCredits_MASK 0x1f80 +#define GMMx219C_LazyTimer_OFFSET 13 +#define GMMx219C_LazyTimer_WIDTH 4 +#define GMMx219C_LazyTimer_MASK 0x1e000 +#define GMMx219C_StallThreshold_OFFSET 17 +#define GMMx219C_StallThreshold_WIDTH 6 +#define GMMx219C_StallThreshold_MASK 0x7e0000 +#define GMMx219C_Reserved_31_23_OFFSET 23 +#define GMMx219C_Reserved_31_23_WIDTH 9 +#define GMMx219C_Reserved_31_23_MASK 0xff800000 + +/// GMMx219C +typedef union { + struct { ///< + UINT32 Enable:1 ; ///< + UINT32 Reserved_1_1:1 ; ///< + UINT32 StallMode:1 ; ///< + UINT32 MaxBurst:4 ; ///< + UINT32 AskCredits:6 ; ///< + UINT32 LazyTimer:4 ; ///< + UINT32 StallThreshold:6 ; ///< + UINT32 Reserved_31_23:9 ; ///< + } Field; ///< + UINT32 Value; ///< +} GMMx219C_STRUCT; + // **** GMMx21A4 Register Definition **** // Address #define GMMx21A4_ADDRESS 0x21a4 @@ -9474,6 +12597,29 @@ typedef union { UINT32 Value; ///< } GMMx2898_STRUCT; +// **** GMMx28C8 Register Definition **** +// Address +#define GMMx28C8_ADDRESS 0x28c8 + +// Type +#define GMMx28C8_TYPE TYPE_GMM +// Field Data +#define GMMx28C8_Delay_OFFSET 0 +#define GMMx28C8_Delay_WIDTH 4 +#define GMMx28C8_Delay_MASK 0xf +#define GMMx28C8_Reserved_31_4_OFFSET 4 +#define GMMx28C8_Reserved_31_4_WIDTH 28 +#define GMMx28C8_Reserved_31_4_MASK 0xfffffff0 + +/// GMMx28C8 +typedef union { + struct { ///< + UINT32 Delay:4 ; ///< + UINT32 Reserved_31_4:28; ///< + } Field; ///< + UINT32 Value; ///< +} GMMx28C8_STRUCT; + // **** GMMx28D8 Register Definition **** // Address #define GMMx28D8_ADDRESS 0x28d8 @@ -9578,6 +12724,34 @@ typedef union { UINT32 Value; ///< } GMMx2B90_STRUCT; +// **** GMMx2B94 Register Definition **** +// Address +#define GMMx2B94_ADDRESS 0x2b94 + +// Type +#define GMMx2B94_TYPE TYPE_GMM +// Field Data +#define GMMx2B94_RengExecuteOnPwrUp_OFFSET 0 +#define GMMx2B94_RengExecuteOnPwrUp_WIDTH 1 +#define GMMx2B94_RengExecuteOnPwrUp_MASK 0x1 +#define GMMx2B94_Reserved_31_1_OFFSET 1 +#define GMMx2B94_Reserved_31_1_WIDTH 31 +#define GMMx2B94_Reserved_31_1_MASK 0xfffffffe + +/// GMMx2B94 +typedef union { + struct { ///< + UINT32 RengExecuteOnPwrUp:1 ; ///< + UINT32 Reserved_31_1:31; ///< + } Field; ///< + UINT32 Value; ///< +} GMMx2B94_STRUCT; + +// **** GMMx2B98 Register Definition **** +// Address +#define GMMx2B98_ADDRESS 0x2b98 +// Type +#define GMMx2B98_TYPE TYPE_GMM // **** GMMx2C04 Register Definition **** // Address #define GMMx2C04_ADDRESS 0x2c04 @@ -9647,60 +12821,6 @@ typedef union { UINT32 Value; ///< } GMMx5490_STRUCT; -// **** SMUx03 Register Definition **** -// Address -#define SMUx03_ADDRESS 0x3 - -// Type -#define SMUx03_TYPE TYPE_SMU -// Field Data -#define SMUx03_IntReq_OFFSET 0 -#define SMUx03_IntReq_WIDTH 1 -#define SMUx03_IntReq_MASK 0x1 -#define SMUx03_IntAck_OFFSET 1 -#define SMUx03_IntAck_WIDTH 1 -#define SMUx03_IntAck_MASK 0x2 -#define SMUx03_IntDone_OFFSET 2 -#define SMUx03_IntDone_WIDTH 1 -#define SMUx03_IntDone_MASK 0x4 -#define SMUx03_ServiceIndex_OFFSET 3 -#define SMUx03_ServiceIndex_WIDTH 8 -#define SMUx03_ServiceIndex_MASK 0x7f8 -#define SMUx03_Reserved_31_11_OFFSET 11 -#define SMUx03_Reserved_31_11_WIDTH 21 -#define SMUx03_Reserved_31_11_MASK 0xfffff800 - -/// SMUx03 -typedef union { - struct { ///< - UINT32 IntReq:1 ; ///< - UINT32 IntAck:1 ; ///< - UINT32 IntDone:1 ; ///< - UINT32 ServiceIndex:8 ; ///< - UINT32 Reserved_31_11:21; ///< - } Field; ///< - UINT32 Value; ///< -} SMUx03_STRUCT; - -// **** SMUx05 Register Definition **** -// Address -#define SMUx05_ADDRESS 0x5 - -// Type -#define SMUx05_TYPE TYPE_SMU -// Field Data -#define SMUx05_McuRam_OFFSET 0 -#define SMUx05_McuRam_WIDTH 32 -#define SMUx05_McuRam_MASK 0xffffffff - -/// SMUx05 -typedef union { - struct { ///< - UINT32 McuRam:32; ///< - } Field; ///< - UINT32 Value; ///< -} SMUx05_STRUCT; - // **** SMUx0B Register Definition **** // Address #define SMUx0B_ADDRESS 0xb @@ -9748,69 +12868,6 @@ typedef union { } MSRC001_001A_STRUCT; -// **** FCRxFF30_0AE6(GMMx2B98) Register Definition **** -// Address -#define FCRxFF30_0AE6_ADDRESS 0xff300AE6 - -// Field Data -#define FCRxFF30_0AE6_RengExecuteNonsecureStartPtr_OFFSET 0 -#define FCRxFF30_0AE6_RengExecuteNonsecureStartPtr_WIDTH 10 -#define FCRxFF30_0AE6_RengExecuteNowMode_OFFSET 10 -#define FCRxFF30_0AE6_RengExecuteNowMode_WIDTH 1 -#define FCRxFF30_0AE6_RengExecuteOnRegUpdate_OFFSET 11 -#define FCRxFF30_0AE6_RengExecuteOnRegUpdate_WIDTH 1 -#define FCRxFF30_0AE6_RengSrbmCreditsMcd_OFFSET 12 -#define FCRxFF30_0AE6_RengSrbmCreditsMcd_WIDTH 4 -#define FCRxFF30_0AE6_StctrlStutterEn_OFFSET 16 -#define FCRxFF30_0AE6_StctrlStutterEn_WIDTH 1 -#define FCRxFF30_0AE6_StctrlGmcIdleThreshold_OFFSET 17 -#define FCRxFF30_0AE6_StctrlGmcIdleThreshold_WIDTH 2 -#define FCRxFF30_0AE6_StctrlSrbmIdleThreshold_OFFSET 19 -#define FCRxFF30_0AE6_StctrlSrbmIdleThreshold_WIDTH 2 -#define FCRxFF30_0AE6_StctrlIgnorePreSr_OFFSET 21 -#define FCRxFF30_0AE6_StctrlIgnorePreSr_WIDTH 1 -#define FCRxFF30_0AE6_StctrlIgnoreAllowStop_OFFSET 22 -#define FCRxFF30_0AE6_StctrlIgnoreAllowStop_WIDTH 1 -#define FCRxFF30_0AE6_StctrlIgnoreDramOffline_OFFSET 23 -#define FCRxFF30_0AE6_StctrlIgnoreDramOffline_WIDTH 1 -#define FCRxFF30_0AE6_StctrlIgnoreProtectionFault_OFFSET 24 -#define FCRxFF30_0AE6_StctrlIgnoreProtectionFault_WIDTH 1 -#define FCRxFF30_0AE6_StctrlDisableAllowSr_OFFSET 25 -#define FCRxFF30_0AE6_StctrlDisableAllowSr_WIDTH 1 -#define FCRxFF30_0AE6_StctrlDisableGmcOffline_OFFSET 26 -#define FCRxFF30_0AE6_StctrlDisableGmcOffline_WIDTH 1 -#define FCRxFF30_0AE6_CriticalRegsLock_OFFSET 27 -#define FCRxFF30_0AE6_CriticalRegsLock_WIDTH 1 -#define FCRxFF30_0AE6_SmuExecuteOnRegUpdate_OFFSET 28 -#define FCRxFF30_0AE6_SmuExecuteOnRegUpdate_WIDTH 1 -#define FCRxFF30_0AE6_AllowDeepSleepMode_OFFSET 29 -#define FCRxFF30_0AE6_AllowDeepSleepMode_WIDTH 2 -#define FCRxFF30_0AE6_Reserved_31_31_OFFSET 31 -#define FCRxFF30_0AE6_Reserved_31_31_WIDTH 1 - -/// FCRxFF30_0AE6 -typedef union { - struct { ///< - UINT32 RengExecuteNonsecureStartPtr:10; ///< - UINT32 RengExecuteNowMode:1 ; ///< - UINT32 RengExecuteOnRegUpdate:1 ; ///< - UINT32 RengSrbmCreditsMcd:4 ; ///< - UINT32 StctrlStutterEn:1 ; ///< - UINT32 StctrlGmcIdleThreshold:2 ; ///< - UINT32 StctrlSrbmIdleThreshold:2 ; ///< - UINT32 StctrlIgnorePreSr:1 ; ///< - UINT32 StctrlIgnoreAllowStop:1 ; ///< - UINT32 StctrlIgnoreDramOffline:1 ; ///< - UINT32 StctrlIgnoreProtectionFault:1 ; ///< - UINT32 StctrlDisableAllowSr:1 ; ///< - UINT32 StctrlDisableGmcOffline:1 ; ///< - UINT32 CriticalRegsLock:1 ; ///< - UINT32 SmuExecuteOnRegUpdate:1 ; ///< - UINT32 AllowDeepSleepMode:2 ; ///< - UINT32 Reserved_31_31:1 ; ///< - } Field; - UINT32 Value; -} FCRxFF30_0AE6_STRUCT; // **** FCRxFF30_0134(GMMx4D0) Register Definition **** // Address @@ -9853,6 +12910,292 @@ typedef union { UINT32 Value; ///< } FCRxFF30_0134_STRUCT; +// **** FCRxFF30_01F4 Register Definition **** +// Address +#define FCRxFF30_01F4_ADDRESS 0xff3001f4 + +// Type +#define FCRxFF30_01F4_TYPE TYPE_FCR +// Field Data +#define FCRxFF30_01F4_CgRlcCgttSclkOverride_OFFSET 0 +#define FCRxFF30_01F4_CgRlcCgttSclkOverride_WIDTH 1 +#define FCRxFF30_01F4_CgRlcCgttSclkOverride_MASK 0x1 +#define FCRxFF30_01F4_CgCpCgttSclkOverride_OFFSET 1 +#define FCRxFF30_01F4_CgCpCgttSclkOverride_WIDTH 1 +#define FCRxFF30_01F4_CgCpCgttSclkOverride_MASK 0x2 +#define FCRxFF30_01F4_CgVgtCgttSclkOverride_OFFSET 2 +#define FCRxFF30_01F4_CgVgtCgttSclkOverride_WIDTH 1 +#define FCRxFF30_01F4_CgVgtCgttSclkOverride_MASK 0x4 +#define FCRxFF30_01F4_CgPaCgttSclkOverride_OFFSET 3 +#define FCRxFF30_01F4_CgPaCgttSclkOverride_WIDTH 1 +#define FCRxFF30_01F4_CgPaCgttSclkOverride_MASK 0x8 +#define FCRxFF30_01F4_CgScCgttSclkOverride_OFFSET 4 +#define FCRxFF30_01F4_CgScCgttSclkOverride_WIDTH 1 +#define FCRxFF30_01F4_CgScCgttSclkOverride_MASK 0x10 +#define FCRxFF30_01F4_CgSpimCgttSclkOverride_OFFSET 5 +#define FCRxFF30_01F4_CgSpimCgttSclkOverride_WIDTH 1 +#define FCRxFF30_01F4_CgSpimCgttSclkOverride_MASK 0x20 +#define FCRxFF30_01F4_CgSxmCgttSclkOverride_OFFSET 6 +#define FCRxFF30_01F4_CgSxmCgttSclkOverride_WIDTH 1 +#define FCRxFF30_01F4_CgSxmCgttSclkOverride_MASK 0x40 +#define FCRxFF30_01F4_CgSxsCgttSclkOverride_OFFSET 7 +#define FCRxFF30_01F4_CgSxsCgttSclkOverride_WIDTH 1 +#define FCRxFF30_01F4_CgSxsCgttSclkOverride_MASK 0x80 +#define FCRxFF30_01F4_CgCb0CgttSclkOverride_OFFSET 8 +#define FCRxFF30_01F4_CgCb0CgttSclkOverride_WIDTH 1 +#define FCRxFF30_01F4_CgCb0CgttSclkOverride_MASK 0x100 +#define FCRxFF30_01F4_CgCb1CgttSclkOverride_OFFSET 9 +#define FCRxFF30_01F4_CgCb1CgttSclkOverride_WIDTH 1 +#define FCRxFF30_01F4_CgCb1CgttSclkOverride_MASK 0x200 +#define FCRxFF30_01F4_ReservedCgtt10Override_OFFSET 10 +#define FCRxFF30_01F4_ReservedCgtt10Override_WIDTH 1 +#define FCRxFF30_01F4_ReservedCgtt10Override_MASK 0x400 +#define FCRxFF30_01F4_ReservedCgtt11Override_OFFSET 11 +#define FCRxFF30_01F4_ReservedCgtt11Override_WIDTH 1 +#define FCRxFF30_01F4_ReservedCgtt11Override_MASK 0x800 +#define FCRxFF30_01F4_CgDb0CgttSclkOverride_OFFSET 12 +#define FCRxFF30_01F4_CgDb0CgttSclkOverride_WIDTH 1 +#define FCRxFF30_01F4_CgDb0CgttSclkOverride_MASK 0x1000 +#define FCRxFF30_01F4_CgDb1CgttSclkOverride_OFFSET 13 +#define FCRxFF30_01F4_CgDb1CgttSclkOverride_WIDTH 1 +#define FCRxFF30_01F4_CgDb1CgttSclkOverride_MASK 0x2000 +#define FCRxFF30_01F4_ReservedCgtt14Override_OFFSET 14 +#define FCRxFF30_01F4_ReservedCgtt14Override_WIDTH 1 +#define FCRxFF30_01F4_ReservedCgtt14Override_MASK 0x4000 +#define FCRxFF30_01F4_ReservedCgtt15Override_OFFSET 15 +#define FCRxFF30_01F4_ReservedCgtt15Override_WIDTH 1 +#define FCRxFF30_01F4_ReservedCgtt15Override_MASK 0x8000 +#define FCRxFF30_01F4_CgVcCgttSclkOverride_OFFSET 16 +#define FCRxFF30_01F4_CgVcCgttSclkOverride_WIDTH 1 +#define FCRxFF30_01F4_CgVcCgttSclkOverride_MASK 0x10000 +#define FCRxFF30_01F4_CgAvpCgttSclkOverride_OFFSET 17 +#define FCRxFF30_01F4_CgAvpCgttSclkOverride_WIDTH 1 +#define FCRxFF30_01F4_CgAvpCgttSclkOverride_MASK 0x20000 +#define FCRxFF30_01F4_CgAvpCgttEclkOverride_OFFSET 18 +#define FCRxFF30_01F4_CgAvpCgttEclkOverride_WIDTH 1 +#define FCRxFF30_01F4_CgAvpCgttEclkOverride_MASK 0x40000 +#define FCRxFF30_01F4_CgUvdmCgttSclkOverride_OFFSET 19 +#define FCRxFF30_01F4_CgUvdmCgttSclkOverride_WIDTH 1 +#define FCRxFF30_01F4_CgUvdmCgttSclkOverride_MASK 0x80000 +#define FCRxFF30_01F4_CgUvdmCgttVclkOverride_OFFSET 20 +#define FCRxFF30_01F4_CgUvdmCgttVclkOverride_WIDTH 1 +#define FCRxFF30_01F4_CgUvdmCgttVclkOverride_MASK 0x100000 +#define FCRxFF30_01F4_CgUvdmCgttDclkOverride_OFFSET 21 +#define FCRxFF30_01F4_CgUvdmCgttDclkOverride_WIDTH 1 +#define FCRxFF30_01F4_CgUvdmCgttDclkOverride_MASK 0x200000 +#define FCRxFF30_01F4_CgBifCgttSclkOverride_OFFSET 22 +#define FCRxFF30_01F4_CgBifCgttSclkOverride_WIDTH 1 +#define FCRxFF30_01F4_CgBifCgttSclkOverride_MASK 0x400000 +#define FCRxFF30_01F4_CgRomCgttSclkOverride_OFFSET 23 +#define FCRxFF30_01F4_CgRomCgttSclkOverride_WIDTH 1 +#define FCRxFF30_01F4_CgRomCgttSclkOverride_MASK 0x800000 +#define FCRxFF30_01F4_CgDrmCgttSclkOverride_OFFSET 24 +#define FCRxFF30_01F4_CgDrmCgttSclkOverride_WIDTH 1 +#define FCRxFF30_01F4_CgDrmCgttSclkOverride_MASK 0x1000000 +#define FCRxFF30_01F4_CgDcCgttSclkOverride_OFFSET 25 +#define FCRxFF30_01F4_CgDcCgttSclkOverride_WIDTH 1 +#define FCRxFF30_01F4_CgDcCgttSclkOverride_MASK 0x2000000 +#define FCRxFF30_01F4_ReservedCgtt26Override_OFFSET 26 +#define FCRxFF30_01F4_ReservedCgtt26Override_WIDTH 1 +#define FCRxFF30_01F4_ReservedCgtt26Override_MASK 0x4000000 +#define FCRxFF30_01F4_CgMcbCgttSclkOverride_OFFSET 27 +#define FCRxFF30_01F4_CgMcbCgttSclkOverride_WIDTH 1 +#define FCRxFF30_01F4_CgMcbCgttSclkOverride_MASK 0x8000000 +#define FCRxFF30_01F4_CgMcdwCgttSclkOverride_OFFSET 28 +#define FCRxFF30_01F4_CgMcdwCgttSclkOverride_WIDTH 1 +#define FCRxFF30_01F4_CgMcdwCgttSclkOverride_MASK 0x10000000 +#define FCRxFF30_01F4_ReservedCgtt29Override_OFFSET 29 +#define FCRxFF30_01F4_ReservedCgtt29Override_WIDTH 1 +#define FCRxFF30_01F4_ReservedCgtt29Override_MASK 0x20000000 +#define FCRxFF30_01F4_ReservedCgtt30Override_OFFSET 30 +#define FCRxFF30_01F4_ReservedCgtt30Override_WIDTH 1 +#define FCRxFF30_01F4_ReservedCgtt30Override_MASK 0x40000000 +#define FCRxFF30_01F4_ReservedCgtt31Override_OFFSET 31 +#define FCRxFF30_01F4_ReservedCgtt31Override_WIDTH 1 +#define FCRxFF30_01F4_ReservedCgtt31Override_MASK 0x80000000 + +/// FCRxFF30_01F4 +typedef union { + struct { ///< + UINT32 CgRlcCgttSclkOverride:1 ; ///< + UINT32 CgCpCgttSclkOverride:1 ; ///< + UINT32 CgVgtCgttSclkOverride:1 ; ///< + UINT32 CgPaCgttSclkOverride:1 ; ///< + UINT32 CgScCgttSclkOverride:1 ; ///< + UINT32 CgSpimCgttSclkOverride:1 ; ///< + UINT32 CgSxmCgttSclkOverride:1 ; ///< + UINT32 CgSxsCgttSclkOverride:1 ; ///< + UINT32 CgCb0CgttSclkOverride:1 ; ///< + UINT32 CgCb1CgttSclkOverride:1 ; ///< + UINT32 ReservedCgtt10Override:1 ; ///< + UINT32 ReservedCgtt11Override:1 ; ///< + UINT32 CgDb0CgttSclkOverride:1 ; ///< + UINT32 CgDb1CgttSclkOverride:1 ; ///< + UINT32 ReservedCgtt14Override:1 ; ///< + UINT32 ReservedCgtt15Override:1 ; ///< + UINT32 CgVcCgttSclkOverride:1 ; ///< + UINT32 CgAvpCgttSclkOverride:1 ; ///< + UINT32 CgAvpCgttEclkOverride:1 ; ///< + UINT32 CgUvdmCgttSclkOverride:1 ; ///< + UINT32 CgUvdmCgttVclkOverride:1 ; ///< + UINT32 CgUvdmCgttDclkOverride:1 ; ///< + UINT32 CgBifCgttSclkOverride:1 ; ///< + UINT32 CgRomCgttSclkOverride:1 ; ///< + UINT32 CgDrmCgttSclkOverride:1 ; ///< + UINT32 CgDcCgttSclkOverride:1 ; ///< + UINT32 ReservedCgtt26Override:1 ; ///< + UINT32 CgMcbCgttSclkOverride:1 ; ///< + UINT32 CgMcdwCgttSclkOverride:1 ; ///< + UINT32 ReservedCgtt29Override:1 ; ///< + UINT32 ReservedCgtt30Override:1 ; ///< + UINT32 ReservedCgtt31Override:1 ; ///< + } Field; ///< + UINT32 Value; ///< +} FCRxFF30_01F4_STRUCT; + +// **** FCRxFF30_01F5 Register Definition **** +// Address +#define FCRxFF30_01F5_ADDRESS 0xff3001f5 + +// Type +#define FCRxFF30_01F5_TYPE TYPE_FCR +// Field Data +#define FCRxFF30_01F5_ReservedCgtt32Override_OFFSET 0 +#define FCRxFF30_01F5_ReservedCgtt32Override_WIDTH 1 +#define FCRxFF30_01F5_ReservedCgtt32Override_MASK 0x1 +#define FCRxFF30_01F5_ReservedCgtt33Override_OFFSET 1 +#define FCRxFF30_01F5_ReservedCgtt33Override_WIDTH 1 +#define FCRxFF30_01F5_ReservedCgtt33Override_MASK 0x2 +#define FCRxFF30_01F5_ReservedCgtt34Override_OFFSET 2 +#define FCRxFF30_01F5_ReservedCgtt34Override_WIDTH 1 +#define FCRxFF30_01F5_ReservedCgtt34Override_MASK 0x4 +#define FCRxFF30_01F5_ReservedCgtt35Override_OFFSET 3 +#define FCRxFF30_01F5_ReservedCgtt35Override_WIDTH 1 +#define FCRxFF30_01F5_ReservedCgtt35Override_MASK 0x8 +#define FCRxFF30_01F5_CgTaCgttSclkOverride_OFFSET 4 +#define FCRxFF30_01F5_CgTaCgttSclkOverride_WIDTH 1 +#define FCRxFF30_01F5_CgTaCgttSclkOverride_MASK 0x10 +#define FCRxFF30_01F5_CgTdCgttSclkOverride_OFFSET 5 +#define FCRxFF30_01F5_CgTdCgttSclkOverride_WIDTH 1 +#define FCRxFF30_01F5_CgTdCgttSclkOverride_MASK 0x20 +#define FCRxFF30_01F5_CgTcaCgttSclkOverride_OFFSET 6 +#define FCRxFF30_01F5_CgTcaCgttSclkOverride_WIDTH 1 +#define FCRxFF30_01F5_CgTcaCgttSclkOverride_MASK 0x40 +#define FCRxFF30_01F5_CgTcpCgttSclkOverride_OFFSET 7 +#define FCRxFF30_01F5_CgTcpCgttSclkOverride_WIDTH 1 +#define FCRxFF30_01F5_CgTcpCgttSclkOverride_MASK 0x80 +#define FCRxFF30_01F5_CgTccCgttSclkOverride_OFFSET 8 +#define FCRxFF30_01F5_CgTccCgttSclkOverride_WIDTH 1 +#define FCRxFF30_01F5_CgTccCgttSclkOverride_MASK 0x100 +#define FCRxFF30_01F5_CgSqCgttSclkOverride_OFFSET 9 +#define FCRxFF30_01F5_CgSqCgttSclkOverride_WIDTH 1 +#define FCRxFF30_01F5_CgSqCgttSclkOverride_MASK 0x200 +#define FCRxFF30_01F5_CgHdpCgttSclkOverride_OFFSET 10 +#define FCRxFF30_01F5_CgHdpCgttSclkOverride_WIDTH 1 +#define FCRxFF30_01F5_CgHdpCgttSclkOverride_MASK 0x400 +#define FCRxFF30_01F5_CgVmcCgttSclkOverride_OFFSET 11 +#define FCRxFF30_01F5_CgVmcCgttSclkOverride_WIDTH 1 +#define FCRxFF30_01F5_CgVmcCgttSclkOverride_MASK 0x800 +#define FCRxFF30_01F5_CgOrbCgttSclkOverride_OFFSET 12 +#define FCRxFF30_01F5_CgOrbCgttSclkOverride_WIDTH 1 +#define FCRxFF30_01F5_CgOrbCgttSclkOverride_MASK 0x1000 +#define FCRxFF30_01F5_CgOrbCgttLclkOverride_OFFSET 13 +#define FCRxFF30_01F5_CgOrbCgttLclkOverride_WIDTH 1 +#define FCRxFF30_01F5_CgOrbCgttLclkOverride_MASK 0x2000 +#define FCRxFF30_01F5_CgIocCgttSclkOverride_OFFSET 14 +#define FCRxFF30_01F5_CgIocCgttSclkOverride_WIDTH 1 +#define FCRxFF30_01F5_CgIocCgttSclkOverride_MASK 0x4000 +#define FCRxFF30_01F5_CgIocCgttLclkOverride_OFFSET 15 +#define FCRxFF30_01F5_CgIocCgttLclkOverride_WIDTH 1 +#define FCRxFF30_01F5_CgIocCgttLclkOverride_MASK 0x8000 +#define FCRxFF30_01F5_CgGrbmCgttSclkOverride_OFFSET 16 +#define FCRxFF30_01F5_CgGrbmCgttSclkOverride_WIDTH 1 +#define FCRxFF30_01F5_CgGrbmCgttSclkOverride_MASK 0x10000 +#define FCRxFF30_01F5_ReservedCgtt49Override_OFFSET 17 +#define FCRxFF30_01F5_ReservedCgtt49Override_WIDTH 1 +#define FCRxFF30_01F5_ReservedCgtt49Override_MASK 0x20000 +#define FCRxFF30_01F5_CgSmuCgttSclkOverride_OFFSET 18 +#define FCRxFF30_01F5_CgSmuCgttSclkOverride_WIDTH 1 +#define FCRxFF30_01F5_CgSmuCgttSclkOverride_MASK 0x40000 +#define FCRxFF30_01F5_ReservedCgtt51Override_OFFSET 19 +#define FCRxFF30_01F5_ReservedCgtt51Override_WIDTH 1 +#define FCRxFF30_01F5_ReservedCgtt51Override_MASK 0x80000 +#define FCRxFF30_01F5_CgIhCgttSclkOverride_OFFSET 20 +#define FCRxFF30_01F5_CgIhCgttSclkOverride_WIDTH 1 +#define FCRxFF30_01F5_CgIhCgttSclkOverride_MASK 0x100000 +#define FCRxFF30_01F5_CgDbgCgttSclkOverride_OFFSET 21 +#define FCRxFF30_01F5_CgDbgCgttSclkOverride_WIDTH 1 +#define FCRxFF30_01F5_CgDbgCgttSclkOverride_MASK 0x200000 +#define FCRxFF30_01F5_CgSemCgttSclkOverride_OFFSET 22 +#define FCRxFF30_01F5_CgSemCgttSclkOverride_WIDTH 1 +#define FCRxFF30_01F5_CgSemCgttSclkOverride_MASK 0x400000 +#define FCRxFF30_01F5_CgSrbmCgttSclkOverride_OFFSET 23 +#define FCRxFF30_01F5_CgSrbmCgttSclkOverride_WIDTH 1 +#define FCRxFF30_01F5_CgSrbmCgttSclkOverride_MASK 0x800000 +#define FCRxFF30_01F5_CgDrmdmaCgttSclkOverride_OFFSET 24 +#define FCRxFF30_01F5_CgDrmdmaCgttSclkOverride_WIDTH 1 +#define FCRxFF30_01F5_CgDrmdmaCgttSclkOverride_MASK 0x1000000 +#define FCRxFF30_01F5_CgUvduCgttSclkOverride_OFFSET 25 +#define FCRxFF30_01F5_CgUvduCgttSclkOverride_WIDTH 1 +#define FCRxFF30_01F5_CgUvduCgttSclkOverride_MASK 0x2000000 +#define FCRxFF30_01F5_CgUvduCgttVclkOverride_OFFSET 26 +#define FCRxFF30_01F5_CgUvduCgttVclkOverride_WIDTH 1 +#define FCRxFF30_01F5_CgUvduCgttVclkOverride_MASK 0x4000000 +#define FCRxFF30_01F5_CgUvduCgttDclkOverride_OFFSET 27 +#define FCRxFF30_01F5_CgUvduCgttDclkOverride_WIDTH 1 +#define FCRxFF30_01F5_CgUvduCgttDclkOverride_MASK 0x8000000 +#define FCRxFF30_01F5_CgDcCgttDispclkOverride_OFFSET 28 +#define FCRxFF30_01F5_CgDcCgttDispclkOverride_WIDTH 1 +#define FCRxFF30_01F5_CgDcCgttDispclkOverride_MASK 0x10000000 +#define FCRxFF30_01F5_CgXbrCgttSclkOverride_OFFSET 29 +#define FCRxFF30_01F5_CgXbrCgttSclkOverride_WIDTH 1 +#define FCRxFF30_01F5_CgXbrCgttSclkOverride_MASK 0x20000000 +#define FCRxFF30_01F5_CgSpimCgtsSclkOverride_OFFSET 30 +#define FCRxFF30_01F5_CgSpimCgtsSclkOverride_WIDTH 1 +#define FCRxFF30_01F5_CgSpimCgtsSclkOverride_MASK 0x40000000 +#define FCRxFF30_01F5_CgSpimCgtsSclkLsOverride_OFFSET 31 +#define FCRxFF30_01F5_CgSpimCgtsSclkLsOverride_WIDTH 1 +#define FCRxFF30_01F5_CgSpimCgtsSclkLsOverride_MASK 0x80000000 + +/// FCRxFF30_01F5 +typedef union { + struct { ///< + UINT32 ReservedCgtt32Override:1 ; ///< + UINT32 ReservedCgtt33Override:1 ; ///< + UINT32 ReservedCgtt34Override:1 ; ///< + UINT32 ReservedCgtt35Override:1 ; ///< + UINT32 CgTaCgttSclkOverride:1 ; ///< + UINT32 CgTdCgttSclkOverride:1 ; ///< + UINT32 CgTcaCgttSclkOverride:1 ; ///< + UINT32 CgTcpCgttSclkOverride:1 ; ///< + UINT32 CgTccCgttSclkOverride:1 ; ///< + UINT32 CgSqCgttSclkOverride:1 ; ///< + UINT32 CgHdpCgttSclkOverride:1 ; ///< + UINT32 CgVmcCgttSclkOverride:1 ; ///< + UINT32 CgOrbCgttSclkOverride:1 ; ///< + UINT32 CgOrbCgttLclkOverride:1 ; ///< + UINT32 CgIocCgttSclkOverride:1 ; ///< + UINT32 CgIocCgttLclkOverride:1 ; ///< + UINT32 CgGrbmCgttSclkOverride:1 ; ///< + UINT32 ReservedCgtt49Override:1 ; ///< + UINT32 CgSmuCgttSclkOverride:1 ; ///< + UINT32 ReservedCgtt51Override:1 ; ///< + UINT32 CgIhCgttSclkOverride:1 ; ///< + UINT32 CgDbgCgttSclkOverride:1 ; ///< + UINT32 CgSemCgttSclkOverride:1 ; ///< + UINT32 CgSrbmCgttSclkOverride:1 ; ///< + UINT32 CgDrmdmaCgttSclkOverride:1 ; ///< + UINT32 CgUvduCgttSclkOverride:1 ; ///< + UINT32 CgUvduCgttVclkOverride:1 ; ///< + UINT32 CgUvduCgttDclkOverride:1 ; ///< + UINT32 CgDcCgttDispclkOverride:1 ; ///< + UINT32 CgXbrCgttSclkOverride:1 ; ///< + UINT32 CgSpimCgtsSclkOverride:1 ; ///< + UINT32 CgSpimCgtsSclkLsOverride:1 ; ///< + } Field; ///< + UINT32 Value; ///< +} FCRxFF30_01F5_STRUCT; + // **** FCRxFF30_1B7C(GMMx6DF0) Register Definition **** // Address #define FCRxFF30_1B7C_ADDRESS 0xff301B7C @@ -10016,191 +13359,6 @@ typedef union { UINT32 Value; ///< } SMUx0B_x8498_STRUCT; -// **** D0F0xE4_WRAP_8013 Register Definition **** -// Address -#define D0F0xE4_WRAP_8013_ADDRESS 0x8013 - -// Field Data -#define D0F0xE4_WRAP_8013_MasterPciePllA_OFFSET 0 -#define D0F0xE4_WRAP_8013_MasterPciePllA_WIDTH 1 -#define D0F0xE4_WRAP_8013_MasterPciePllA_MASK 0x1 -#define D0F0xE4_WRAP_8013_Reserved_1_1_OFFSET 1 -#define D0F0xE4_WRAP_8013_Reserved_1_1_WIDTH 1 -#define D0F0xE4_WRAP_8013_Reserved_1_1_MASK 0x2 -#define D0F0xE4_WRAP_8013_Reserved_2_2_OFFSET 2 -#define D0F0xE4_WRAP_8013_Reserved_2_2_WIDTH 1 -#define D0F0xE4_WRAP_8013_Reserved_2_2_MASK 0x4 -#define D0F0xE4_WRAP_8013_Reserved_3_3_OFFSET 3 -#define D0F0xE4_WRAP_8013_Reserved_3_3_WIDTH 1 -#define D0F0xE4_WRAP_8013_Reserved_3_3_MASK 0x8 -#define D0F0xE4_WRAP_8013_ClkDividerResetOverrideA_OFFSET 4 -#define D0F0xE4_WRAP_8013_ClkDividerResetOverrideA_WIDTH 1 -#define D0F0xE4_WRAP_8013_ClkDividerResetOverrideA_MASK 0x10 -#define D0F0xE4_WRAP_8013_Reserved_5_5_OFFSET 5 -#define D0F0xE4_WRAP_8013_Reserved_5_5_WIDTH 1 -#define D0F0xE4_WRAP_8013_Reserved_5_5_MASK 0x20 -#define D0F0xE4_WRAP_8013_Reserved_6_6_OFFSET 6 -#define D0F0xE4_WRAP_8013_Reserved_6_6_WIDTH 1 -#define D0F0xE4_WRAP_8013_Reserved_6_6_MASK 0x40 -#define D0F0xE4_WRAP_8013_Reserved_7_7_OFFSET 7 -#define D0F0xE4_WRAP_8013_Reserved_7_7_WIDTH 1 -#define D0F0xE4_WRAP_8013_Reserved_7_7_MASK 0x80 -#define D0F0xE4_WRAP_8013_TxclkSelCoreOverride_OFFSET 8 -#define D0F0xE4_WRAP_8013_TxclkSelCoreOverride_WIDTH 1 -#define D0F0xE4_WRAP_8013_TxclkSelCoreOverride_MASK 0x100 -#define D0F0xE4_WRAP_8013_TxclkSelPifAOverride_OFFSET 9 -#define D0F0xE4_WRAP_8013_TxclkSelPifAOverride_WIDTH 1 -#define D0F0xE4_WRAP_8013_TxclkSelPifAOverride_MASK 0x200 -#define D0F0xE4_WRAP_8013_Reserved_10_10_OFFSET 10 -#define D0F0xE4_WRAP_8013_Reserved_10_10_WIDTH 1 -#define D0F0xE4_WRAP_8013_Reserved_10_10_MASK 0x400 -#define D0F0xE4_WRAP_8013_Reserved_11_11_OFFSET 11 -#define D0F0xE4_WRAP_8013_Reserved_11_11_WIDTH 1 -#define D0F0xE4_WRAP_8013_Reserved_11_11_MASK 0x800 -#define D0F0xE4_WRAP_8013_Reserved_12_12_OFFSET 12 -#define D0F0xE4_WRAP_8013_Reserved_12_12_WIDTH 1 -#define D0F0xE4_WRAP_8013_Reserved_12_12_MASK 0x1000 -#define D0F0xE4_WRAP_8013_Reserved_15_13_OFFSET 13 -#define D0F0xE4_WRAP_8013_Reserved_15_13_WIDTH 3 -#define D0F0xE4_WRAP_8013_Reserved_15_13_MASK 0xe000 -#define D0F0xE4_WRAP_8013_Reserved_16_16_OFFSET 16 -#define D0F0xE4_WRAP_8013_Reserved_16_16_WIDTH 1 -#define D0F0xE4_WRAP_8013_Reserved_16_16_MASK 0x10000 -#define D0F0xE4_WRAP_8013_Reserved_19_17_OFFSET 17 -#define D0F0xE4_WRAP_8013_Reserved_19_17_WIDTH 3 -#define D0F0xE4_WRAP_8013_Reserved_19_17_MASK 0xe0000 -#define D0F0xE4_WRAP_8013_Reserved_20_20_OFFSET 20 -#define D0F0xE4_WRAP_8013_Reserved_20_20_WIDTH 1 -#define D0F0xE4_WRAP_8013_Reserved_20_20_MASK 0x100000 -#define D0F0xE4_WRAP_8013_Reserved_31_21_OFFSET 21 -#define D0F0xE4_WRAP_8013_Reserved_31_21_WIDTH 11 -#define D0F0xE4_WRAP_8013_Reserved_31_21_MASK 0xffe00000 - -/// D0F0xE4_WRAP_8013 -typedef union { - struct { ///< - UINT32 MasterPciePllA:1 ; ///< - UINT32 MasterPciePllB:1 ; ///< - UINT32 MasterPciePllC:1 ; ///< - UINT32 MasterPciePllD:1 ; ///< - UINT32 ClkDividerResetOverrideA:1 ; ///< - UINT32 Reserved_5_5:1 ; ///< - UINT32 Reserved_6_6:1 ; ///< - UINT32 Reserved_7_7:1 ; ///< - UINT32 TxclkSelCoreOverride:1 ; ///< - UINT32 TxclkSelPifAOverride:1 ; ///< - UINT32 Reserved_10_10:1 ; ///< - UINT32 Reserved_11_11:1 ; ///< - UINT32 Reserved_12_12:1 ; ///< - UINT32 Reserved_15_13:3 ; ///< - UINT32 Reserved_16_16:1 ; ///< - UINT32 Reserved_19_17:3 ; ///< - UINT32 Reserved_20_20:1 ; ///< - UINT32 Reserved_31_21:11; ///< - } Field; ///< - UINT32 Value; ///< -} D0F0xE4_WRAP_8013_STRUCT; - -// **** D0F0xE4_WRAP_8014 Register Definition **** -// Address -#define D0F0xE4_WRAP_8014_ADDRESS 0x8014 - -// Field Data -#define D0F0xE4_WRAP_8014_TxclkPermGateEnable_OFFSET 0 -#define D0F0xE4_WRAP_8014_TxclkPermGateEnable_WIDTH 1 -#define D0F0xE4_WRAP_8014_TxclkPermGateEnable_MASK 0x1 -#define D0F0xE4_WRAP_8014_TxclkPrbsGateEnable_OFFSET 1 -#define D0F0xE4_WRAP_8014_TxclkPrbsGateEnable_WIDTH 1 -#define D0F0xE4_WRAP_8014_TxclkPrbsGateEnable_MASK 0x2 -#define D0F0xE4_WRAP_8014_Reserved_2_2_OFFSET 2 -#define D0F0xE4_WRAP_8014_Reserved_2_2_WIDTH 1 -#define D0F0xE4_WRAP_8014_Reserved_2_2_MASK 0x4 -#define D0F0xE4_WRAP_8014_Reserved_3_3_OFFSET 3 -#define D0F0xE4_WRAP_8014_Reserved_3_3_WIDTH 1 -#define D0F0xE4_WRAP_8014_Reserved_3_3_MASK 0x8 -#define D0F0xE4_WRAP_8014_Reserved_4_4_OFFSET 4 -#define D0F0xE4_WRAP_8014_Reserved_4_4_WIDTH 1 -#define D0F0xE4_WRAP_8014_Reserved_4_4_MASK 0x10 -#define D0F0xE4_WRAP_8014_Reserved_5_5_OFFSET 5 -#define D0F0xE4_WRAP_8014_Reserved_5_5_WIDTH 1 -#define D0F0xE4_WRAP_8014_Reserved_5_5_MASK 0x20 -#define D0F0xE4_WRAP_8014_Reserved_6_6_OFFSET 6 -#define D0F0xE4_WRAP_8014_Reserved_6_6_WIDTH 1 -#define D0F0xE4_WRAP_8014_Reserved_6_6_MASK 0x40 -#define D0F0xE4_WRAP_8014_Reserved_7_7_OFFSET 7 -#define D0F0xE4_WRAP_8014_Reserved_7_7_WIDTH 1 -#define D0F0xE4_WRAP_8014_Reserved_7_7_MASK 0x80 -#define D0F0xE4_WRAP_8014_Reserved_8_8_OFFSET 8 -#define D0F0xE4_WRAP_8014_Reserved_8_8_WIDTH 1 -#define D0F0xE4_WRAP_8014_Reserved_8_8_MASK 0x100 -#define D0F0xE4_WRAP_8014_Reserved_9_9_OFFSET 9 -#define D0F0xE4_WRAP_8014_Reserved_9_9_WIDTH 1 -#define D0F0xE4_WRAP_8014_Reserved_9_9_MASK 0x200 -#define D0F0xE4_WRAP_8014_Reserved_10_10_OFFSET 10 -#define D0F0xE4_WRAP_8014_Reserved_10_10_WIDTH 1 -#define D0F0xE4_WRAP_8014_Reserved_10_10_MASK 0x400 -#define D0F0xE4_WRAP_8014_Reserved_11_11_OFFSET 11 -#define D0F0xE4_WRAP_8014_Reserved_11_11_WIDTH 1 -#define D0F0xE4_WRAP_8014_Reserved_11_11_MASK 0x800 -#define D0F0xE4_WRAP_8014_PcieGatePifA1xEnable_OFFSET 12 -#define D0F0xE4_WRAP_8014_PcieGatePifA1xEnable_WIDTH 1 -#define D0F0xE4_WRAP_8014_PcieGatePifA1xEnable_MASK 0x1000 -#define D0F0xE4_WRAP_8014_Reserved_13_13_OFFSET 13 -#define D0F0xE4_WRAP_8014_Reserved_13_13_WIDTH 1 -#define D0F0xE4_WRAP_8014_Reserved_13_13_MASK 0x2000 -#define D0F0xE4_WRAP_8014_Reserved_14_14_OFFSET 14 -#define D0F0xE4_WRAP_8014_Reserved_14_14_WIDTH 1 -#define D0F0xE4_WRAP_8014_Reserved_14_14_MASK 0x4000 -#define D0F0xE4_WRAP_8014_Reserved_15_15_OFFSET 15 -#define D0F0xE4_WRAP_8014_Reserved_15_15_WIDTH 1 -#define D0F0xE4_WRAP_8014_Reserved_15_15_MASK 0x8000 -#define D0F0xE4_WRAP_8014_PcieGatePifA2p5xEnable_OFFSET 16 -#define D0F0xE4_WRAP_8014_PcieGatePifA2p5xEnable_WIDTH 1 -#define D0F0xE4_WRAP_8014_PcieGatePifA2p5xEnable_MASK 0x10000 -#define D0F0xE4_WRAP_8014_Reserved_17_17_OFFSET 17 -#define D0F0xE4_WRAP_8014_Reserved_17_17_WIDTH 1 -#define D0F0xE4_WRAP_8014_Reserved_17_17_MASK 0x20000 -#define D0F0xE4_WRAP_8014_Reserved_18_18_OFFSET 18 -#define D0F0xE4_WRAP_8014_Reserved_18_18_WIDTH 1 -#define D0F0xE4_WRAP_8014_Reserved_18_18_MASK 0x40000 -#define D0F0xE4_WRAP_8014_Reserved_19_19_OFFSET 19 -#define D0F0xE4_WRAP_8014_Reserved_19_19_WIDTH 1 -#define D0F0xE4_WRAP_8014_Reserved_19_19_MASK 0x80000 -#define D0F0xE4_WRAP_8014_TxclkPermGateOnlyWhenPllPwrDn_OFFSET 20 -#define D0F0xE4_WRAP_8014_TxclkPermGateOnlyWhenPllPwrDn_WIDTH 1 -#define D0F0xE4_WRAP_8014_TxclkPermGateOnlyWhenPllPwrDn_MASK 0x100000 -#define D0F0xE4_WRAP_8014_Reserved_31_21_OFFSET 21 -#define D0F0xE4_WRAP_8014_Reserved_31_21_WIDTH 11 -#define D0F0xE4_WRAP_8014_Reserved_31_21_MASK 0xffe00000 - -/// D0F0xE4_WRAP_8014 -typedef union { - struct { - UINT32 TxclkPermGateEnable:1 ; ///< - UINT32 TxclkPrbsGateEnable:1 ; ///< - UINT32 DdiGatePifA1xEnable:1 ; ///< - UINT32 DdiGatePifB1xEnable:1 ; ///< - UINT32 DdiGatePifC1xEnable:1 ; ///< - UINT32 DdiGatePifD1xEnable:1 ; ///< - UINT32 DdiGateDigAEnable:1 ; ///< - UINT32 DdiGateDigBEnable:1 ; ///< - UINT32 DdiGatePifA2p5xEnable:1 ; ///< - UINT32 DdiGatePifB2p5xEnable:1 ; ///< - UINT32 DdiGatePifC2p5xEnable:1 ; ///< - UINT32 DdiGatePifD2p5xEnable:1 ; ///< - UINT32 PcieGatePifA1xEnable:1 ; ///< - UINT32 PcieGatePifB1xEnable:1 ; ///< - UINT32 PcieGatePifC1xEnable:1 ; ///< - UINT32 PcieGatePifD1xEnable:1 ; ///< - UINT32 PcieGatePifA2p5xEnable:1 ; ///< - UINT32 PcieGatePifB2p5xEnable:1 ; ///< - UINT32 PcieGatePifC2p5xEnable:1 ; ///< - UINT32 PcieGatePifD2p5xEnable:1 ; ///< - UINT32 TxclkPermGateOnlyWhenPllPwrDn:1 ; ///< - UINT32 Reserved_31_21:11; ///< - } Field; ///< - UINT32 Value; ///< -} D0F0xE4_WRAP_8014_STRUCT; // **** SMUx0B_x85B0 Register Definition **** // Address @@ -10262,6 +13420,107 @@ typedef union { UINT32 Value; ///< } D0F0x64_x51_STRUCT; +// **** D0F0xE4_PHY_6440 Register Definition **** +// Address +#define D0F0xE4_PHY_6440_ADDRESS 0x6440 + +// Type +#define D0F0xE4_PHY_6440_TYPE TYPE_D0F0xE4 +// Field Data +#define D0F0xE4_PHY_6440_RxInCalForce_OFFSET 7 +#define D0F0xE4_PHY_6440_RxInCalForce_WIDTH 1 +#define D0F0xE4_PHY_6440_RxInCalForce_MASK 0x80 + +// **** D0F0xE4_PHY_6480 Register Definition **** +// Address +#define D0F0xE4_PHY_6480_ADDRESS 0x6480 + +// Type +#define D0F0xE4_PHY_6480_TYPE TYPE_D0F0xE4 +// Field Data +#define D0F0xE4_PHY_6480_RxInCalForce_OFFSET 7 +#define D0F0xE4_PHY_6480_RxInCalForce_WIDTH 1 +#define D0F0xE4_PHY_6480_RxInCalForce_MASK 0x80 + +// **** D0F0xE4_PHY_6500 Register Definition **** +// Address +#define D0F0xE4_PHY_6500_ADDRESS 0x6500 + +// Type +#define D0F0xE4_PHY_6500_TYPE TYPE_D0F0xE4 +// Field Data +#define D0F0xE4_PHY_6500_RxInCalForce_OFFSET 7 +#define D0F0xE4_PHY_6500_RxInCalForce_WIDTH 1 +#define D0F0xE4_PHY_6500_RxInCalForce_MASK 0x80 + +// **** D0F0xE4_PHY_6600 Register Definition **** +// Address +#define D0F0xE4_PHY_6600_ADDRESS 0x6600 + +// Type +#define D0F0xE4_PHY_6600_TYPE TYPE_D0F0xE4 +// Field Data +#define D0F0xE4_PHY_6600_RxInCalForce_OFFSET 7 +#define D0F0xE4_PHY_6600_RxInCalForce_WIDTH 1 +#define D0F0xE4_PHY_6600_RxInCalForce_MASK 0x80 + + +// **** D0F0xE4_PHY_6840 Register Definition **** +// Address +#define D0F0xE4_PHY_6840_ADDRESS 0x6840 + +// Type +#define D0F0xE4_PHY_6840_TYPE TYPE_D0F0xE4 +// Field Data +#define D0F0xE4_PHY_6840_RxInCalForce_OFFSET 7 +#define D0F0xE4_PHY_6840_RxInCalForce_WIDTH 1 +#define D0F0xE4_PHY_6840_RxInCalForce_MASK 0x80 + + +// **** D0F0xE4_PHY_6880 Register Definition **** +// Address +#define D0F0xE4_PHY_6880_ADDRESS 0x6880 + +// Type +#define D0F0xE4_PHY_6880_TYPE TYPE_D0F0xE4 +// Field Data +#define D0F0xE4_PHY_6880_RxInCalForce_OFFSET 7 +#define D0F0xE4_PHY_6880_RxInCalForce_WIDTH 1 +#define D0F0xE4_PHY_6880_RxInCalForce_MASK 0x80 + +// **** D0F0xE4_PHY_6900 Register Definition **** +// Address +#define D0F0xE4_PHY_6900_ADDRESS 0x6900 + +// Type +#define D0F0xE4_PHY_6900_TYPE TYPE_D0F0xE4 +// Field Data +#define D0F0xE4_PHY_6900_RxInCalForce_OFFSET 7 +#define D0F0xE4_PHY_6900_RxInCalForce_WIDTH 1 +#define D0F0xE4_PHY_6900_RxInCalForce_MASK 0x80 + +// **** D0F0xE4_PHY_6A00 Register Definition **** +// Address +#define D0F0xE4_PHY_6A00_ADDRESS 0x6a00 + +// Type +#define D0F0xE4_PHY_6A00_TYPE TYPE_D0F0xE4 +// Field Data +#define D0F0xE4_PHY_6A00_RxInCalForce_OFFSET 7 +#define D0F0xE4_PHY_6A00_RxInCalForce_WIDTH 1 +#define D0F0xE4_PHY_6A00_RxInCalForce_MASK 0x80 + +// **** D0F0x64_x20 Register Definition **** +// Address +#define D0F0x64_x20_ADDRESS 0x20 + +// Type +#define D0F0x64_x20_TYPE TYPE_D0F0x64 +// Field Data +#define D0F0x64_x20_IocPcieDevRemapDis_OFFSET 1 +#define D0F0x64_x20_IocPcieDevRemapDis_WIDTH 1 +#define D0F0x64_x20_IocPcieDevRemapDis_MASK 0x2 + // **** SMUx33 Register Definition **** // Address #define SMUx33_ADDRESS 0x33 @@ -10275,24 +13534,36 @@ typedef union { #define SMUx33_LclkActMonUnt_OFFSET 16 #define SMUx33_LclkActMonUnt_WIDTH 4 #define SMUx33_LclkActMonUnt_MASK 0xf0000 -#define SMUx33_Reserved_22_20_OFFSET 20 -#define SMUx33_Reserved_22_20_WIDTH 3 -#define SMUx33_Reserved_22_20_MASK 0x700000 +#define SMUx33_TrendMode_OFFSET 20 +#define SMUx33_TrendMode_WIDTH 1 +#define SMUx33_TrendMode_MASK 0x100000 +#define SMUx33_ForceTrend_OFFSET 21 +#define SMUx33_ForceTrend_WIDTH 1 +#define SMUx33_ForceTrend_MASK 0x200000 +#define SMUx33_ActMonRst_OFFSET 22 +#define SMUx33_ActMonRst_WIDTH 1 +#define SMUx33_ActMonRst_MASK 0x400000 #define SMUx33_BusyCntSel_OFFSET 23 #define SMUx33_BusyCntSel_WIDTH 2 #define SMUx33_BusyCntSel_MASK 0x1800000 -#define SMUx33_Reserved_31_25_OFFSET 25 -#define SMUx33_Reserved_31_25_WIDTH 7 -#define SMUx33_Reserved_31_25_MASK 0xfe000000 +#define SMUx33_AccessCntl_OFFSET 25 +#define SMUx33_AccessCntl_WIDTH 1 +#define SMUx33_AccessCntl_MASK 0x2000000 +#define SMUx33_Reserved_31_26_OFFSET 26 +#define SMUx33_Reserved_31_26_WIDTH 6 +#define SMUx33_Reserved_31_26_MASK 0xfc000000 /// SMUx33 typedef union { struct { ///< UINT32 LclkActMonPrd:16; ///< UINT32 LclkActMonUnt:4 ; ///< - UINT32 Reserved_22_20:3 ; ///< + UINT32 TrendMode:1 ; ///< + UINT32 ForceTrend:1 ; ///< + UINT32 ActMonRst:1 ; ///< UINT32 BusyCntSel:2 ; ///< - UINT32 Reserved_31_25:7 ; ///< + UINT32 AccessCntl:1 ; ///< + UINT32 Reserved_31_26:6 ; ///< } Field; ///< UINT32 Value; ///< } SMUx33_STRUCT; @@ -10343,9 +13614,12 @@ typedef union { // Type #define FCRxFF30_01E4_TYPE TYPE_FCR // Field Data -#define FCRxFF30_01E4_Reserved_19_0_OFFSET 0 -#define FCRxFF30_01E4_Reserved_19_0_WIDTH 20 -#define FCRxFF30_01E4_Reserved_19_0_MASK 0xfffff +#define FCRxFF30_01E4_Fraction_OFFSET 0 +#define FCRxFF30_01E4_Fraction_WIDTH 8 +#define FCRxFF30_01E4_Fraction_MASK 0xff +#define FCRxFF30_01E4_Hysteresis_OFFSET 8 +#define FCRxFF30_01E4_Hysteresis_WIDTH 12 +#define FCRxFF30_01E4_Hysteresis_MASK 0xfff00 #define FCRxFF30_01E4_VoltageChangeEn_OFFSET 20 #define FCRxFF30_01E4_VoltageChangeEn_WIDTH 1 #define FCRxFF30_01E4_VoltageChangeEn_MASK 0x100000 @@ -10356,943 +13630,191 @@ typedef union { /// FCRxFF30_01E4 typedef union { struct { ///< - UINT32 Reserved_19_0:20; ///< + UINT32 Fraction:8 ; ///< + UINT32 Hysteresis:12; ///< UINT32 VoltageChangeEn:1 ; ///< UINT32 Reserved_31_21:11; ///< } Field; ///< UINT32 Value; ///< } FCRxFF30_01E4_STRUCT; - -// **** SMUx0B_x8470 Register Definition **** -// Address -#define SMUx0B_x8470_ADDRESS 0x8470 - - -// **** SMUx0B_x8440 Register Definition **** -// Address -#define SMUx0B_x8440_ADDRESS 0x8440 - - -// **** SMUx0B_x848C Register Definition **** -// Address -#define SMUx0B_x848C_ADDRESS 0x848c - - -// **** SMUx35 Register Definition **** +// **** SMUx0B_x84AC Register Definition **** // Address -#define SMUx35_ADDRESS 0x35 +#define SMUx0B_x84AC_ADDRESS 0x84ac // Type -#define SMUx35_TYPE TYPE_SMU +#define SMUx0B_x84AC_TYPE TYPE_SMUx0B // Field Data -#define SMUx35_DownTrendCoef_OFFSET 0 -#define SMUx35_DownTrendCoef_WIDTH 10 -#define SMUx35_DownTrendCoef_MASK 0x3ff -#define SMUx35_UpTrendCoef_OFFSET 10 -#define SMUx35_UpTrendCoef_WIDTH 10 -#define SMUx35_UpTrendCoef_MASK 0xffc00 -#define SMUx35_Reserved_31_20_OFFSET 20 -#define SMUx35_Reserved_31_20_WIDTH 12 -#define SMUx35_Reserved_31_20_MASK 0xfff00000 +#define SMUx0B_x84AC_FstateCredits_1_OFFSET 0 +#define SMUx0B_x84AC_FstateCredits_1_WIDTH 16 +#define SMUx0B_x84AC_FstateCredits_1_MASK 0xffff +#define SMUx0B_x84AC_FstateCredits_0_OFFSET 16 +#define SMUx0B_x84AC_FstateCredits_0_WIDTH 16 +#define SMUx0B_x84AC_FstateCredits_0_MASK 0xffff0000 -/// SMUx35 +/// SMUx0B_x84AC typedef union { struct { ///< - UINT32 DownTrendCoef:10; ///< - UINT32 UpTrendCoef:10; ///< - UINT32 Reserved_31_20:12; ///< + UINT32 FstateCredits_1:16; ///< + UINT32 FstateCredits_0:16; ///< } Field; ///< UINT32 Value; ///< -} SMUx35_STRUCT; - -// **** SMUx37 Register Definition **** -// Address -#define SMUx37_ADDRESS 0x37 +} SMUx0B_x84AC_STRUCT; - -// **** SMUx51 Register Definition **** -// Address -#define SMUx51_ADDRESS 0x51 - - -// **** SMUx0B_x8490 Register Definition **** -// Address -#define SMUx0B_x8490_ADDRESS 0x8490 - - -// **** DxF0xE4_xB5 Register Definition **** -// Address -#define DxF0xE4_xB5_ADDRESS 0xb5 - -// Type -#define DxF0xE4_xB5_TYPE TYPE_D4F0xE4 -// Field Data -#define DxF0xE4_xB5_Reserved_9_0_OFFSET 0 -#define DxF0xE4_xB5_Reserved_9_0_WIDTH 10 -#define DxF0xE4_xB5_Reserved_9_0_MASK 0x3ff -#define DxF0xE4_xB5_LcEnhancedHotPlugEn_OFFSET 10 -#define DxF0xE4_xB5_LcEnhancedHotPlugEn_WIDTH 1 -#define DxF0xE4_xB5_LcEnhancedHotPlugEn_MASK 0x400 -#define DxF0xE4_xB5_Reserved_11_11_OFFSET 11 -#define DxF0xE4_xB5_Reserved_11_11_WIDTH 1 -#define DxF0xE4_xB5_Reserved_11_11_MASK 0x800 -#define DxF0xE4_xB5_LcEhpRxPhyCmd_OFFSET 12 -#define DxF0xE4_xB5_LcEhpRxPhyCmd_WIDTH 2 -#define DxF0xE4_xB5_LcEhpRxPhyCmd_MASK 0x3000 -#define DxF0xE4_xB5_LcEhpTxPhyCmd_OFFSET 14 -#define DxF0xE4_xB5_LcEhpTxPhyCmd_WIDTH 2 -#define DxF0xE4_xB5_LcEhpTxPhyCmd_MASK 0xc000 -#define DxF0xE4_xB5_Reserved_31_16_OFFSET 16 -#define DxF0xE4_xB5_Reserved_31_16_WIDTH 16 -#define DxF0xE4_xB5_Reserved_31_16_MASK 0xffff0000 - -/// DxF0xE4_xB5 -typedef union { - struct { ///< - UINT32 Reserved_9_0:10; ///< - UINT32 LcEnhancedHotPlugEn:1 ; ///< - UINT32 Reserved_11_11:1 ; ///< - UINT32 LcEhpRxPhyCmd:2 ; ///< - UINT32 LcEhpTxPhyCmd:2 ; ///< - UINT32 Reserved_31_16:16 ; ///< - } Field; ///< - UINT32 Value; ///< -} DxF0xE4_xB5_STRUCT; - -// **** D0F0xE4_WRAP_80F0 Register Definition **** -// Address -#define D0F0xE4_WRAP_80F0_ADDRESS 0x80f0 - -// Type -#define D0F0xE4_WRAP_80F0_TYPE TYPE_D0F0xE4 -// Field Data -#define D0F0xE4_WRAP_80F0_MicroSeconds_OFFSET 0 -#define D0F0xE4_WRAP_80F0_MicroSeconds_WIDTH 32 -#define D0F0xE4_WRAP_80F0_MicroSeconds_MASK 0xffffffff - -/// D0F0xE4_WRAP_80F0 -typedef union { - struct { ///< - UINT32 MicroSeconds:32; ///< - } Field; ///< - UINT32 Value; ///< -} D0F0xE4_WRAP_80F0_STRUCT; - -// **** DxF0xE4_xA5 Register Definition **** -// Address -#define DxF0xE4_xA5_ADDRESS 0xa5 - - -// **** D0F0xE4_WRAP_8012 Register Definition **** -// Address -#define D0F0xE4_WRAP_8012_ADDRESS 0x8012 - -// Type -#define D0F0xE4_WRAP_8012_TYPE TYPE_D0F0xE4 -// Field Data -#define D0F0xE4_WRAP_8012_Pif1xIdleGateLatency_OFFSET 0 -#define D0F0xE4_WRAP_8012_Pif1xIdleGateLatency_WIDTH 6 -#define D0F0xE4_WRAP_8012_Pif1xIdleGateLatency_MASK 0x3f -#define D0F0xE4_WRAP_8012_Reserved_6_6_OFFSET 6 -#define D0F0xE4_WRAP_8012_Reserved_6_6_WIDTH 1 -#define D0F0xE4_WRAP_8012_Reserved_6_6_MASK 0x40 -#define D0F0xE4_WRAP_8012_Pif1xIdleGateEnable_OFFSET 7 -#define D0F0xE4_WRAP_8012_Pif1xIdleGateEnable_WIDTH 1 -#define D0F0xE4_WRAP_8012_Pif1xIdleGateEnable_MASK 0x80 -#define D0F0xE4_WRAP_8012_Pif1xIdleResumeLatency_OFFSET 8 -#define D0F0xE4_WRAP_8012_Pif1xIdleResumeLatency_WIDTH 6 -#define D0F0xE4_WRAP_8012_Pif1xIdleResumeLatency_MASK 0x3f00 -#define D0F0xE4_WRAP_8012_Reserved_15_14_OFFSET 14 -#define D0F0xE4_WRAP_8012_Reserved_15_14_WIDTH 2 -#define D0F0xE4_WRAP_8012_Reserved_15_14_MASK 0xc000 -#define D0F0xE4_WRAP_8012_Pif2p5xIdleGateLatency_OFFSET 16 -#define D0F0xE4_WRAP_8012_Pif2p5xIdleGateLatency_WIDTH 6 -#define D0F0xE4_WRAP_8012_Pif2p5xIdleGateLatency_MASK 0x3f0000 -#define D0F0xE4_WRAP_8012_Reserved_22_22_OFFSET 22 -#define D0F0xE4_WRAP_8012_Reserved_22_22_WIDTH 1 -#define D0F0xE4_WRAP_8012_Reserved_22_22_MASK 0x400000 -#define D0F0xE4_WRAP_8012_Pif2p5xIdleGateEnable_OFFSET 23 -#define D0F0xE4_WRAP_8012_Pif2p5xIdleGateEnable_WIDTH 1 -#define D0F0xE4_WRAP_8012_Pif2p5xIdleGateEnable_MASK 0x800000 -#define D0F0xE4_WRAP_8012_Pif2p5xIdleResumeLatency_OFFSET 24 -#define D0F0xE4_WRAP_8012_Pif2p5xIdleResumeLatency_WIDTH 6 -#define D0F0xE4_WRAP_8012_Pif2p5xIdleResumeLatency_MASK 0x3f000000 -#define D0F0xE4_WRAP_8012_Reserved_31_30_OFFSET 30 -#define D0F0xE4_WRAP_8012_Reserved_31_30_WIDTH 2 -#define D0F0xE4_WRAP_8012_Reserved_31_30_MASK 0xc0000000 - -/// D0F0xE4_WRAP_8012 -typedef union { - struct { ///< - UINT32 Pif1xIdleGateLatency:6 ; ///< - UINT32 Reserved_6_6:1 ; ///< - UINT32 Pif1xIdleGateEnable:1 ; ///< - UINT32 Pif1xIdleResumeLatency:6 ; ///< - UINT32 Reserved_15_14:2 ; ///< - UINT32 Pif2p5xIdleGateLatency:6 ; ///< - UINT32 Reserved_22_22:1 ; ///< - UINT32 Pif2p5xIdleGateEnable:1 ; ///< - UINT32 Pif2p5xIdleResumeLatency:6 ; ///< - UINT32 Reserved_31_30:2 ; ///< - } Field; ///< - UINT32 Value; ///< -} D0F0xE4_WRAP_8012_STRUCT; - -// **** D0F0xE4_WRAP_8011 Register Definition **** -// Address -#define D0F0xE4_WRAP_8011_ADDRESS 0x8011 - -// Type -#define D0F0xE4_WRAP_8011_TYPE TYPE_D0F0xE4 -// Field Data -#define D0F0xE4_WRAP_8011_TxclkDynGateLatency_OFFSET 0 -#define D0F0xE4_WRAP_8011_TxclkDynGateLatency_WIDTH 6 -#define D0F0xE4_WRAP_8011_TxclkDynGateLatency_MASK 0x3f -#define D0F0xE4_WRAP_8011_TxclkPermGateEven_OFFSET 6 -#define D0F0xE4_WRAP_8011_TxclkPermGateEven_WIDTH 1 -#define D0F0xE4_WRAP_8011_TxclkPermGateEven_MASK 0x40 -#define D0F0xE4_WRAP_8011_TxclkDynGateEnable_OFFSET 7 -#define D0F0xE4_WRAP_8011_TxclkDynGateEnable_WIDTH 1 -#define D0F0xE4_WRAP_8011_TxclkDynGateEnable_MASK 0x80 -#define D0F0xE4_WRAP_8011_Reserved_8_8_OFFSET 8 -#define D0F0xE4_WRAP_8011_Reserved_8_8_WIDTH 1 -#define D0F0xE4_WRAP_8011_Reserved_8_8_MASK 0x100 -#define D0F0xE4_WRAP_8011_TxclkRegsGateEnable_OFFSET 9 -#define D0F0xE4_WRAP_8011_TxclkRegsGateEnable_WIDTH 1 -#define D0F0xE4_WRAP_8011_TxclkRegsGateEnable_MASK 0x200 -#define D0F0xE4_WRAP_8011_TxclkRegsGateLatency_OFFSET 10 -#define D0F0xE4_WRAP_8011_TxclkRegsGateLatency_WIDTH 6 -#define D0F0xE4_WRAP_8011_TxclkRegsGateLatency_MASK 0xfc00 -#define D0F0xE4_WRAP_8011_RcvrDetClkEnable_OFFSET 16 -#define D0F0xE4_WRAP_8011_RcvrDetClkEnable_WIDTH 1 -#define D0F0xE4_WRAP_8011_RcvrDetClkEnable_MASK 0x10000 -#define D0F0xE4_WRAP_8011_TxclkPermGateLatency_OFFSET 17 -#define D0F0xE4_WRAP_8011_TxclkPermGateLatency_WIDTH 6 -#define D0F0xE4_WRAP_8011_TxclkPermGateLatency_MASK 0x7e0000 -#define D0F0xE4_WRAP_8011_Reserved_23_23_OFFSET 23 -#define D0F0xE4_WRAP_8011_Reserved_23_23_WIDTH 1 -#define D0F0xE4_WRAP_8011_Reserved_23_23_MASK 0x800000 -#define D0F0xE4_WRAP_8011_TxclkLcntGateEnable_OFFSET 24 -#define D0F0xE4_WRAP_8011_TxclkLcntGateEnable_WIDTH 1 -#define D0F0xE4_WRAP_8011_TxclkLcntGateEnable_MASK 0x1000000 -#define D0F0xE4_WRAP_8011_Reserved_31_25_OFFSET 25 -#define D0F0xE4_WRAP_8011_Reserved_31_25_WIDTH 7 -#define D0F0xE4_WRAP_8011_Reserved_31_25_MASK 0xfe000000 - -/// D0F0xE4_WRAP_8011 -typedef union { - struct { ///< - UINT32 TxclkDynGateLatency:6 ; ///< - UINT32 TxclkPermGateEven:1 ; ///< - UINT32 TxclkDynGateEnable:1 ; ///< - UINT32 Reserved_8_8:1 ; ///< - UINT32 TxclkRegsGateEnable:1 ; ///< - UINT32 TxclkRegsGateLatency:6 ; ///< - UINT32 RcvrDetClkEnable:1 ; ///< - UINT32 TxclkPermGateLatency:6 ; ///< - UINT32 Reserved_23_23:1 ; ///< - UINT32 TxclkLcntGateEnable:1 ; ///< - UINT32 Reserved_31_25:7 ; ///< - } Field; ///< - UINT32 Value; ///< -} D0F0xE4_WRAP_8011_STRUCT; - -// **** D0F0xE4_WRAP_8016 Register Definition **** -// Address -#define D0F0xE4_WRAP_8016_ADDRESS 0x8016 - -// Type -#define D0F0xE4_WRAP_8016_TYPE TYPE_D0F0xE4 -// Field Data -#define D0F0xE4_WRAP_8016_CalibAckLatency_OFFSET 0 -#define D0F0xE4_WRAP_8016_CalibAckLatency_WIDTH 6 -#define D0F0xE4_WRAP_8016_CalibAckLatency_MASK 0x3f -#define D0F0xE4_WRAP_8016_Reserved_21_6_OFFSET 6 -#define D0F0xE4_WRAP_8016_Reserved_21_6_WIDTH 16 -#define D0F0xE4_WRAP_8016_Reserved_21_6_MASK 0x3fffc0 -#define D0F0xE4_WRAP_8016_LclkGateFree_OFFSET 22 -#define D0F0xE4_WRAP_8016_LclkGateFree_WIDTH 1 -#define D0F0xE4_WRAP_8016_LclkGateFree_MASK 0x400000 -#define D0F0xE4_WRAP_8016_LclkDynGateEnable_OFFSET 23 -#define D0F0xE4_WRAP_8016_LclkDynGateEnable_WIDTH 1 -#define D0F0xE4_WRAP_8016_LclkDynGateEnable_MASK 0x800000 -#define D0F0xE4_WRAP_8016_Reserved_31_24_OFFSET 24 -#define D0F0xE4_WRAP_8016_Reserved_31_24_WIDTH 8 -#define D0F0xE4_WRAP_8016_Reserved_31_24_MASK 0xff000000 - -/// D0F0xE4_WRAP_8016 -typedef union { - struct { ///< - UINT32 CalibAckLatency:6 ; ///< - UINT32 Reserved_21_6:16; ///< - UINT32 LclkGateFree:1 ; ///< - UINT32 LclkDynGateEnable:1 ; ///< - UINT32 Reserved_31_24:8 ; ///< - } Field; ///< - UINT32 Value; ///< -} D0F0xE4_WRAP_8016_STRUCT; - -// **** D18F6x110 Register Definition **** -// Address -#define D18F6x110_ADDRESS 0x110 - -// Type -#define D18F6x110_TYPE TYPE_D18F6 -// Field Data -#define D18F6x110_NclkFifoOff_OFFSET 0 -#define D18F6x110_NclkFifoOff_WIDTH 3 -#define D18F6x110_NclkFifoOff_MASK 0x7 -#define D18F6x110_Reserved_3_3_OFFSET 3 -#define D18F6x110_Reserved_3_3_WIDTH 1 -#define D18F6x110_Reserved_3_3_MASK 0x8 -#define D18F6x110_LclkFifoOff_OFFSET 4 -#define D18F6x110_LclkFifoOff_WIDTH 3 -#define D18F6x110_LclkFifoOff_MASK 0x70 -#define D18F6x110_Reserved_7_7_OFFSET 7 -#define D18F6x110_Reserved_7_7_WIDTH 1 -#define D18F6x110_Reserved_7_7_MASK 0x80 -#define D18F6x110_PllMult_OFFSET 8 -#define D18F6x110_PllMult_WIDTH 6 -#define D18F6x110_PllMult_MASK 0x3f00 -#define D18F6x110_Reserved_14_14_OFFSET 14 -#define D18F6x110_Reserved_14_14_WIDTH 1 -#define D18F6x110_Reserved_14_14_MASK 0x4000 -#define D18F6x110_Enable_OFFSET 15 -#define D18F6x110_Enable_WIDTH 1 -#define D18F6x110_Enable_MASK 0x8000 -#define D18F6x110_LclkFreq_OFFSET 16 -#define D18F6x110_LclkFreq_WIDTH 7 -#define D18F6x110_LclkFreq_MASK 0x7f0000 -#define D18F6x110_LclkFreqType_OFFSET 23 -#define D18F6x110_LclkFreqType_WIDTH 1 -#define D18F6x110_LclkFreqType_MASK 0x800000 -#define D18F6x110_NclkFreq_OFFSET 24 -#define D18F6x110_NclkFreq_WIDTH 7 -#define D18F6x110_NclkFreq_MASK 0x7f000000 -#define D18F6x110_NclkFreqType_OFFSET 31 -#define D18F6x110_NclkFreqType_WIDTH 1 -#define D18F6x110_NclkFreqType_MASK 0x80000000 - -/// D18F6x110 -typedef union { - struct { ///< - UINT32 NclkFifoOff:3 ; ///< - UINT32 Reserved_3_3:1 ; ///< - UINT32 LclkFifoOff:3 ; ///< - UINT32 Reserved_7_7:1 ; ///< - UINT32 PllMult:6 ; ///< - UINT32 Reserved_14_14:1 ; ///< - UINT32 Enable:1 ; ///< - UINT32 LclkFreq:7 ; ///< - UINT32 LclkFreqType:1 ; ///< - UINT32 NclkFreq:7 ; ///< - UINT32 NclkFreqType:1 ; ///< - } Field; ///< - UINT32 Value; ///< -} D18F6x110_STRUCT; - -// **** D18F3xA0 Register Definition **** -// Address -#define D18F3xA0_ADDRESS 0xa0 - -// Type -#define D18F3xA0_TYPE TYPE_D18F3 -// Field Data -#define D18F3xA0_PsiVid_OFFSET 0 -#define D18F3xA0_PsiVid_WIDTH 7 -#define D18F3xA0_PsiVid_MASK 0x7f -#define D18F3xA0_PsiVidEn_OFFSET 7 -#define D18F3xA0_PsiVidEn_WIDTH 1 -#define D18F3xA0_PsiVidEn_MASK 0x80 -#define D18F3xA0_Reserved_8_8_OFFSET 8 -#define D18F3xA0_Reserved_8_8_WIDTH 1 -#define D18F3xA0_Reserved_8_8_MASK 0x100 -#define D18F3xA0_SviHighFreqSel_OFFSET 9 -#define D18F3xA0_SviHighFreqSel_WIDTH 1 -#define D18F3xA0_SviHighFreqSel_MASK 0x200 -#define D18F3xA0_Reserved_15_10_OFFSET 10 -#define D18F3xA0_Reserved_15_10_WIDTH 6 -#define D18F3xA0_Reserved_15_10_MASK 0xfc00 -#define D18F3xA0_ConfigId_OFFSET 16 -#define D18F3xA0_ConfigId_WIDTH 12 -#define D18F3xA0_ConfigId_MASK 0xfff0000 -#define D18F3xA0_Reserved_30_28_OFFSET 28 -#define D18F3xA0_Reserved_30_28_WIDTH 3 -#define D18F3xA0_Reserved_30_28_MASK 0x70000000 -#define D18F3xA0_CofVidProg_OFFSET 31 -#define D18F3xA0_CofVidProg_WIDTH 1 -#define D18F3xA0_CofVidProg_MASK 0x80000000 - -/// D18F3xA0 -typedef union { - struct { ///< - UINT32 PsiVid:7 ; ///< - UINT32 PsiVidEn:1 ; ///< - UINT32 Reserved_8_8:1 ; ///< - UINT32 SviHighFreqSel:1 ; ///< - UINT32 Reserved_15_10:6 ; ///< - UINT32 ConfigId:12; ///< - UINT32 Reserved_30_28:3 ; ///< - UINT32 CofVidProg:1 ; ///< - } Field; ///< - UINT32 Value; ///< -} D18F3xA0_STRUCT; - -// **** FCRxFF30_0398 Register Definition **** +// **** SMUx0B_x848C Register Definition **** // Address -#define FCRxFF30_0398_ADDRESS 0xff300398 +#define SMUx0B_x848C_ADDRESS 0x848c // Type -#define FCRxFF30_0398_TYPE TYPE_FCR -// Field Data -#define FCRxFF30_0398_Reserved_4_0_OFFSET 0 -#define FCRxFF30_0398_Reserved_4_0_WIDTH 5 -#define FCRxFF30_0398_Reserved_4_0_MASK 0x1f -#define FCRxFF30_0398_SoftResetDc_OFFSET 5 -#define FCRxFF30_0398_SoftResetDc_WIDTH 1 -#define FCRxFF30_0398_SoftResetDc_MASK 0x20 -#define FCRxFF30_0398_Reserved_6_6_OFFSET 6 -#define FCRxFF30_0398_Reserved_6_6_WIDTH 1 -#define FCRxFF30_0398_Reserved_6_6_MASK 0x40 -#define FCRxFF30_0398_SoftResetGrbm_OFFSET 8 -#define FCRxFF30_0398_SoftResetGrbm_WIDTH 1 -#define FCRxFF30_0398_SoftResetGrbm_MASK 0x100 -#define FCRxFF30_0398_SoftResetMc_OFFSET 11 -#define FCRxFF30_0398_SoftResetMc_WIDTH 1 -#define FCRxFF30_0398_SoftResetMc_MASK 0x800 -#define FCRxFF30_0398_Reserved_12_12_OFFSET 12 -#define FCRxFF30_0398_Reserved_12_12_WIDTH 1 -#define FCRxFF30_0398_Reserved_12_12_MASK 0x1000 -#define FCRxFF30_0398_SoftResetRlc_OFFSET 13 -#define FCRxFF30_0398_SoftResetRlc_WIDTH 1 -#define FCRxFF30_0398_SoftResetRlc_MASK 0x2000 -#define FCRxFF30_0398_Reserved_16_16_OFFSET 16 -#define FCRxFF30_0398_Reserved_16_16_WIDTH 1 -#define FCRxFF30_0398_Reserved_16_16_MASK 0x10000 -#define FCRxFF30_0398_SoftResetUvd_OFFSET 18 -#define FCRxFF30_0398_SoftResetUvd_WIDTH 1 -#define FCRxFF30_0398_SoftResetUvd_MASK 0x40000 -#define FCRxFF30_0398_Reserved_31_19_OFFSET 19 -#define FCRxFF30_0398_Reserved_31_19_WIDTH 13 -#define FCRxFF30_0398_Reserved_31_19_MASK 0xfff80000 - -/// FCRxFF30_0398 -typedef union { - struct { ///< - UINT32 Reserved_4_0:5 ; ///< - UINT32 SoftResetDc:1 ; ///< - UINT32 Reserved_6_6:1 ; ///< +#define SMUx0B_x848C_TYPE TYPE_SMUx0B +// Field Data +#define SMUx0B_x848C_FstateDiv_7_OFFSET 0 +#define SMUx0B_x848C_FstateDiv_7_WIDTH 7 +#define SMUx0B_x848C_FstateDiv_7_MASK 0x7f +#define SMUx0B_x848C_Reserved_7_7_OFFSET 7 +#define SMUx0B_x848C_Reserved_7_7_WIDTH 1 +#define SMUx0B_x848C_Reserved_7_7_MASK 0x80 +#define SMUx0B_x848C_FstateDiv_6_OFFSET 8 +#define SMUx0B_x848C_FstateDiv_6_WIDTH 7 +#define SMUx0B_x848C_FstateDiv_6_MASK 0x7f00 +#define SMUx0B_x848C_Reserved_15_15_OFFSET 15 +#define SMUx0B_x848C_Reserved_15_15_WIDTH 1 +#define SMUx0B_x848C_Reserved_15_15_MASK 0x8000 +#define SMUx0B_x848C_FstateDiv_5_OFFSET 16 +#define SMUx0B_x848C_FstateDiv_5_WIDTH 7 +#define SMUx0B_x848C_FstateDiv_5_MASK 0x7f0000 +#define SMUx0B_x848C_Reserved_23_23_OFFSET 23 +#define SMUx0B_x848C_Reserved_23_23_WIDTH 1 +#define SMUx0B_x848C_Reserved_23_23_MASK 0x800000 +#define SMUx0B_x848C_FstateDiv_4_OFFSET 24 +#define SMUx0B_x848C_FstateDiv_4_WIDTH 7 +#define SMUx0B_x848C_FstateDiv_4_MASK 0x7f000000 +#define SMUx0B_x848C_Reserved_31_31_OFFSET 31 +#define SMUx0B_x848C_Reserved_31_31_WIDTH 1 +#define SMUx0B_x848C_Reserved_31_31_MASK 0x80000000 + +/// SMUx0B_x848C +typedef union { + struct { ///< + UINT32 FstateDiv_7:7 ; ///< UINT32 Reserved_7_7:1 ; ///< - UINT32 SoftResetGrbm:1 ; ///< - UINT32 Reserved_9_9:1 ; ///< - UINT32 Reserved_10_10:1 ; ///< - UINT32 SoftResetMc:1 ; ///< - UINT32 Reserved_12_12:1 ; ///< - UINT32 SoftResetRlc:1 ; ///< - UINT32 Reserved_14_14:1 ; ///< + UINT32 FstateDiv_6:7 ; ///< UINT32 Reserved_15_15:1 ; ///< - UINT32 Reserved_16_16:1 ; ///< - UINT32 Reserved_17_17:1 ; ///< - UINT32 SoftResetUvd:1 ; ///< - UINT32 Reserved_31_19:13; ///< + UINT32 FstateDiv_5:7 ; ///< + UINT32 Reserved_23_23:1 ; ///< + UINT32 FstateDiv_4:7 ; ///< + UINT32 Reserved_31_31:1 ; ///< } Field; ///< UINT32 Value; ///< -} FCRxFF30_0398_STRUCT; +} SMUx0B_x848C_STRUCT; -// **** SMUx0B_x8504 Register Definition **** +// **** SMUx0B_x8470 Register Definition **** // Address -#define SMUx0B_x8504_ADDRESS 0x8504 +#define SMUx0B_x8470_ADDRESS 0x8470 // Type -#define SMUx0B_x8504_TYPE TYPE_SMUx0B +#define SMUx0B_x8470_TYPE TYPE_SMUx0B // Field Data -#define SMUx0B_x8504_SaveRestoreWidth_OFFSET 0 -#define SMUx0B_x8504_SaveRestoreWidth_WIDTH 8 -#define SMUx0B_x8504_SaveRestoreWidth_MASK 0xff -#define SMUx0B_x8504_PsoRestoreTimer_OFFSET 8 -#define SMUx0B_x8504_PsoRestoreTimer_WIDTH 8 -#define SMUx0B_x8504_PsoRestoreTimer_MASK 0xff00 -#define SMUx0B_x8504_Reserved_31_16_OFFSET 16 -#define SMUx0B_x8504_Reserved_31_16_WIDTH 16 -#define SMUx0B_x8504_Reserved_31_16_MASK 0xffff0000 +#define SMUx0B_x8470_Raising_OFFSET 0 +#define SMUx0B_x8470_Raising_WIDTH 16 +#define SMUx0B_x8470_Raising_MASK 0xffff +#define SMUx0B_x8470_Lowering_OFFSET 16 +#define SMUx0B_x8470_Lowering_WIDTH 16 +#define SMUx0B_x8470_Lowering_MASK 0xffff0000 -/// SMUx0B_x8504 +/// SMUx0B_x8470 typedef union { struct { ///< - UINT32 SaveRestoreWidth:8 ; ///< - UINT32 PsoRestoreTimer:8 ; ///< - UINT32 Reserved_31_16:16; ///< + UINT32 Raising:16; ///< + UINT32 Lowering:16; ///< } Field; ///< UINT32 Value; ///< -} SMUx0B_x8504_STRUCT; - -// **** SMUx0B_x8408 Register Definition **** -// Address -#define SMUx0B_x8408_ADDRESS 0x8408 - +} SMUx0B_x8470_STRUCT; -// **** SMUx0B_x8410 Register Definition **** +// **** SMUx0B_x8440 Register Definition **** // Address -#define SMUx0B_x8410_ADDRESS 0x8410 +#define SMUx0B_x8440_ADDRESS 0x8440 // Type -#define SMUx0B_x8410_TYPE TYPE_SMUx0B +#define SMUx0B_x8440_TYPE TYPE_SMUx0B // Field Data -#define SMUx0B_x8410_PwrGatingEn_OFFSET 0 -#define SMUx0B_x8410_PwrGatingEn_WIDTH 1 -#define SMUx0B_x8410_PwrGatingEn_MASK 0x1 -#define SMUx0B_x8410_Reserved_2_1_OFFSET 1 -#define SMUx0B_x8410_Reserved_2_1_WIDTH 2 -#define SMUx0B_x8410_Reserved_2_1_MASK 0x6 -#define SMUx0B_x8410_PsoControlValidNum_OFFSET 3 -#define SMUx0B_x8410_PsoControlValidNum_WIDTH 5 -#define SMUx0B_x8410_PsoControlValidNum_MASK 0xf8 -#define SMUx0B_x8410_SavePsoDelay_OFFSET 8 -#define SMUx0B_x8410_SavePsoDelay_WIDTH 4 -#define SMUx0B_x8410_SavePsoDelay_MASK 0xf00 -#define SMUx0B_x8410_Reserved_27_12_OFFSET 12 -#define SMUx0B_x8410_Reserved_27_12_WIDTH 16 -#define SMUx0B_x8410_Reserved_27_12_MASK 0xffff000 -#define SMUx0B_x8410_PwrGaterSel_OFFSET 28 -#define SMUx0B_x8410_PwrGaterSel_WIDTH 4 -#define SMUx0B_x8410_PwrGaterSel_MASK 0xf0000000 +#define SMUx0B_x8440_FstatePeriod_5_OFFSET 0 +#define SMUx0B_x8440_FstatePeriod_5_WIDTH 16 +#define SMUx0B_x8440_FstatePeriod_5_MASK 0xffff +#define SMUx0B_x8440_FstatePeriod_4_OFFSET 16 +#define SMUx0B_x8440_FstatePeriod_4_WIDTH 16 +#define SMUx0B_x8440_FstatePeriod_4_MASK 0xffff0000 -/// SMUx0B_x8410 +/// SMUx0B_x8440 typedef union { struct { ///< - UINT32 PwrGatingEn:1 ; ///< - UINT32 Reserved_2_1:2 ; ///< - UINT32 PsoControlValidNum:5 ; ///< - UINT32 SavePsoDelay:4 ; ///< - UINT32 Reserved_27_12:16; ///< - UINT32 PwrGaterSel:4 ; ///< + UINT32 FstatePeriod_5:16; ///< + UINT32 FstatePeriod_4:16; ///< } Field; ///< UINT32 Value; ///< -} SMUx0B_x8410_STRUCT; +} SMUx0B_x8440_STRUCT; -// **** SMUx0B_x84A0 Register Definition **** -// Address -#define SMUx0B_x84A0_ADDRESS 0x84a0 - -// **** D0F0xE4_CORE_0020 Register Definition **** -// Address -#define D0F0xE4_CORE_0020_ADDRESS 0x20 - -// Type -#define D0F0xE4_CORE_0020_TYPE TYPE_D0F0xE4 -// Field Data -#define D0F0xE4_CORE_0020_Reserved_8_0_OFFSET 0 -#define D0F0xE4_CORE_0020_Reserved_8_0_WIDTH 9 -#define D0F0xE4_CORE_0020_Reserved_8_0_MASK 0x1ff -#define D0F0xE4_CORE_0020_CiSlvOrderingDis_OFFSET 8 -#define D0F0xE4_CORE_0020_CiSlvOrderingDis_WIDTH 1 -#define D0F0xE4_CORE_0020_CiSlvOrderingDis_MASK 0x100 -#define D0F0xE4_CORE_0020_CiRcOrderingDis_OFFSET 9 -#define D0F0xE4_CORE_0020_CiRcOrderingDis_WIDTH 1 -#define D0F0xE4_CORE_0020_CiRcOrderingDis_MASK 0x200 -#define D0F0xE4_CORE_0020_Reserved_31_10_OFFSET 10 -#define D0F0xE4_CORE_0020_Reserved_31_10_WIDTH 22 -#define D0F0xE4_CORE_0020_Reserved_31_10_MASK 0xfffffc00 - -/// D0F0xE4_CORE_0020 -typedef union { - struct { ///< - UINT32 Reserved_8_0:9 ; ///< - UINT32 CiRcOrderingDis:1 ; ///< - UINT32 Reserved_31_10:22; ///< - } Field; ///< - UINT32 Value; ///< -} D0F0xE4_CORE_0020_STRUCT; - -// **** D0F0xE4_CORE_00B0 Register Definition **** -// Address -#define D0F0xE4_CORE_00B0_ADDRESS 0xb0 - -// Type -#define D0F0xE4_CORE_00B0_TYPE TYPE_D0F0xE4 -// Field Data -#define D0F0xE4_CORE_00B0_Reserved_1_0_OFFSET 0 -#define D0F0xE4_CORE_00B0_Reserved_1_0_WIDTH 2 -#define D0F0xE4_CORE_00B0_Reserved_1_0_MASK 0x3 -#define D0F0xE4_CORE_00B0_StrapF0MsiEn_OFFSET 2 -#define D0F0xE4_CORE_00B0_StrapF0MsiEn_WIDTH 1 -#define D0F0xE4_CORE_00B0_StrapF0MsiEn_MASK 0x4 -#define D0F0xE4_CORE_00B0_Reserved_31_3_OFFSET 3 -#define D0F0xE4_CORE_00B0_Reserved_31_3_WIDTH 29 -#define D0F0xE4_CORE_00B0_Reserved_31_3_MASK 0xfffffff8 - -/// D0F0xE4_CORE_00B0 -typedef union { - struct { ///< - UINT32 Reserved_1_0:2 ; ///< - UINT32 StrapF0MsiEn:1 ; ///< - UINT32 Reserved_31_3:29; ///< - } Field; ///< - UINT32 Value; ///< -} D0F0xE4_CORE_00B0_STRUCT; - -// **** D0F0x64_x1C Register Definition **** -// Address -#define D0F0x64_x1C_ADDRESS 0x1c - -// Type -#define D0F0x64_x1C_TYPE TYPE_D0F0x64 -// Field Data -#define D0F0x64_x1C_WriteDis_OFFSET 0 -#define D0F0x64_x1C_WriteDis_WIDTH 1 -#define D0F0x64_x1C_WriteDis_MASK 0x1 -#define D0F0x64_x1C_F0NonlegacyDeviceTypeEn_OFFSET 1 -#define D0F0x64_x1C_F0NonlegacyDeviceTypeEn_WIDTH 1 -#define D0F0x64_x1C_F0NonlegacyDeviceTypeEn_MASK 0x2 -#define D0F0x64_x1C_Reserved_2_2_OFFSET 2 -#define D0F0x64_x1C_Reserved_2_2_WIDTH 1 -#define D0F0x64_x1C_Reserved_2_2_MASK 0x4 -#define D0F0x64_x1C_MemApSize_OFFSET 3 -#define D0F0x64_x1C_MemApSize_WIDTH 3 -#define D0F0x64_x1C_MemApSize_MASK 0x38 -#define D0F0x64_x1C_RegApSize_OFFSET 6 -#define D0F0x64_x1C_RegApSize_WIDTH 1 -#define D0F0x64_x1C_RegApSize_MASK 0x40 -#define D0F0x64_x1C_Reserved_7_7_OFFSET 7 -#define D0F0x64_x1C_Reserved_7_7_WIDTH 1 -#define D0F0x64_x1C_Reserved_7_7_MASK 0x80 -#define D0F0x64_x1C_AudioEn_OFFSET 8 -#define D0F0x64_x1C_AudioEn_WIDTH 1 -#define D0F0x64_x1C_AudioEn_MASK 0x100 -#define D0F0x64_x1C_Reserved_9_9_OFFSET 9 -#define D0F0x64_x1C_Reserved_9_9_WIDTH 1 -#define D0F0x64_x1C_Reserved_9_9_MASK 0x200 -#define D0F0x64_x1C_AudioNonlegacyDeviceTypeEn_OFFSET 10 -#define D0F0x64_x1C_AudioNonlegacyDeviceTypeEn_WIDTH 1 -#define D0F0x64_x1C_AudioNonlegacyDeviceTypeEn_MASK 0x400 -#define D0F0x64_x1C_Reserved_16_11_OFFSET 11 -#define D0F0x64_x1C_Reserved_16_11_WIDTH 6 -#define D0F0x64_x1C_Reserved_16_11_MASK 0x1f800 -#define D0F0x64_x1C_F0En_OFFSET 17 -#define D0F0x64_x1C_F0En_WIDTH 1 -#define D0F0x64_x1C_F0En_MASK 0x20000 -#define D0F0x64_x1C_Reserved_22_18_OFFSET 18 -#define D0F0x64_x1C_Reserved_22_18_WIDTH 5 -#define D0F0x64_x1C_Reserved_22_18_MASK 0x7c0000 -#define D0F0x64_x1C_RcieEn_OFFSET 23 -#define D0F0x64_x1C_RcieEn_WIDTH 1 -#define D0F0x64_x1C_RcieEn_MASK 0x800000 -#define D0F0x64_x1C_Reserved_31_24_OFFSET 24 -#define D0F0x64_x1C_Reserved_31_24_WIDTH 8 -#define D0F0x64_x1C_Reserved_31_24_MASK 0xff000000 - -/// D0F0x64_x1C -typedef union { - struct { ///< - UINT32 WriteDis:1 ; ///< - UINT32 F0NonlegacyDeviceTypeEn:1 ; ///< - UINT32 Reserved_2_2:1 ; ///< - UINT32 MemApSize:3 ; ///< - UINT32 RegApSize:1 ; ///< - UINT32 Reserved_7_7:1 ; ///< - UINT32 AudioEn:1 ; ///< - UINT32 Reserved_9_9:1 ; ///< - UINT32 AudioNonlegacyDeviceTypeEn:1 ; ///< - UINT32 Reserved_16_11:6 ; ///< - UINT32 F0En:1 ; ///< - UINT32 Reserved_22_18:5 ; ///< - UINT32 RcieEn:1 ; ///< - UINT32 Reserved_31_24:8 ; ///< - } Field; ///< - UINT32 Value; ///< -} D0F0x64_x1C_STRUCT; - -// **** D18F2x0F4_x40 Register Definition **** -// Address -#define D18F2x0F4_x40_ADDRESS 0x40 - -// Type -#define D18F2x0F4_x40_TYPE TYPE_D18F2x0F4 -// Field Data -#define D18F2x0F4_x40_Trcd_OFFSET 0 -#define D18F2x0F4_x40_Trcd_WIDTH 4 -#define D18F2x0F4_x40_Trcd_MASK 0xf -#define D18F2x0F4_x40_Reserved_7_4_OFFSET 4 -#define D18F2x0F4_x40_Reserved_7_4_WIDTH 4 -#define D18F2x0F4_x40_Reserved_7_4_MASK 0xf0 -#define D18F2x0F4_x40_Trp_OFFSET 8 -#define D18F2x0F4_x40_Trp_WIDTH 4 -#define D18F2x0F4_x40_Trp_MASK 0xf00 -#define D18F2x0F4_x40_Reserved_15_12_OFFSET 12 -#define D18F2x0F4_x40_Reserved_15_12_WIDTH 4 -#define D18F2x0F4_x40_Reserved_15_12_MASK 0xf000 -#define D18F2x0F4_x40_Tras_OFFSET 16 -#define D18F2x0F4_x40_Tras_WIDTH 5 -#define D18F2x0F4_x40_Tras_MASK 0x1f0000 -#define D18F2x0F4_x40_Reserved_23_21_OFFSET 21 -#define D18F2x0F4_x40_Reserved_23_21_WIDTH 3 -#define D18F2x0F4_x40_Reserved_23_21_MASK 0xe00000 -#define D18F2x0F4_x40_Trc_OFFSET 24 -#define D18F2x0F4_x40_Trc_WIDTH 6 -#define D18F2x0F4_x40_Trc_MASK 0x3f000000 -#define D18F2x0F4_x40_Reserved_31_30_OFFSET 30 -#define D18F2x0F4_x40_Reserved_31_30_WIDTH 2 -#define D18F2x0F4_x40_Reserved_31_30_MASK 0xc0000000 - -/// D18F2x0F4_x40 -typedef union { - struct { ///< - UINT32 Trcd:4 ; ///< - UINT32 Reserved_7_4:4 ; ///< - UINT32 Trp:4 ; ///< - UINT32 Reserved_15_12:4 ; ///< - UINT32 Tras:5 ; ///< - UINT32 Reserved_23_21:3 ; ///< - UINT32 Trc:6 ; ///< - UINT32 Reserved_31_30:2 ; ///< - } Field; ///< - UINT32 Value; ///< -} D18F2x0F4_x40_STRUCT; - -// **** D18F2x0F4_x41 Register Definition **** +// **** SMUx51 Register Definition **** // Address -#define D18F2x0F4_x41_ADDRESS 0x41 +#define SMUx51_ADDRESS 0x51 // Type -#define D18F2x0F4_x41_TYPE TYPE_D18F2x0F4 +#define SMUx51_TYPE TYPE_SMU // Field Data -#define D18F2x0F4_x41_Trtp_OFFSET 0 -#define D18F2x0F4_x41_Trtp_WIDTH 3 -#define D18F2x0F4_x41_Trtp_MASK 0x7 -#define D18F2x0F4_x41_Reserved_7_3_OFFSET 3 -#define D18F2x0F4_x41_Reserved_7_3_WIDTH 5 -#define D18F2x0F4_x41_Reserved_7_3_MASK 0xf8 -#define D18F2x0F4_x41_Trrd_OFFSET 8 -#define D18F2x0F4_x41_Trrd_WIDTH 3 -#define D18F2x0F4_x41_Trrd_MASK 0x700 -#define D18F2x0F4_x41_Reserved_15_11_OFFSET 11 -#define D18F2x0F4_x41_Reserved_15_11_WIDTH 5 -#define D18F2x0F4_x41_Reserved_15_11_MASK 0xf800 -#define D18F2x0F4_x41_Twtr_OFFSET 16 -#define D18F2x0F4_x41_Twtr_WIDTH 3 -#define D18F2x0F4_x41_Twtr_MASK 0x70000 -#define D18F2x0F4_x41_Reserved_31_19_OFFSET 19 -#define D18F2x0F4_x41_Reserved_31_19_WIDTH 13 -#define D18F2x0F4_x41_Reserved_31_19_MASK 0xfff80000 - -/// D18F2x0F4_x41 -typedef union { - struct { ///< - UINT32 Trtp:3 ; ///< - UINT32 Reserved_7_3:5 ; ///< - UINT32 Trrd:3 ; ///< - UINT32 Reserved_15_11:5 ; ///< - UINT32 Twtr:3 ; ///< - UINT32 Reserved_31_19:13; ///< - } Field; ///< - UINT32 Value; ///< -} D18F2x0F4_x41_STRUCT; - -// **** D18F2x0F0 Register Definition **** -// Address -#define D18F2x0F0_ADDRESS 0xf0 - - -// **** D18F2x1F0 Register Definition **** -// Address -#define D18F2x1F0_ADDRESS 0x1f0 - +#define SMUx51_DownTrendCoef_OFFSET 0 +#define SMUx51_DownTrendCoef_WIDTH 10 +#define SMUx51_DownTrendCoef_MASK 0x3ff +#define SMUx51_UpTrendCoef_OFFSET 10 +#define SMUx51_UpTrendCoef_WIDTH 10 +#define SMUx51_UpTrendCoef_MASK 0xffc00 +#define SMUx51_Reserved_31_20_OFFSET 20 +#define SMUx51_Reserved_31_20_WIDTH 12 +#define SMUx51_Reserved_31_20_MASK 0xfff00000 -// **** D18F2x184 Register Definition **** -// Address -#define D18F2x184_ADDRESS 0x184 - - -// **** D18F2x094 Register Definition **** -// Address -#define D18F2x094_ADDRESS 0x94 - -// Type -#define D18F2x094_TYPE TYPE_D18F2 -// Field Data -#define D18F2x094_MemClkFreq_OFFSET 0 -#define D18F2x094_MemClkFreq_WIDTH 5 -#define D18F2x094_MemClkFreq_MASK 0x1f -#define D18F2x094_Reserved_6_5_OFFSET 5 -#define D18F2x094_Reserved_6_5_WIDTH 2 -#define D18F2x094_Reserved_6_5_MASK 0x60 -#define D18F2x094_MemClkFreqVal_OFFSET 7 -#define D18F2x094_MemClkFreqVal_WIDTH 1 -#define D18F2x094_MemClkFreqVal_MASK 0x80 -#define D18F2x094_Reserved_9_8_OFFSET 8 -#define D18F2x094_Reserved_9_8_WIDTH 2 -#define D18F2x094_Reserved_9_8_MASK 0x300 -#define D18F2x094_ZqcsInterval_OFFSET 10 -#define D18F2x094_ZqcsInterval_WIDTH 2 -#define D18F2x094_ZqcsInterval_MASK 0xc00 -#define D18F2x094_Reserved_13_12_OFFSET 12 -#define D18F2x094_Reserved_13_12_WIDTH 2 -#define D18F2x094_Reserved_13_12_MASK 0x3000 -#define D18F2x094_DisDramInterface_OFFSET 14 -#define D18F2x094_DisDramInterface_WIDTH 1 -#define D18F2x094_DisDramInterface_MASK 0x4000 -#define D18F2x094_PowerDownEn_OFFSET 15 -#define D18F2x094_PowerDownEn_WIDTH 1 -#define D18F2x094_PowerDownEn_MASK 0x8000 -#define D18F2x094_PowerDownMode_OFFSET 16 -#define D18F2x094_PowerDownMode_WIDTH 1 -#define D18F2x094_PowerDownMode_MASK 0x10000 -#define D18F2x094_Reserved_19_17_OFFSET 17 -#define D18F2x094_Reserved_19_17_WIDTH 3 -#define D18F2x094_Reserved_19_17_MASK 0xe0000 -#define D18F2x094_SlowAccessMode_OFFSET 20 -#define D18F2x094_SlowAccessMode_WIDTH 1 -#define D18F2x094_SlowAccessMode_MASK 0x100000 -#define D18F2x094_Reserved_21_21_OFFSET 21 -#define D18F2x094_Reserved_21_21_WIDTH 1 -#define D18F2x094_Reserved_21_21_MASK 0x200000 -#define D18F2x094_BankSwizzleMode_OFFSET 22 -#define D18F2x094_BankSwizzleMode_WIDTH 1 -#define D18F2x094_BankSwizzleMode_MASK 0x400000 -#define D18F2x094_ProcOdtDis_OFFSET 23 -#define D18F2x094_ProcOdtDis_WIDTH 1 -#define D18F2x094_ProcOdtDis_MASK 0x800000 -#define D18F2x094_DcqBypassMax_OFFSET 24 -#define D18F2x094_DcqBypassMax_WIDTH 4 -#define D18F2x094_DcqBypassMax_MASK 0xf000000 -#define D18F2x094_FourActWindow_OFFSET 28 -#define D18F2x094_FourActWindow_WIDTH 4 -#define D18F2x094_FourActWindow_MASK 0xf0000000 - -/// D18F2x094 +/// SMUx51 typedef union { struct { ///< - UINT32 MemClkFreq:5 ; ///< - UINT32 Reserved_6_5:2 ; ///< - UINT32 MemClkFreqVal:1 ; ///< - UINT32 Reserved_9_8:2 ; ///< - UINT32 ZqcsInterval:2 ; ///< - UINT32 Reserved_13_12:2 ; ///< - UINT32 DisDramInterface:1 ; ///< - UINT32 PowerDownEn:1 ; ///< - UINT32 PowerDownMode:1 ; ///< - UINT32 Reserved_19_17:3 ; ///< - UINT32 SlowAccessMode:1 ; ///< - UINT32 Reserved_21_21:1 ; ///< - UINT32 BankSwizzleMode:1 ; ///< - UINT32 ProcOdtDis:1 ; ///< - UINT32 DcqBypassMax:4 ; ///< - UINT32 FourActWindow:4 ; ///< + UINT32 DownTrendCoef:10; ///< + UINT32 UpTrendCoef:10; ///< + UINT32 Reserved_31_20:12; ///< } Field; ///< UINT32 Value; ///< -} D18F2x094_STRUCT; - -// **** D18F2x194 Register Definition **** -// Address -#define D18F2x194_ADDRESS 0x194 +} SMUx51_STRUCT; - -// **** D18F2x18C Register Definition **** -// Address -#define D18F2x18C_ADDRESS 0x18c - - -// **** D18F2x190 Register Definition **** -// Address -#define D18F2x190_ADDRESS 0x190 - - -// **** D18F2x098 Register Definition **** -// Address -#define D18F2x098_ADDRESS 0x98 - - -// **** D18F2x198 Register Definition **** -// Address -#define D18F2x198_ADDRESS 0x198 - - -// **** D18F2x09C_x0D0FE00A Register Definition **** +// **** FCRxFE00_70A2 Register Definition **** // Address -#define D18F2x09C_x0D0FE00A_ADDRESS 0x0D0FE00A +#define FCRxFE00_70A2_ADDRESS 0xfe0070a2 // Type -#define D18F2x09C_x0D0FE00A_TYPE TYPE_D18F2x9C +#define FCRxFE00_70A2_TYPE TYPE_FCR // Field Data -#define D18F2x09C_x0D0FE00A_Reserved_11_0_OFFSET 0 -#define D18F2x09C_x0D0FE00A_Reserved_11_0_WIDTH 12 -#define D18F2x09C_x0D0FE00A_Reserved_11_0_MASK 0xfff -#define D18F2x09C_x0D0FE00A_CsrPhySrPllPdMode_OFFSET 12 -#define D18F2x09C_x0D0FE00A_CsrPhySrPllPdMode_WIDTH 2 -#define D18F2x09C_x0D0FE00A_CsrPhySrPllPdMode_MASK 0x3000 -#define D18F2x09C_x0D0FE00A_SelCsrPllPdMode_OFFSET 14 -#define D18F2x09C_x0D0FE00A_SelCsrPllPdMode_WIDTH 1 -#define D18F2x09C_x0D0FE00A_SelCsrPllPdMode_MASK 0x4000 -#define D18F2x09C_x0D0FE00A_Reserved_31_15_OFFSET 15 -#define D18F2x09C_x0D0FE00A_Reserved_31_15_WIDTH 17 -#define D18F2x09C_x0D0FE00A_Reserved_31_15_MASK 0xFFFF8000 - -/// D18F2x09C_x0D0FE00A -typedef union { - struct { ///< - UINT32 Reserved_11_0:12; ///< - UINT32 CsrPhySrPllPdMode:2; ///< - UINT32 SelCsrPllPdMode:1; ///< - UINT32 Reserved_31_15:17; ///< - } Field; ///< - UINT32 Value; ///< -} D18F2x09C_x0D0FE00A_STRUCT; - -// **** GMMx201C Register Definition **** -// Address -#define GMMx201C_ADDRESS 0x201c - - -// **** GMMx217C Register Definition **** -// Address -#define GMMx217C_ADDRESS 0x217c - - -// **** GMMx2188 Register Definition **** -// Address -#define GMMx2188_ADDRESS 0x2188 - - -// **** GMMx28C8 Register Definition **** -// Address -#define GMMx28C8_ADDRESS 0x28c8 - - -// **** SMUx01 Register Definition **** -// Address -#define SMUx01_ADDRESS 0x1 +#define FCRxFE00_70A2_Reserved_6_0_OFFSET 0 +#define FCRxFE00_70A2_Reserved_6_0_WIDTH 7 +#define FCRxFE00_70A2_Reserved_6_0_MASK 0x7f +#define FCRxFE00_70A2_PPlayTableRev_OFFSET 7 +#define FCRxFE00_70A2_PPlayTableRev_WIDTH 4 +#define FCRxFE00_70A2_PPlayTableRev_MASK 0x780 +#define FCRxFE00_70A2_SclkThermDid_OFFSET 11 +#define FCRxFE00_70A2_SclkThermDid_WIDTH 7 +#define FCRxFE00_70A2_SclkThermDid_MASK 0x3f800 +#define FCRxFE00_70A2_PcieGen2Vid_OFFSET 18 +#define FCRxFE00_70A2_PcieGen2Vid_WIDTH 2 +#define FCRxFE00_70A2_PcieGen2Vid_MASK 0xc0000 +#define FCRxFE00_70A2_Reserved_31_20_OFFSET 20 +#define FCRxFE00_70A2_Reserved_31_20_WIDTH 12 +#define FCRxFE00_70A2_Reserved_31_20_MASK 0xfff00000 -// Type -#define SMUx01_TYPE TYPE_SMU -// Field Data -#define SMUx01_RamSwitch_OFFSET 0 -#define SMUx01_RamSwitch_WIDTH 1 -#define SMUx01_RamSwitch_MASK 0x1 -#define SMUx01_Reset_OFFSET 1 -#define SMUx01_Reset_WIDTH 1 -#define SMUx01_Reset_MASK 0x2 -#define SMUx01_Reserved_17_2_OFFSET 2 -#define SMUx01_Reserved_17_2_WIDTH 16 -#define SMUx01_Reserved_17_2_MASK 0x3fffc -#define SMUx01_VectorOverride_OFFSET 18 -#define SMUx01_VectorOverride_WIDTH 1 -#define SMUx01_VectorOverride_MASK 0x40000 -#define SMUx01_Reserved_31_19_OFFSET 19 -#define SMUx01_Reserved_31_19_WIDTH 13 -#define SMUx01_Reserved_31_19_MASK 0xfff80000 -// -/// SMUx01 +/// FCRxFE00_70A2 typedef union { struct { ///< - UINT32 RamSwitch:1 ; ///< - UINT32 Reset:1 ; ///< - UINT32 Reserved_17_2:16; ///< - UINT32 VectorOverride:1 ; ///< - UINT32 Reserved_31_19:13; ///< + UINT32 Reserved_6_0:7 ; ///< + UINT32 PPlayTableRev:4 ; ///< + UINT32 SclkThermDid:7 ; ///< + UINT32 PcieGen2Vid:2 ; ///< + UINT32 Reserved_31_20:12; ///< } Field; ///< UINT32 Value; ///< -} SMUx01_STRUCT; +} FCRxFE00_70A2_STRUCT; // **** FCRxFE00_70A4 Register Definition **** // Address @@ -11855,40 +14377,118 @@ typedef union { UINT32 Value; ///< } FCRxFE00_70C7_STRUCT; -// **** FCRxFE00_70A2 Register Definition **** +// **** SMUx0B_x8490 Register Definition **** // Address -#define FCRxFE00_70A2_ADDRESS 0xfe0070a2 +#define SMUx0B_x8490_ADDRESS 0x8490 // Type -#define FCRxFE00_70A2_TYPE TYPE_FCR +#define SMUx0B_x8490_TYPE TYPE_SMUx0B +// Field Data +#define SMUx0B_x8490_LclkState0Valid_OFFSET 0 +#define SMUx0B_x8490_LclkState0Valid_WIDTH 1 +#define SMUx0B_x8490_LclkState0Valid_MASK 0x1 +#define SMUx0B_x8490_LclkState1Valid_OFFSET 1 +#define SMUx0B_x8490_LclkState1Valid_WIDTH 1 +#define SMUx0B_x8490_LclkState1Valid_MASK 0x2 +#define SMUx0B_x8490_LclkState2Valid_OFFSET 2 +#define SMUx0B_x8490_LclkState2Valid_WIDTH 1 +#define SMUx0B_x8490_LclkState2Valid_MASK 0x4 +#define SMUx0B_x8490_LclkState3Valid_OFFSET 3 +#define SMUx0B_x8490_LclkState3Valid_WIDTH 1 +#define SMUx0B_x8490_LclkState3Valid_MASK 0x8 +#define SMUx0B_x8490_LclkState4Valid_OFFSET 4 +#define SMUx0B_x8490_LclkState4Valid_WIDTH 1 +#define SMUx0B_x8490_LclkState4Valid_MASK 0x10 +#define SMUx0B_x8490_LclkState5Valid_OFFSET 5 +#define SMUx0B_x8490_LclkState5Valid_WIDTH 1 +#define SMUx0B_x8490_LclkState5Valid_MASK 0x20 +#define SMUx0B_x8490_LclkState6Valid_OFFSET 6 +#define SMUx0B_x8490_LclkState6Valid_WIDTH 1 +#define SMUx0B_x8490_LclkState6Valid_MASK 0x40 +#define SMUx0B_x8490_LclkState7Valid_OFFSET 7 +#define SMUx0B_x8490_LclkState7Valid_WIDTH 1 +#define SMUx0B_x8490_LclkState7Valid_MASK 0x80 +#define SMUx0B_x8490_LclkDivTtExit_OFFSET 8 +#define SMUx0B_x8490_LclkDivTtExit_WIDTH 8 +#define SMUx0B_x8490_LclkDivTtExit_MASK 0xff00 +#define SMUx0B_x8490_MinDivAllowed_OFFSET 16 +#define SMUx0B_x8490_MinDivAllowed_WIDTH 8 +#define SMUx0B_x8490_MinDivAllowed_MASK 0xff0000 +#define SMUx0B_x8490_Reserved_31_24_OFFSET 24 +#define SMUx0B_x8490_Reserved_31_24_WIDTH 8 +#define SMUx0B_x8490_Reserved_31_24_MASK 0xff000000 + +/// SMUx0B_x8490 +typedef union { + struct { ///< + UINT32 LclkState0Valid:1 ; ///< + UINT32 LclkState1Valid:1 ; ///< + UINT32 LclkState2Valid:1 ; ///< + UINT32 LclkState3Valid:1 ; ///< + UINT32 LclkState4Valid:1 ; ///< + UINT32 LclkState5Valid:1 ; ///< + UINT32 LclkState6Valid:1 ; ///< + UINT32 LclkState7Valid:1 ; ///< + UINT32 LclkDivTtExit:8 ; ///< + UINT32 MinDivAllowed:8 ; ///< + UINT32 Reserved_31_24:8 ; ///< + } Field; ///< + UINT32 Value; ///< +} SMUx0B_x8490_STRUCT; + +// **** SMUx35 Register Definition **** +// Address +#define SMUx35_ADDRESS 0x35 + +// Type +#define SMUx35_TYPE TYPE_SMU // Field Data -#define FCRxFE00_70A2_Reserved_6_0_OFFSET 0 -#define FCRxFE00_70A2_Reserved_6_0_WIDTH 7 -#define FCRxFE00_70A2_Reserved_6_0_MASK 0x7f -#define FCRxFE00_70A2_PPlayTableRev_OFFSET 7 -#define FCRxFE00_70A2_PPlayTableRev_WIDTH 4 -#define FCRxFE00_70A2_PPlayTableRev_MASK 0x780 -#define FCRxFE00_70A2_SclkThermDid_OFFSET 11 -#define FCRxFE00_70A2_SclkThermDid_WIDTH 7 -#define FCRxFE00_70A2_SclkThermDid_MASK 0x3f800 -#define FCRxFE00_70A2_PcieGen2Vid_OFFSET 18 -#define FCRxFE00_70A2_PcieGen2Vid_WIDTH 2 -#define FCRxFE00_70A2_PcieGen2Vid_MASK 0xc0000 -#define FCRxFE00_70A2_Reserved_31_20_OFFSET 20 -#define FCRxFE00_70A2_Reserved_31_20_WIDTH 12 -#define FCRxFE00_70A2_Reserved_31_20_MASK 0xfff00000 +#define SMUx35_DownTrendCoef_OFFSET 0 +#define SMUx35_DownTrendCoef_WIDTH 10 +#define SMUx35_DownTrendCoef_MASK 0x3ff +#define SMUx35_UpTrendCoef_OFFSET 10 +#define SMUx35_UpTrendCoef_WIDTH 10 +#define SMUx35_UpTrendCoef_MASK 0xffc00 +#define SMUx35_Reserved_31_20_OFFSET 20 +#define SMUx35_Reserved_31_20_WIDTH 12 +#define SMUx35_Reserved_31_20_MASK 0xfff00000 -/// FCRxFE00_70A2 +/// SMUx35 typedef union { struct { ///< - UINT32 Reserved_6_0:7 ; ///< - UINT32 PPlayTableRev:4 ; ///< - UINT32 SclkThermDid:7 ; ///< - UINT32 PcieGen2Vid:2 ; ///< + UINT32 DownTrendCoef:10; ///< + UINT32 UpTrendCoef:10; ///< UINT32 Reserved_31_20:12; ///< } Field; ///< UINT32 Value; ///< -} FCRxFE00_70A2_STRUCT; +} SMUx35_STRUCT; + +// **** SMUx37 Register Definition **** +// Address +#define SMUx37_ADDRESS 0x37 + +// Type +#define SMUx37_TYPE TYPE_SMU +// Field Data +#define SMUx37_DownTrendCoef_OFFSET 0 +#define SMUx37_DownTrendCoef_WIDTH 10 +#define SMUx37_DownTrendCoef_MASK 0x3ff +#define SMUx37_UpTrendCoef_OFFSET 10 +#define SMUx37_UpTrendCoef_WIDTH 10 +#define SMUx37_UpTrendCoef_MASK 0xffc00 +#define SMUx37_Reserved_31_20_OFFSET 20 +#define SMUx37_Reserved_31_20_WIDTH 12 +#define SMUx37_Reserved_31_20_MASK 0xfff00000 + +/// SMUx37 +typedef union { + struct { ///< + UINT32 DownTrendCoef:10; ///< + UINT32 UpTrendCoef:10; ///< + UINT32 Reserved_31_20:12; ///< + } Field; ///< + UINT32 Value; ///< +} SMUx37_STRUCT; // **** FCRxFE00_70AA Register Definition **** // Address @@ -11917,509 +14517,731 @@ typedef union { UINT32 Value; ///< } FCRxFE00_70AA_STRUCT; -// **** D18F3xD4 Register Definition **** +// **** FCRxFE00_70C8 Register Definition **** // Address -#define D18F3xD4_ADDRESS 0xd4 +#define FCRxFE00_70C8_ADDRESS 0xfe0070c8 // Type -#define D18F3xD4_TYPE TYPE_D18F3 +#define FCRxFE00_70C8_TYPE TYPE_FCR // Field Data -#define D18F3xD4_MainPllOpFreqId_OFFSET 0 -#define D18F3xD4_MainPllOpFreqId_WIDTH 6 -#define D18F3xD4_MainPllOpFreqId_MASK 0x3f -#define D18F3xD4_MainPllOpFreqIdEn_OFFSET 6 -#define D18F3xD4_MainPllOpFreqIdEn_WIDTH 1 -#define D18F3xD4_MainPllOpFreqIdEn_MASK 0x40 -#define D18F3xD4_Reserved_7_7_OFFSET 7 -#define D18F3xD4_Reserved_7_7_WIDTH 1 -#define D18F3xD4_Reserved_7_7_MASK 0x80 -#define D18F3xD4_ClkRampHystSel_OFFSET 8 -#define D18F3xD4_ClkRampHystSel_WIDTH 4 -#define D18F3xD4_ClkRampHystSel_MASK 0xf00 -#define D18F3xD4_OnionOutHyst_OFFSET 12 -#define D18F3xD4_OnionOutHyst_WIDTH 4 -#define D18F3xD4_OnionOutHyst_MASK 0xf000 -#define D18F3xD4_DisNclkGatingIdle_OFFSET 16 -#define D18F3xD4_DisNclkGatingIdle_WIDTH 1 -#define D18F3xD4_DisNclkGatingIdle_MASK 0x10000 -#define D18F3xD4_ClockGatingEnDram_OFFSET 17 -#define D18F3xD4_ClockGatingEnDram_WIDTH 1 -#define D18F3xD4_ClockGatingEnDram_MASK 0x20000 -#define D18F3xD4_Reserved_31_18_OFFSET 18 -#define D18F3xD4_Reserved_31_18_WIDTH 14 -#define D18F3xD4_Reserved_31_18_MASK 0xfffc0000 +#define FCRxFE00_70C8_Reserved_4_0_OFFSET 0 +#define FCRxFE00_70C8_Reserved_4_0_WIDTH 5 +#define FCRxFE00_70C8_Reserved_4_0_MASK 0x1f +#define FCRxFE00_70C8_GpuBoostCap_OFFSET 5 +#define FCRxFE00_70C8_GpuBoostCap_WIDTH 1 +#define FCRxFE00_70C8_GpuBoostCap_MASK 0x20 +#define FCRxFE00_70C8_SclkDpmDid5_OFFSET 6 +#define FCRxFE00_70C8_SclkDpmDid5_WIDTH 7 +#define FCRxFE00_70C8_SclkDpmDid5_MASK 0x00001fc0 +#define FCRxFE00_70C8_SclkDpmVid5_OFFSET 13 +#define FCRxFE00_70C8_SclkDpmVid5_WIDTH 2 +#define FCRxFE00_70C8_SclkDpmVid5_MASK 0x00060000 +#define FCRxFE00_70C8_Reserved_31_15_OFFSET 15 +#define FCRxFE00_70C8_Reserved_31_15_WIDTH 17 +#define FCRxFE00_70C8_Reserved_31_15_MASK 0xffff8000 -/// D18F3xD4 +/// FCRxFE00_70C8 typedef union { struct { ///< - UINT32 MainPllOpFreqId:6 ; ///< - UINT32 MainPllOpFreqIdEn:1 ; ///< - UINT32 Reserved_7_7:1 ; ///< - UINT32 ClkRampHystSel:4 ; ///< - UINT32 OnionOutHyst:4 ; ///< - UINT32 DisNclkGatingIdle:1 ; ///< - UINT32 ClockGatingEnDram:1 ; ///< - UINT32 Reserved_31_18:14; ///< + UINT32 Reserved_4_0:5 ; ///< + UINT32 GpuBoostCap:1 ; ///< + UINT32 SclkDpmDid5:7 ; ///< + UINT32 SclkDpmVid5:2 ; ///< + UINT32 Reserved_31_15:17; ///< } Field; ///< UINT32 Value; ///< -} D18F3xD4_STRUCT; +} FCRxFE00_70C8_STRUCT; -// **** FCRxFF30_01F4 Register Definition **** +// **** FCRxFE00_70C9 Register Definition **** // Address -#define FCRxFF30_01F4_ADDRESS 0xff3001f4 +#define FCRxFE00_70C9_ADDRESS 0xfe0070c9 // Type -#define FCRxFF30_01F4_TYPE TYPE_FCR +#define FCRxFE00_70C9_TYPE TYPE_FCR // Field Data -#define FCRxFF30_01F4_ReservedCgttSclk_21_0_OFFSET 0 -#define FCRxFF30_01F4_ReservedCgttSclk_21_0_WIDTH 21 -#define FCRxFF30_01F4_ReservedCgttSclk_21_0_MASK 0x3fffff -#define FCRxFF30_01F4_CgBifCgttSclkOverride_OFFSET 22 -#define FCRxFF30_01F4_CgBifCgttSclkOverride_WIDTH 1 -#define FCRxFF30_01F4_CgBifCgttSclkOverride_MASK 0x400000 -#define FCRxFF30_01F4_ReservedCgttSclk_24_23_OFFSET 23 -#define FCRxFF30_01F4_ReservedCgttSclk_24_23_WIDTH 2 -#define FCRxFF30_01F4_ReservedCgttSclk_24_23_MASK 0x1800000 -#define FCRxFF30_01F4_CgDcCgttSclkOverride_OFFSET 25 -#define FCRxFF30_01F4_CgDcCgttSclkOverride_WIDTH 1 -#define FCRxFF30_01F4_CgDcCgttSclkOverride_MASK 0x2000000 -#define FCRxFF30_01F4_ReservedCgttSclk_26_26_OFFSET 26 -#define FCRxFF30_01F4_ReservedCgttSclk_26_26_WIDTH 1 -#define FCRxFF30_01F4_ReservedCgttSclk_26_26_MASK 0x4000000 -#define FCRxFF30_01F4_CgMcbCgttSclkOverride_OFFSET 27 -#define FCRxFF30_01F4_CgMcbCgttSclkOverride_WIDTH 1 -#define FCRxFF30_01F4_CgMcbCgttSclkOverride_MASK 0x8000000 -#define FCRxFF30_01F4_CgMcdwCgttSclkOverride_OFFSET 28 -#define FCRxFF30_01F4_CgMcdwCgttSclkOverride_WIDTH 1 -#define FCRxFF30_01F4_CgMcdwCgttSclkOverride_MASK 0x10000000 -#define FCRxFF30_01F4_ReservedCgttSclk_31_29_OFFSET 29 -#define FCRxFF30_01F4_ReservedCgttSclk_31_29_WIDTH 3 -#define FCRxFF30_01F4_ReservedCgttSclk_31_29_MASK 0xe0000000 +#define FCRxFE00_70C9_Reserved_6_0_OFFSET 0 +#define FCRxFE00_70C9_Reserved_6_0_WIDTH 7 +#define FCRxFE00_70C9_Reserved_6_0_MASK 0x7f +#define FCRxFE00_70C9_SclkDpmTdpLimit0_OFFSET 7 +#define FCRxFE00_70C9_SclkDpmTdpLimit0_WIDTH 12 +#define FCRxFE00_70C9_SclkDpmTdpLimit0_MASK 0x7ff80 +#define FCRxFE00_70C9_SclkDpmTdpLimit1_OFFSET 19 +#define FCRxFE00_70C9_SclkDpmTdpLimit1_WIDTH 12 +#define FCRxFE00_70C9_SclkDpmTdpLimit1_MASK 0x7ff80000 +#define FCRxFE00_70C9_Reserved_31_31_OFFSET 31 +#define FCRxFE00_70C9_Reserved_31_31_WIDTH 1 +#define FCRxFE00_70C9_Reserved_31_31_MASK 0x80000000 -/// FCRxFF30_01F4 +/// FCRxFE00_70C9 typedef union { struct { ///< - UINT32 ReservedCgttSclk_21_0:22; ///< - UINT32 CgBifCgttSclkOverride:1 ; ///< - UINT32 ReservedCgttSclk_24_23:2 ; ///< - UINT32 CgDcCgttSclkOverride:1 ; ///< - UINT32 ReservedCgttSclk_26_26:1 ; ///< - UINT32 CgMcbCgttSclkOverride:1 ; ///< - UINT32 CgMcdwCgttSclkOverride:1 ; ///< - UINT32 ReservedCgttSclk_31_29:3 ; ///< + UINT32 Reserved_6_0:7 ; ///< + UINT32 SclkDpmTdpLimit0:12; ///< + UINT32 SclkDpmTdpLimit1:12; ///< + UINT32 Reserved_31_31:1 ; ///< } Field; ///< UINT32 Value; ///< -} FCRxFF30_01F4_STRUCT; +} FCRxFE00_70C9_STRUCT; -// **** FCRxFF30_01F5 Register Definition **** +// **** FCRxFE00_70CC Register Definition **** // Address -#define FCRxFF30_01F5_ADDRESS 0xff3001f5 +#define FCRxFE00_70CC_ADDRESS 0xfe0070cc // Type -#define FCRxFF30_01F5_TYPE TYPE_FCR +#define FCRxFE00_70CC_TYPE TYPE_FCR // Field Data -#define FCRxFF30_01F5_ReservedCgttSclk_10_0_OFFSET 0 -#define FCRxFF30_01F5_ReservedCgttSclk_10_0_WIDTH 11 -#define FCRxFF30_01F5_ReservedCgttSclk_10_0_MASK 0x7ff -#define FCRxFF30_01F5_CgVmcCgttSclkOverride_OFFSET 11 -#define FCRxFF30_01F5_CgVmcCgttSclkOverride_WIDTH 1 -#define FCRxFF30_01F5_CgVmcCgttSclkOverride_MASK 0x800 -#define FCRxFF30_01F5_CgOrbCgttSclkOverride_OFFSET 12 -#define FCRxFF30_01F5_CgOrbCgttSclkOverride_WIDTH 1 -#define FCRxFF30_01F5_CgOrbCgttSclkOverride_MASK 0x1000 -#define FCRxFF30_01F5_CgOrbCgttLclkOverride_OFFSET 13 -#define FCRxFF30_01F5_CgOrbCgttLclkOverride_WIDTH 1 -#define FCRxFF30_01F5_CgOrbCgttLclkOverride_MASK 0x2000 -#define FCRxFF30_01F5_CgIocCgttSclkOverride_OFFSET 14 -#define FCRxFF30_01F5_CgIocCgttSclkOverride_WIDTH 1 -#define FCRxFF30_01F5_CgIocCgttSclkOverride_MASK 0x4000 -#define FCRxFF30_01F5_CgIocCgttLclkOverride_OFFSET 15 -#define FCRxFF30_01F5_CgIocCgttLclkOverride_WIDTH 1 -#define FCRxFF30_01F5_CgIocCgttLclkOverride_MASK 0x8000 -#define FCRxFF30_01F5_ReservedCgttSclk_27_16_OFFSET 16 -#define FCRxFF30_01F5_ReservedCgttSclk_27_16_WIDTH 12 -#define FCRxFF30_01F5_ReservedCgttSclk_27_16_MASK 0xfff0000 -#define FCRxFF30_01F5_CgDcCgttDispClkOverride_OFFSET 28 -#define FCRxFF30_01F5_CgDcCgttDispClkOverride_WIDTH 1 -#define FCRxFF30_01F5_CgDcCgttDispClkOverride_MASK 0x10000000 -#define FCRxFF30_01F5_ReservedCgttSclk_31_29_OFFSET 29 -#define FCRxFF30_01F5_ReservedCgttSclk_31_29_WIDTH 3 -#define FCRxFF30_01F5_ReservedCgttSclk_31_29_MASK 0xe0000000 +#define FCRxFE00_70CC_Reserved_6_0_OFFSET 0 +#define FCRxFE00_70CC_Reserved_6_0_WIDTH 7 +#define FCRxFE00_70CC_Reserved_6_0_MASK 0x7f +#define FCRxFE00_70CC_SclkDpmTdpLimit2_OFFSET 7 +#define FCRxFE00_70CC_SclkDpmTdpLimit2_WIDTH 12 +#define FCRxFE00_70CC_SclkDpmTdpLimit2_MASK 0x7ff80 +#define FCRxFE00_70CC_SclkDpmTdpLimit3_OFFSET 19 +#define FCRxFE00_70CC_SclkDpmTdpLimit3_WIDTH 12 +#define FCRxFE00_70CC_SclkDpmTdpLimit3_MASK 0x7ff80000 +#define FCRxFE00_70CC_Reserved_31_31_OFFSET 31 +#define FCRxFE00_70CC_Reserved_31_31_WIDTH 1 +#define FCRxFE00_70CC_Reserved_31_31_MASK 0x80000000 -/// FCRxFF30_01F5 +/// FCRxFE00_70CC typedef union { struct { ///< - UINT32 ReservedCgttSclk_10_0:11; ///< - UINT32 CgVmcCgttSclkOverride:1 ; ///< - UINT32 CgOrbCgttSclkOverride:1 ; ///< - UINT32 CgOrbCgttLclkOverride:1 ; ///< - UINT32 CgIocCgttSclkOverride:1 ; ///< - UINT32 CgIocCgttLclkOverride:1 ; ///< - UINT32 ReservedCgttSclk_27_16:12; ///< - UINT32 CgDcCgttDispClkOverride:1 ; ///< - UINT32 ReservedCgttSclk_31_29:3 ; ///< + UINT32 Reserved_6_0:7 ; ///< + UINT32 SclkDpmTdpLimit2:12; ///< + UINT32 SclkDpmTdpLimit3:12; ///< + UINT32 Reserved_31_31:1 ; ///< } Field; ///< UINT32 Value; ///< -} FCRxFF30_01F5_STRUCT; +} FCRxFE00_70CC_STRUCT; -// **** FCRxFF30_1512 Register Definition **** +// **** FCRxFE00_70CF Register Definition **** // Address -#define FCRxFF30_1512_ADDRESS 0xff301512 +#define FCRxFE00_70CF_ADDRESS 0xfe0070cf // Type -#define FCRxFF30_1512_TYPE TYPE_FCR +#define FCRxFE00_70CF_TYPE TYPE_FCR // Field Data -#define FCRxFF30_1512_Reserved_30_0_OFFSET 0 -#define FCRxFF30_1512_Reserved_30_0_WIDTH 31 -#define FCRxFF30_1512_Reserved_30_0_MASK 0x7fffffff -#define FCRxFF30_1512_SoftOverride0_OFFSET 31 -#define FCRxFF30_1512_SoftOverride0_WIDTH 1 -#define FCRxFF30_1512_SoftOverride0_MASK 0x80000000 +#define FCRxFE00_70CF_Reserved_6_0_OFFSET 0 +#define FCRxFE00_70CF_Reserved_6_0_WIDTH 7 +#define FCRxFE00_70CF_Reserved_6_0_MASK 0x7f +#define FCRxFE00_70CF_SclkDpmTdpLimit4_OFFSET 7 +#define FCRxFE00_70CF_SclkDpmTdpLimit4_WIDTH 12 +#define FCRxFE00_70CF_SclkDpmTdpLimit4_MASK 0x7ff80 +#define FCRxFE00_70CF_SclkDpmTdpLimit5_OFFSET 19 +#define FCRxFE00_70CF_SclkDpmTdpLimit5_WIDTH 12 +#define FCRxFE00_70CF_SclkDpmTdpLimit5_MASK 0x7ff80000 +#define FCRxFE00_70CF_Reserved_31_31_OFFSET 31 +#define FCRxFE00_70CF_Reserved_31_31_WIDTH 1 +#define FCRxFE00_70CF_Reserved_31_31_MASK 0x80000000 -/// FCRxFF30_1512 +/// FCRxFE00_70CF typedef union { struct { ///< - UINT32 Reserved_30_0:31; ///< - UINT32 SoftOverride0:1 ; ///< + UINT32 Reserved_6_0:7 ; ///< + UINT32 SclkDpmTdpLimit4:12; ///< + UINT32 SclkDpmTdpLimit5:12; ///< + UINT32 Reserved_31_31:1 ; ///< } Field; ///< UINT32 Value; ///< -} FCRxFF30_1512_STRUCT; +} FCRxFE00_70CF_STRUCT; -// **** SMUx1B Register Definition **** +// **** FCRxFE00_70D2 Register Definition **** // Address -#define SMUx1B_ADDRESS 0x1b +#define FCRxFE00_70D2_ADDRESS 0xfe0070d2 // Type -#define SMUx1B_TYPE TYPE_SMU +#define FCRxFE00_70D2_TYPE TYPE_FCR // Field Data -#define SMUx1B_LclkDpSlpDiv_OFFSET 0 -#define SMUx1B_LclkDpSlpDiv_WIDTH 3 -#define SMUx1B_LclkDpSlpDiv_MASK 0x7 -#define SMUx1B_RampDis_OFFSET 3 -#define SMUx1B_RampDis_WIDTH 1 -#define SMUx1B_RampDis_MASK 0x8 -#define SMUx1B_Reserved_7_4_OFFSET 4 -#define SMUx1B_Reserved_7_4_WIDTH 4 -#define SMUx1B_Reserved_7_4_MASK 0xf0 -#define SMUx1B_LclkDpSlpMask_OFFSET 8 -#define SMUx1B_LclkDpSlpMask_WIDTH 8 -#define SMUx1B_LclkDpSlpMask_MASK 0xff00 +#define FCRxFE00_70D2_Reserved_6_0_OFFSET 0 +#define FCRxFE00_70D2_Reserved_6_0_WIDTH 7 +#define FCRxFE00_70D2_Reserved_6_0_MASK 0x7f +#define FCRxFE00_70D2_SclkDpmTdpLimitPG_OFFSET 7 +#define FCRxFE00_70D2_SclkDpmTdpLimitPG_WIDTH 12 +#define FCRxFE00_70D2_SclkDpmTdpLimitPG_MASK 0x7ff80 +#define FCRxFE00_70D2_Reserved_31_19_OFFSET 19 +#define FCRxFE00_70D2_Reserved_31_19_WIDTH 13 +#define FCRxFE00_70D2_Reserved_31_19_MASK 0xfff80000 -/// SMUx1B +/// FCRxFE00_70D2 typedef union { struct { ///< - UINT32 LclkDpSlpDiv:3 ; ///< - UINT32 RampDis:1 ; ///< - UINT32 Reserved_7_4:4 ; ///< - UINT32 LclkDpSlpMask:8 ; ///< + UINT32 Reserved_6_0:7 ; ///< + UINT32 SclkDpmTdpLimitPG:12; ///< + UINT32 Reserved_31_19:13; ///< } Field; ///< UINT32 Value; ///< -} SMUx1B_STRUCT; +} FCRxFE00_70D2_STRUCT; -// **** SMUx1D Register Definition **** +// **** FCRxFE00_70D4 Register Definition **** // Address -#define SMUx1D_ADDRESS 0x1d +#define FCRxFE00_70D4_ADDRESS 0xfe0070d4 // Type -#define SMUx1D_TYPE TYPE_SMU +#define FCRxFE00_70D4_TYPE TYPE_FCR // Field Data -#define SMUx1D_LclkDpSlpHyst_OFFSET 0 -#define SMUx1D_LclkDpSlpHyst_WIDTH 12 -#define SMUx1D_LclkDpSlpHyst_MASK 0xfff -#define SMUx1D_LclkDpSlpEn_OFFSET 12 -#define SMUx1D_LclkDpSlpEn_WIDTH 1 -#define SMUx1D_LclkDpSlpEn_MASK 0x1000 -#define SMUx1D_Reserved_15_13_OFFSET 13 -#define SMUx1D_Reserved_15_13_WIDTH 3 -#define SMUx1D_Reserved_15_13_MASK 0xe000 +#define FCRxFE00_70D4_Reserved_2_0_OFFSET 0 +#define FCRxFE00_70D4_Reserved_2_0_WIDTH 3 +#define FCRxFE00_70D4_Reserved_2_0_MASK 0x7 +#define FCRxFE00_70D4_SclkDpmBoostMargin_OFFSET 3 +#define FCRxFE00_70D4_SclkDpmBoostMargin_WIDTH 21 +#define FCRxFE00_70D4_SclkDpmBoostMargin_MASK 0xfffff8 +#define FCRxFE00_70D4_Reserved_31_24_OFFSET 24 +#define FCRxFE00_70D4_Reserved_31_24_WIDTH 8 +#define FCRxFE00_70D4_Reserved_31_24_MASK 0xff000000 -/// SMUx1D +/// FCRxFE00_70D4 typedef union { struct { ///< - UINT32 LclkDpSlpHyst:12; ///< - UINT32 LclkDpSlpEn:1 ; ///< - UINT32 Reserved_15_13:3 ; ///< + UINT32 Reserved_2_0:3 ; ///< + UINT32 SclkDpmBoostMargin:21; ///< + UINT32 Reserved_31_24:8 ; ///< } Field; ///< UINT32 Value; ///< -} SMUx1D_STRUCT; +} FCRxFE00_70D4_STRUCT; -// **** SMUx6F Register Definition **** +// **** FCRxFE00_70D7 Register Definition **** // Address -#define SMUx6F_ADDRESS 0x6f +#define FCRxFE00_70D7_ADDRESS 0xfe0070d7 + +// Type +#define FCRxFE00_70D7_TYPE TYPE_FCR +// Field Data +#define FCRxFE00_70D7_SclkDpmThrottleMargin_OFFSET 0 +#define FCRxFE00_70D7_SclkDpmThrottleMargin_WIDTH 21 +#define FCRxFE00_70D7_SclkDpmThrottleMargin_MASK 0x1fffff +#define FCRxFE00_70D7_Reserved_31_21_OFFSET 21 +#define FCRxFE00_70D7_Reserved_31_21_WIDTH 11 +#define FCRxFE00_70D7_Reserved_31_21_MASK 0xffe00000 +/// FCRxFE00_70D7 +typedef union { + struct { ///< + UINT32 SclkDpmThrottleMargin:21; ///< + UINT32 Reserved_31_21:11; ///< + } Field; ///< + UINT32 Value; ///< +} FCRxFE00_70D7_STRUCT; -// **** SMUx71 Register Definition **** +// **** SMUx0B_x8410 Register Definition **** // Address -#define SMUx71_ADDRESS 0x71 +#define SMUx0B_x8410_ADDRESS 0x8410 + +// Type +#define SMUx0B_x8410_TYPE TYPE_SMUx0B +// Field Data +#define SMUx0B_x8410_PwrGatingEn_OFFSET 0 +#define SMUx0B_x8410_PwrGatingEn_WIDTH 1 +#define SMUx0B_x8410_PwrGatingEn_MASK 0x1 +#define SMUx0B_x8410_Reserved_2_1_OFFSET 1 +#define SMUx0B_x8410_Reserved_2_1_WIDTH 2 +#define SMUx0B_x8410_Reserved_2_1_MASK 0x6 +#define SMUx0B_x8410_PsoControlValidNum_OFFSET 3 +#define SMUx0B_x8410_PsoControlValidNum_WIDTH 5 +#define SMUx0B_x8410_PsoControlValidNum_MASK 0xf8 +#define SMUx0B_x8410_SavePsoDelay_OFFSET 8 +#define SMUx0B_x8410_SavePsoDelay_WIDTH 4 +#define SMUx0B_x8410_SavePsoDelay_MASK 0xf00 +#define SMUx0B_x8410_NRestoreIsoDelay_OFFSET 12 +#define SMUx0B_x8410_NRestoreIsoDelay_WIDTH 4 +#define SMUx0B_x8410_NRestoreIsoDelay_MASK 0xf000 +#define SMUx0B_x8410_RstPulseWidth_OFFSET 16 +#define SMUx0B_x8410_RstPulseWidth_WIDTH 8 +#define SMUx0B_x8410_RstPulseWidth_MASK 0xff0000 +#define SMUx0B_x8410_IsoDelay_OFFSET 24 +#define SMUx0B_x8410_IsoDelay_WIDTH 4 +#define SMUx0B_x8410_IsoDelay_MASK 0xf000000 +#define SMUx0B_x8410_PwrGaterSel_OFFSET 28 +#define SMUx0B_x8410_PwrGaterSel_WIDTH 4 +#define SMUx0B_x8410_PwrGaterSel_MASK 0xf0000000 +/// SMUx0B_x8410 +typedef union { + struct { ///< + UINT32 PwrGatingEn:1 ; ///< + UINT32 Reserved_2_1:2 ; ///< + UINT32 PsoControlValidNum:5 ; ///< + UINT32 SavePsoDelay:4 ; ///< + UINT32 NRestoreIsoDelay:4 ; ///< + UINT32 RstPulseWidth:8 ; ///< + UINT32 IsoDelay:4 ; ///< + UINT32 PwrGaterSel:4 ; ///< + } Field; ///< + UINT32 Value; ///< +} SMUx0B_x8410_STRUCT; -// **** SMUx73 Register Definition **** +// **** SMUx0B_x8504 Register Definition **** // Address -#define SMUx73_ADDRESS 0x73 +#define SMUx0B_x8504_ADDRESS 0x8504 // Type -#define SMUx73_TYPE TYPE_SMU +#define SMUx0B_x8504_TYPE TYPE_SMUx0B // Field Data -#define SMUx73_DisLclkGating_OFFSET 0 -#define SMUx73_DisLclkGating_WIDTH 1 -#define SMUx73_DisLclkGating_MASK 0x1 -#define SMUx73_DisSclkGating_OFFSET 1 -#define SMUx73_DisSclkGating_WIDTH 1 -#define SMUx73_DisSclkGating_MASK 0x2 -#define SMUx73_Reserved_15_2_OFFSET 2 -#define SMUx73_Reserved_15_2_WIDTH 14 -#define SMUx73_Reserved_15_2_MASK 0xfffc +#define SMUx0B_x8504_SaveRestoreWidth_OFFSET 0 +#define SMUx0B_x8504_SaveRestoreWidth_WIDTH 8 +#define SMUx0B_x8504_SaveRestoreWidth_MASK 0xff +#define SMUx0B_x8504_PsoRestoreTimer_OFFSET 8 +#define SMUx0B_x8504_PsoRestoreTimer_WIDTH 8 +#define SMUx0B_x8504_PsoRestoreTimer_MASK 0xff00 +#define SMUx0B_x8504_Reserved_31_16_OFFSET 16 +#define SMUx0B_x8504_Reserved_31_16_WIDTH 16 +#define SMUx0B_x8504_Reserved_31_16_MASK 0xffff0000 -/// SMUx73 +/// SMUx0B_x8504 typedef union { struct { ///< - UINT32 DisLclkGating:1 ; ///< - UINT32 DisSclkGating:1 ; ///< - UINT32 Reserved_15_2:14; ///< + UINT32 SaveRestoreWidth:8 ; ///< + UINT32 PsoRestoreTimer:8 ; ///< + UINT32 Reserved_31_16:16; ///< } Field; ///< UINT32 Value; ///< -} SMUx73_STRUCT; +} SMUx0B_x8504_STRUCT; -// **** D0F0x98_x49 Register Definition **** +// **** SMUx0B_x8408 Register Definition **** // Address -#define D0F0x98_x49_ADDRESS 0x49 +#define SMUx0B_x8408_ADDRESS 0x8408 // Type -#define D0F0x98_x49_TYPE TYPE_D0F0x98 +#define SMUx0B_x8408_TYPE TYPE_SMUx0B +// Field Data +#define SMUx0B_x8408_PsoControlId0_OFFSET 0 +#define SMUx0B_x8408_PsoControlId0_WIDTH 4 +#define SMUx0B_x8408_PsoControlId0_MASK 0xf +#define SMUx0B_x8408_PsoControlId1_OFFSET 4 +#define SMUx0B_x8408_PsoControlId1_WIDTH 4 +#define SMUx0B_x8408_PsoControlId1_MASK 0xf0 +#define SMUx0B_x8408_PsoControlId2_OFFSET 8 +#define SMUx0B_x8408_PsoControlId2_WIDTH 4 +#define SMUx0B_x8408_PsoControlId2_MASK 0xf00 +#define SMUx0B_x8408_PsoControlId3_OFFSET 12 +#define SMUx0B_x8408_PsoControlId3_WIDTH 4 +#define SMUx0B_x8408_PsoControlId3_MASK 0xf000 +#define SMUx0B_x8408_PsoControlId4_OFFSET 16 +#define SMUx0B_x8408_PsoControlId4_WIDTH 4 +#define SMUx0B_x8408_PsoControlId4_MASK 0xf0000 +#define SMUx0B_x8408_PsoControlId5_OFFSET 20 +#define SMUx0B_x8408_PsoControlId5_WIDTH 4 +#define SMUx0B_x8408_PsoControlId5_MASK 0xf00000 +#define SMUx0B_x8408_PsoControlId6_OFFSET 24 +#define SMUx0B_x8408_PsoControlId6_WIDTH 4 +#define SMUx0B_x8408_PsoControlId6_MASK 0xf000000 +#define SMUx0B_x8408_PsoControlId7_OFFSET 28 +#define SMUx0B_x8408_PsoControlId7_WIDTH 4 +#define SMUx0B_x8408_PsoControlId7_MASK 0xf0000000 + +/// SMUx0B_x8408 +typedef union { + struct { ///< + UINT32 PsoControlId0:4 ; ///< + UINT32 PsoControlId1:4 ; ///< + UINT32 PsoControlId2:4 ; ///< + UINT32 PsoControlId3:4 ; ///< + UINT32 PsoControlId4:4 ; ///< + UINT32 PsoControlId5:4 ; ///< + UINT32 PsoControlId6:4 ; ///< + UINT32 PsoControlId7:4 ; ///< + } Field; ///< + UINT32 Value; ///< +} SMUx0B_x8408_STRUCT; + +// **** FCRxFF30_0398 Register Definition **** +// Address +#define FCRxFF30_0398_ADDRESS 0xff300398 + +// Type +#define FCRxFF30_0398_TYPE TYPE_FCR // Field Data -#define D0F0x98_x49_Reserved_23_0_OFFSET 0 -#define D0F0x98_x49_Reserved_23_0_WIDTH 24 -#define D0F0x98_x49_Reserved_23_0_MASK 0xffffff -#define D0F0x98_x49_SoftOverrideClk6_OFFSET 24 -#define D0F0x98_x49_SoftOverrideClk6_WIDTH 1 -#define D0F0x98_x49_SoftOverrideClk6_MASK 0x1000000 -#define D0F0x98_x49_SoftOverrideClk5_OFFSET 25 -#define D0F0x98_x49_SoftOverrideClk5_WIDTH 1 -#define D0F0x98_x49_SoftOverrideClk5_MASK 0x2000000 -#define D0F0x98_x49_SoftOverrideClk4_OFFSET 26 -#define D0F0x98_x49_SoftOverrideClk4_WIDTH 1 -#define D0F0x98_x49_SoftOverrideClk4_MASK 0x4000000 -#define D0F0x98_x49_SoftOverrideClk3_OFFSET 27 -#define D0F0x98_x49_SoftOverrideClk3_WIDTH 1 -#define D0F0x98_x49_SoftOverrideClk3_MASK 0x8000000 -#define D0F0x98_x49_SoftOverrideClk2_OFFSET 28 -#define D0F0x98_x49_SoftOverrideClk2_WIDTH 1 -#define D0F0x98_x49_SoftOverrideClk2_MASK 0x10000000 -#define D0F0x98_x49_SoftOverrideClk1_OFFSET 29 -#define D0F0x98_x49_SoftOverrideClk1_WIDTH 1 -#define D0F0x98_x49_SoftOverrideClk1_MASK 0x20000000 -#define D0F0x98_x49_SoftOverrideClk0_OFFSET 30 -#define D0F0x98_x49_SoftOverrideClk0_WIDTH 1 -#define D0F0x98_x49_SoftOverrideClk0_MASK 0x40000000 -#define D0F0x98_x49_Reserved_31_31_OFFSET 31 -#define D0F0x98_x49_Reserved_31_31_WIDTH 1 -#define D0F0x98_x49_Reserved_31_31_MASK 0x80000000 +#define FCRxFF30_0398_Reserved_0_0_OFFSET 0 +#define FCRxFF30_0398_Reserved_0_0_WIDTH 1 +#define FCRxFF30_0398_Reserved_0_0_MASK 0x1 +#define FCRxFF30_0398_SoftResetCg_OFFSET 2 +#define FCRxFF30_0398_SoftResetCg_WIDTH 1 +#define FCRxFF30_0398_SoftResetCg_MASK 0x4 +#define FCRxFF30_0398_Reserved_4_3_OFFSET 3 +#define FCRxFF30_0398_Reserved_4_3_WIDTH 2 +#define FCRxFF30_0398_Reserved_4_3_MASK 0x18 +#define FCRxFF30_0398_SoftResetDc_OFFSET 5 +#define FCRxFF30_0398_SoftResetDc_WIDTH 1 +#define FCRxFF30_0398_SoftResetDc_MASK 0x20 +#define FCRxFF30_0398_Reserved_6_6_OFFSET 6 +#define FCRxFF30_0398_Reserved_6_6_WIDTH 1 +#define FCRxFF30_0398_Reserved_6_6_MASK 0x40 +#define FCRxFF30_0398_SoftResetGrbm_OFFSET 8 +#define FCRxFF30_0398_SoftResetGrbm_WIDTH 1 +#define FCRxFF30_0398_SoftResetGrbm_MASK 0x100 +#define FCRxFF30_0398_SoftResetMc_OFFSET 11 +#define FCRxFF30_0398_SoftResetMc_WIDTH 1 +#define FCRxFF30_0398_SoftResetMc_MASK 0x800 +#define FCRxFF30_0398_Reserved_12_12_OFFSET 12 +#define FCRxFF30_0398_Reserved_12_12_WIDTH 1 +#define FCRxFF30_0398_Reserved_12_12_MASK 0x1000 +#define FCRxFF30_0398_SoftResetRlc_OFFSET 13 +#define FCRxFF30_0398_SoftResetRlc_WIDTH 1 +#define FCRxFF30_0398_SoftResetRlc_MASK 0x2000 +#define FCRxFF30_0398_Reserved_16_16_OFFSET 16 +#define FCRxFF30_0398_Reserved_16_16_WIDTH 1 +#define FCRxFF30_0398_Reserved_16_16_MASK 0x10000 +#define FCRxFF30_0398_SoftResetUvd_OFFSET 18 +#define FCRxFF30_0398_SoftResetUvd_WIDTH 1 +#define FCRxFF30_0398_SoftResetUvd_MASK 0x40000 +#define FCRxFF30_0398_Reserved_19_19_OFFSET 19 +#define FCRxFF30_0398_Reserved_19_19_WIDTH 1 +#define FCRxFF30_0398_Reserved_19_19_MASK 0x80000 -/// D0F0x98_x49 +#define FCRxFF30_0398_Reserved_31_24_OFFSET 24 +#define FCRxFF30_0398_Reserved_31_24_WIDTH 8 +#define FCRxFF30_0398_Reserved_31_24_MASK 0xff000000 + +/// FCRxFF30_0398 typedef union { struct { ///< - UINT32 Reserved_23_0:24; ///< - UINT32 SoftOverrideClk6:1 ; ///< - UINT32 SoftOverrideClk5:1 ; ///< - UINT32 SoftOverrideClk4:1 ; ///< - UINT32 SoftOverrideClk3:1 ; ///< - UINT32 SoftOverrideClk2:1 ; ///< - UINT32 SoftOverrideClk1:1 ; ///< - UINT32 SoftOverrideClk0:1 ; ///< - UINT32 Reserved_31_31:1 ; ///< + UINT32 Reserved_0_0:1 ; ///< + UINT32 Reserved_1_1:1 ; ///< + UINT32 SoftResetCg:1 ; ///< + UINT32 Reserved_4_3:2 ; ///< + UINT32 SoftResetDc:1 ; ///< + UINT32 Reserved_6_6:1 ; ///< + UINT32 Reserved_7_7:1 ; ///< + UINT32 SoftResetGrbm:1 ; ///< + UINT32 Reserved_9_9:1 ; ///< + UINT32 Reserved_10_10:1 ; ///< + UINT32 SoftResetMc:1 ; ///< + UINT32 Reserved_12_12:1 ; ///< + UINT32 SoftResetRlc:1 ; ///< + UINT32 Reserved_14_14:1 ; ///< + UINT32 Reserved_15_15:1 ; ///< + UINT32 Reserved_16_16:1 ; ///< + UINT32 Reserved_17_17:1 ; ///< + UINT32 SoftResetUvd:1 ; ///< + UINT32 Reserved_19_19:1 ; ///< + UINT32 Reserved_20_20:1 ; ///< + UINT32 Reserved_21_21:1 ; ///< + UINT32 Reserved_22_22:1 ; ///< + UINT32 Reserved_23_23:1 ; ///< + UINT32 Reserved_31_24:8 ; ///< } Field; ///< UINT32 Value; ///< -} D0F0x98_x49_STRUCT; +} FCRxFF30_0398_STRUCT; -// **** D0F0x98_x4A Register Definition **** +// **** FCRxFF30_1512 Register Definition **** // Address -#define D0F0x98_x4A_ADDRESS 0x4a +#define FCRxFF30_1512_ADDRESS 0xff301512 // Type -#define D0F0x98_x4A_TYPE TYPE_D0F0x98 +#define FCRxFF30_1512_TYPE TYPE_FCR // Field Data -#define D0F0x98_x4A_Reserved_23_0_OFFSET 0 -#define D0F0x98_x4A_Reserved_23_0_WIDTH 24 -#define D0F0x98_x4A_Reserved_23_0_MASK 0xffffff -#define D0F0x98_x4A_SoftOverrideClk6_OFFSET 24 -#define D0F0x98_x4A_SoftOverrideClk6_WIDTH 1 -#define D0F0x98_x4A_SoftOverrideClk6_MASK 0x1000000 -#define D0F0x98_x4A_SoftOverrideClk5_OFFSET 25 -#define D0F0x98_x4A_SoftOverrideClk5_WIDTH 1 -#define D0F0x98_x4A_SoftOverrideClk5_MASK 0x2000000 -#define D0F0x98_x4A_SoftOverrideClk4_OFFSET 26 -#define D0F0x98_x4A_SoftOverrideClk4_WIDTH 1 -#define D0F0x98_x4A_SoftOverrideClk4_MASK 0x4000000 -#define D0F0x98_x4A_SoftOverrideClk3_OFFSET 27 -#define D0F0x98_x4A_SoftOverrideClk3_WIDTH 1 -#define D0F0x98_x4A_SoftOverrideClk3_MASK 0x8000000 -#define D0F0x98_x4A_SoftOverrideClk2_OFFSET 28 -#define D0F0x98_x4A_SoftOverrideClk2_WIDTH 1 -#define D0F0x98_x4A_SoftOverrideClk2_MASK 0x10000000 -#define D0F0x98_x4A_SoftOverrideClk1_OFFSET 29 -#define D0F0x98_x4A_SoftOverrideClk1_WIDTH 1 -#define D0F0x98_x4A_SoftOverrideClk1_MASK 0x20000000 -#define D0F0x98_x4A_SoftOverrideClk0_OFFSET 30 -#define D0F0x98_x4A_SoftOverrideClk0_WIDTH 1 -#define D0F0x98_x4A_SoftOverrideClk0_MASK 0x40000000 -#define D0F0x98_x4A_Reserved_31_31_OFFSET 31 -#define D0F0x98_x4A_Reserved_31_31_WIDTH 1 -#define D0F0x98_x4A_Reserved_31_31_MASK 0x80000000 +#define FCRxFF30_1512_Reserved_30_0_OFFSET 0 +#define FCRxFF30_1512_Reserved_30_0_WIDTH 31 +#define FCRxFF30_1512_Reserved_30_0_MASK 0x7fffffff +#define FCRxFF30_1512_SoftOverride0_OFFSET 31 +#define FCRxFF30_1512_SoftOverride0_WIDTH 1 +#define FCRxFF30_1512_SoftOverride0_MASK 0x80000000 -/// D0F0x98_x4A +/// FCRxFF30_1512 typedef union { struct { ///< - UINT32 Reserved_23_0:24; ///< - UINT32 SoftOverrideClk6:1 ; ///< - UINT32 SoftOverrideClk5:1 ; ///< - UINT32 SoftOverrideClk4:1 ; ///< - UINT32 SoftOverrideClk3:1 ; ///< - UINT32 SoftOverrideClk2:1 ; ///< - UINT32 SoftOverrideClk1:1 ; ///< - UINT32 SoftOverrideClk0:1 ; ///< - UINT32 Reserved_31_31:1 ; ///< + UINT32 Reserved_30_0:31; ///< + UINT32 SoftOverride0:1 ; ///< } Field; ///< UINT32 Value; ///< -} D0F0x98_x4A_STRUCT; +} FCRxFF30_1512_STRUCT; -// **** D0F0x98_x4B Register Definition **** +// **** SMUx0B_x84A0 Register Definition **** // Address -#define D0F0x98_x4B_ADDRESS 0x4b +#define SMUx0B_x84A0_ADDRESS 0x84a0 // Type -#define D0F0x98_x4B_TYPE TYPE_D0F0x98 +#define SMUx0B_x84A0_TYPE TYPE_SMUx0B // Field Data -#define D0F0x98_x4B_Reserved_29_0_OFFSET 0 -#define D0F0x98_x4B_Reserved_29_0_WIDTH 30 -#define D0F0x98_x4B_Reserved_29_0_MASK 0x3fffffff -#define D0F0x98_x4B_SoftOverrideClk_OFFSET 30 -#define D0F0x98_x4B_SoftOverrideClk_WIDTH 1 -#define D0F0x98_x4B_SoftOverrideClk_MASK 0x40000000 -#define D0F0x98_x4B_Reserved_31_31_OFFSET 31 -#define D0F0x98_x4B_Reserved_31_31_WIDTH 1 -#define D0F0x98_x4B_Reserved_31_31_MASK 0x80000000 +#define SMUx0B_x84A0_MothPsoPwrup_OFFSET 0 +#define SMUx0B_x84A0_MothPsoPwrup_WIDTH 16 +#define SMUx0B_x84A0_MothPsoPwrup_MASK 0xffff +#define SMUx0B_x84A0_MothPsoPwrdn_OFFSET 16 +#define SMUx0B_x84A0_MothPsoPwrdn_WIDTH 16 +#define SMUx0B_x84A0_MothPsoPwrdn_MASK 0xffff0000 -/// D0F0x98_x4B +/// SMUx0B_x84A0 typedef union { struct { ///< - UINT32 Reserved_29_0:30; ///< - UINT32 SoftOverrideClk:1 ; ///< - UINT32 Reserved_31_31:1 ; ///< + UINT32 MothPsoPwrup:16; ///< + UINT32 MothPsoPwrdn:16; ///< } Field; ///< UINT32 Value; ///< -} D0F0x98_x4B_STRUCT; +} SMUx0B_x84A0_STRUCT; +// **** GMMxCAC Register Definition **** +// Address +#define GMMxCAC_ADDRESS 0xcac -// **** D0F0x64_x22 Register Definition **** +// Type +#define GMMxCAC_TYPE TYPE_GMM +// Field Data +#define GMMxCAC_NbPstateChangeEnable_OFFSET 0 +#define GMMxCAC_NbPstateChangeEnable_WIDTH 1 +#define GMMxCAC_NbPstateChangeEnable_MASK 0x1 +#define GMMxCAC_Reserved_3_1_OFFSET 1 +#define GMMxCAC_Reserved_3_1_WIDTH 3 +#define GMMxCAC_Reserved_3_1_MASK 0xe +#define GMMxCAC_NbPstateChangeUrgentDuringRequest_OFFSET 4 +#define GMMxCAC_NbPstateChangeUrgentDuringRequest_WIDTH 1 +#define GMMxCAC_NbPstateChangeUrgentDuringRequest_MASK 0x10 +#define GMMxCAC_Reserved_7_5_OFFSET 5 +#define GMMxCAC_Reserved_7_5_WIDTH 3 +#define GMMxCAC_Reserved_7_5_MASK 0xe0 +#define GMMxCAC_NbPstateChangeNotSelfRefreshDuringRequest_OFFSET 8 +#define GMMxCAC_NbPstateChangeNotSelfRefreshDuringRequest_WIDTH 1 +#define GMMxCAC_NbPstateChangeNotSelfRefreshDuringRequest_MASK 0x100 +#define GMMxCAC_NbPstateChangeForceOn_OFFSET 9 +#define GMMxCAC_NbPstateChangeForceOn_WIDTH 1 +#define GMMxCAC_NbPstateChangeForceOn_MASK 0x200 +#define GMMxCAC_Reserved_11_10_OFFSET 10 +#define GMMxCAC_Reserved_11_10_WIDTH 2 +#define GMMxCAC_Reserved_11_10_MASK 0xc00 +#define GMMxCAC_NbPstateChangeWatermarkMask_OFFSET 12 +#define GMMxCAC_NbPstateChangeWatermarkMask_WIDTH 2 +#define GMMxCAC_NbPstateChangeWatermarkMask_MASK 0x3000 +#define GMMxCAC_Reserved_15_14_OFFSET 14 +#define GMMxCAC_Reserved_15_14_WIDTH 2 +#define GMMxCAC_Reserved_15_14_MASK 0xc000 +#define GMMxCAC_NbPstateChangeWatermark_OFFSET 16 +#define GMMxCAC_NbPstateChangeWatermark_WIDTH 16 +#define GMMxCAC_NbPstateChangeWatermark_MASK 0xffff0000 + +/// GMMxCAC +typedef union { + struct { ///< + UINT32 NbPstateChangeEnable:1 ; ///< + UINT32 Reserved_3_1:3 ; ///< + UINT32 NbPstateChangeUrgentDuringRequest:1 ; ///< + UINT32 Reserved_7_5:3 ; ///< + UINT32 NbPstateChangeNotSelfRefreshDuringRequest:1 ; ///< + UINT32 NbPstateChangeForceOn:1 ; ///< + UINT32 Reserved_11_10:2 ; ///< + UINT32 NbPstateChangeWatermarkMask:2 ; ///< + UINT32 Reserved_15_14:2 ; ///< + UINT32 NbPstateChangeWatermark:16; ///< + } Field; ///< + UINT32 Value; ///< +} GMMxCAC_STRUCT; + +// **** GMMxCCC Register Definition **** +// Address +#define GMMxCCC_ADDRESS 0xccc + +// Type +#define GMMxCCC_TYPE TYPE_GMM +// Field Data +#define GMMxCCC_NbPstateChangeEnable_OFFSET 0 +#define GMMxCCC_NbPstateChangeEnable_WIDTH 1 +#define GMMxCCC_NbPstateChangeEnable_MASK 0x1 +#define GMMxCCC_Reserved_3_1_OFFSET 1 +#define GMMxCCC_Reserved_3_1_WIDTH 3 +#define GMMxCCC_Reserved_3_1_MASK 0xe +#define GMMxCCC_NbPstateChangeUrgentDuringRequest_OFFSET 4 +#define GMMxCCC_NbPstateChangeUrgentDuringRequest_WIDTH 1 +#define GMMxCCC_NbPstateChangeUrgentDuringRequest_MASK 0x10 +#define GMMxCCC_Reserved_7_5_OFFSET 5 +#define GMMxCCC_Reserved_7_5_WIDTH 3 +#define GMMxCCC_Reserved_7_5_MASK 0xe0 +#define GMMxCCC_NbPstateChangeNotSelfRefreshDuringRequest_OFFSET 8 +#define GMMxCCC_NbPstateChangeNotSelfRefreshDuringRequest_WIDTH 1 +#define GMMxCCC_NbPstateChangeNotSelfRefreshDuringRequest_MASK 0x100 +#define GMMxCCC_NbPstateChangeForceOn_OFFSET 9 +#define GMMxCCC_NbPstateChangeForceOn_WIDTH 1 +#define GMMxCCC_NbPstateChangeForceOn_MASK 0x200 +#define GMMxCCC_Reserved_11_10_OFFSET 10 +#define GMMxCCC_Reserved_11_10_WIDTH 2 +#define GMMxCCC_Reserved_11_10_MASK 0xc00 +#define GMMxCCC_NbPstateChangeWatermarkMask_OFFSET 12 +#define GMMxCCC_NbPstateChangeWatermarkMask_WIDTH 2 +#define GMMxCCC_NbPstateChangeWatermarkMask_MASK 0x3000 +#define GMMxCCC_Reserved_15_14_OFFSET 14 +#define GMMxCCC_Reserved_15_14_WIDTH 2 +#define GMMxCCC_Reserved_15_14_MASK 0xc000 +#define GMMxCCC_NbPstateChangeWatermark_OFFSET 16 +#define GMMxCCC_NbPstateChangeWatermark_WIDTH 16 +#define GMMxCCC_NbPstateChangeWatermark_MASK 0xffff0000 + +/// GMMxCCC +typedef union { + struct { ///< + UINT32 NbPstateChangeEnable:1 ; ///< + UINT32 Reserved_3_1:3 ; ///< + UINT32 NbPstateChangeUrgentDuringRequest:1 ; ///< + UINT32 Reserved_7_5:3 ; ///< + UINT32 NbPstateChangeNotSelfRefreshDuringRequest:1 ; ///< + UINT32 NbPstateChangeForceOn:1 ; ///< + UINT32 Reserved_11_10:2 ; ///< + UINT32 NbPstateChangeWatermarkMask:2 ; ///< + UINT32 Reserved_15_14:2 ; ///< + UINT32 NbPstateChangeWatermark:16; ///< + } Field; ///< + UINT32 Value; ///< +} GMMxCCC_STRUCT; + +// **** GMMx6B30 Register Definition **** // Address -#define D0F0x64_x22_ADDRESS 0x22 +#define GMMx6B30_ADDRESS 0x6b30 // Type -#define D0F0x64_x22_TYPE TYPE_D0F0x64 +#define GMMx6B30_TYPE TYPE_GMM // Field Data -#define D0F0x64_x22_Reserved_25_0_OFFSET 0 -#define D0F0x64_x22_Reserved_25_0_WIDTH 26 -#define D0F0x64_x22_Reserved_25_0_MASK 0x3ffffff -#define D0F0x64_x22_SoftOverrideClk4_OFFSET 26 -#define D0F0x64_x22_SoftOverrideClk4_WIDTH 1 -#define D0F0x64_x22_SoftOverrideClk4_MASK 0x4000000 -#define D0F0x64_x22_SoftOverrideClk3_OFFSET 27 -#define D0F0x64_x22_SoftOverrideClk3_WIDTH 1 -#define D0F0x64_x22_SoftOverrideClk3_MASK 0x8000000 -#define D0F0x64_x22_SoftOverrideClk2_OFFSET 28 -#define D0F0x64_x22_SoftOverrideClk2_WIDTH 1 -#define D0F0x64_x22_SoftOverrideClk2_MASK 0x10000000 -#define D0F0x64_x22_SoftOverrideClk1_OFFSET 29 -#define D0F0x64_x22_SoftOverrideClk1_WIDTH 1 -#define D0F0x64_x22_SoftOverrideClk1_MASK 0x20000000 -#define D0F0x64_x22_SoftOverrideClk0_OFFSET 30 -#define D0F0x64_x22_SoftOverrideClk0_WIDTH 1 -#define D0F0x64_x22_SoftOverrideClk0_MASK 0x40000000 -#define D0F0x64_x22_Reserved_31_31_OFFSET 31 -#define D0F0x64_x22_Reserved_31_31_WIDTH 1 -#define D0F0x64_x22_Reserved_31_31_MASK 0x80000000 +#define GMMx6B30_DcAllowNbPstatesForceOne_OFFSET 25 +#define GMMx6B30_DcAllowNbPstatesForceOne_WIDTH 1 +#define GMMx6B30_DcAllowNbPstatesForceOne_MASK 0x2000000 -/// D0F0x64_x22 +/// GMMx6B30 typedef union { struct { ///< - UINT32 Reserved_25_0:26; ///< - UINT32 SoftOverrideClk4:1 ; ///< - UINT32 SoftOverrideClk3:1 ; ///< - UINT32 SoftOverrideClk2:1 ; ///< - UINT32 SoftOverrideClk1:1 ; ///< - UINT32 SoftOverrideClk0:1 ; ///< - UINT32 Reserved_31_31:1 ; ///< + UINT32 Reserved_0_24:25 ; ///< + UINT32 DcAllowNbPstatesForceOne:1 ; ///< + UINT32 Reserved_31_26:6 ; ///< } Field; ///< UINT32 Value; ///< -} D0F0x64_x22_STRUCT; +} GMMx6B30_STRUCT; -// **** D0F0x64_x23 Register Definition **** +// **** GMMx7730 Register Definition **** // Address -#define D0F0x64_x23_ADDRESS 0x23 +#define GMMx7730_ADDRESS 0x7730 // Type -#define D0F0x64_x23_TYPE TYPE_D0F0x64 +#define GMMx7730_TYPE TYPE_GMM // Field Data -#define D0F0x64_x23_Reserved_26_0_OFFSET 0 -#define D0F0x64_x23_Reserved_26_0_WIDTH 27 -#define D0F0x64_x23_Reserved_26_0_MASK 0x7ffffff -#define D0F0x64_x23_SoftOverrideClk3_OFFSET 27 -#define D0F0x64_x23_SoftOverrideClk3_WIDTH 1 -#define D0F0x64_x23_SoftOverrideClk3_MASK 0x8000000 -#define D0F0x64_x23_SoftOverrideClk2_OFFSET 28 -#define D0F0x64_x23_SoftOverrideClk2_WIDTH 1 -#define D0F0x64_x23_SoftOverrideClk2_MASK 0x10000000 -#define D0F0x64_x23_SoftOverrideClk1_OFFSET 29 -#define D0F0x64_x23_SoftOverrideClk1_WIDTH 1 -#define D0F0x64_x23_SoftOverrideClk1_MASK 0x20000000 -#define D0F0x64_x23_SoftOverrideClk0_OFFSET 30 -#define D0F0x64_x23_SoftOverrideClk0_WIDTH 1 -#define D0F0x64_x23_SoftOverrideClk0_MASK 0x40000000 -#define D0F0x64_x23_Reserved_31_31_OFFSET 31 -#define D0F0x64_x23_Reserved_31_31_WIDTH 1 -#define D0F0x64_x23_Reserved_31_31_MASK 0x80000000 -/// D0F0x64_x23 +#define GMMx7730_DcAllowNbPstatesForceOne_OFFSET 25 +#define GMMx7730_DcAllowNbPstatesForceOne_WIDTH 1 +#define GMMx7730_DcAllowNbPstatesForceOne_MASK 0x2000000 + +/// GMMx7730 typedef union { struct { ///< - UINT32 Reserved_26_0:27; ///< - UINT32 SoftOverrideClk3:1 ; ///< - UINT32 SoftOverrideClk2:1 ; ///< - UINT32 SoftOverrideClk1:1 ; ///< - UINT32 SoftOverrideClk0:1 ; ///< - UINT32 Reserved_31_31:1 ; ///< + UINT32 Reserved_0_24:25 ; ///< + UINT32 DcAllowNbPstatesForceOne:1 ; ///< + UINT32 Reserved_31_26:6 ; ///< } Field; ///< UINT32 Value; ///< -} D0F0x64_x23_STRUCT; +} GMMx7730_STRUCT; +// **** GMMx2854 Register Definition **** +// Address +#define GMMx2854_ADDRESS 0x2854 -// **** D0F0x64_x24 Register Definition **** +// Type +#define GMMx2854_TYPE TYPE_GMM +// **** D0F0x98_x0C Register Definition **** // Address -#define D0F0x64_x24_ADDRESS 0x24 +#define D0F0x98_x0C_ADDRESS 0xc // Type -#define D0F0x64_x24_TYPE TYPE_D0F0x64 +#define D0F0x98_x0C_TYPE TYPE_D0F0x98 +#define D0F0x98_x0C_IntrHiPriClr_OFFSET 31 +#define D0F0x98_x0C_IntrHiPriClr_WIDTH 1 +#define D0F0x98_x0C_IntrHiPriClr_MASK 0x80000000 +// **** D0F0x98_x0D Register Definition **** +// Address +#define D0F0x98_x0D_ADDRESS 0xd + +// Type +#define D0F0x98_x0D_TYPE TYPE_D0F0x98 +// **** D18F3xA0 Register Definition **** +// Address +#define D18F3xA0_ADDRESS 0xa0 + +// Type +#define D18F3xA0_TYPE TYPE_D18F3 // Field Data -#define D0F0x64_x24_Reserved_28_0_OFFSET 0 -#define D0F0x64_x24_Reserved_28_0_WIDTH 29 -#define D0F0x64_x24_Reserved_28_0_MASK 0x1fffffff -#define D0F0x64_x24_SoftOverrideClk1_OFFSET 29 -#define D0F0x64_x24_SoftOverrideClk1_WIDTH 1 -#define D0F0x64_x24_SoftOverrideClk1_MASK 0x20000000 -#define D0F0x64_x24_SoftOverrideClk0_OFFSET 30 -#define D0F0x64_x24_SoftOverrideClk0_WIDTH 1 -#define D0F0x64_x24_SoftOverrideClk0_MASK 0x40000000 -#define D0F0x64_x24_Reserved_31_31_OFFSET 31 -#define D0F0x64_x24_Reserved_31_31_WIDTH 1 -#define D0F0x64_x24_Reserved_31_31_MASK 0x80000000 +#define D18F3xA0_PsiVid_OFFSET 0 +#define D18F3xA0_PsiVid_WIDTH 7 +#define D18F3xA0_PsiVid_MASK 0x7f +#define D18F3xA0_PsiVidEn_OFFSET 7 +#define D18F3xA0_PsiVidEn_WIDTH 1 +#define D18F3xA0_PsiVidEn_MASK 0x80 +#define D18F3xA0_Reserved_8_8_OFFSET 8 +#define D18F3xA0_Reserved_8_8_WIDTH 1 +#define D18F3xA0_Reserved_8_8_MASK 0x100 +#define D18F3xA0_SviHighFreqSel_OFFSET 9 +#define D18F3xA0_SviHighFreqSel_WIDTH 1 +#define D18F3xA0_SviHighFreqSel_MASK 0x200 +#define D18F3xA0_Reserved_15_10_OFFSET 10 +#define D18F3xA0_Reserved_15_10_WIDTH 6 +#define D18F3xA0_Reserved_15_10_MASK 0xfc00 +#define D18F3xA0_ConfigId_OFFSET 16 +#define D18F3xA0_ConfigId_WIDTH 12 +#define D18F3xA0_ConfigId_MASK 0xfff0000 +#define D18F3xA0_Reserved_30_28_OFFSET 28 +#define D18F3xA0_Reserved_30_28_WIDTH 3 +#define D18F3xA0_Reserved_30_28_MASK 0x70000000 +#define D18F3xA0_CofVidProg_OFFSET 31 +#define D18F3xA0_CofVidProg_WIDTH 1 +#define D18F3xA0_CofVidProg_MASK 0x80000000 -/// D0F0x64_x24 +/// D18F3xA0 typedef union { struct { ///< - UINT32 Reserved_28_0:29; ///< - UINT32 SoftOverrideClk1:1 ; ///< - UINT32 SoftOverrideClk0:1 ; ///< - UINT32 Reserved_31_31:1 ; ///< + UINT32 PsiVid:7 ; ///< + UINT32 PsiVidEn:1 ; ///< + UINT32 Reserved_8_8:1 ; ///< + UINT32 SviHighFreqSel:1 ; ///< + UINT32 Reserved_15_10:6 ; ///< + UINT32 ConfigId:12; ///< + UINT32 Reserved_30_28:3 ; ///< + UINT32 CofVidProg:1 ; ///< } Field; ///< UINT32 Value; ///< -} D0F0x64_x24_STRUCT; +} D18F3xA0_STRUCT; +// **** D18F6x110 Register Definition **** +// Address +#define D18F6x110_ADDRESS 0x110 +// Type +#define D18F6x110_TYPE TYPE_D18F6 +// Field Data +#define D18F6x110_NclkFifoOff_OFFSET 0 +#define D18F6x110_NclkFifoOff_WIDTH 3 +#define D18F6x110_NclkFifoOff_MASK 0x7 +#define D18F6x110_Reserved_3_3_OFFSET 3 +#define D18F6x110_Reserved_3_3_WIDTH 1 +#define D18F6x110_Reserved_3_3_MASK 0x8 +#define D18F6x110_LclkFifoOff_OFFSET 4 +#define D18F6x110_LclkFifoOff_WIDTH 3 +#define D18F6x110_LclkFifoOff_MASK 0x70 +#define D18F6x110_Reserved_7_7_OFFSET 7 +#define D18F6x110_Reserved_7_7_WIDTH 1 +#define D18F6x110_Reserved_7_7_MASK 0x80 +#define D18F6x110_PllMult_OFFSET 8 +#define D18F6x110_PllMult_WIDTH 6 +#define D18F6x110_PllMult_MASK 0x3f00 +#define D18F6x110_Reserved_14_14_OFFSET 14 +#define D18F6x110_Reserved_14_14_WIDTH 1 +#define D18F6x110_Reserved_14_14_MASK 0x4000 +#define D18F6x110_Enable_OFFSET 15 +#define D18F6x110_Enable_WIDTH 1 +#define D18F6x110_Enable_MASK 0x8000 +#define D18F6x110_LclkFreq_OFFSET 16 +#define D18F6x110_LclkFreq_WIDTH 7 +#define D18F6x110_LclkFreq_MASK 0x7f0000 +#define D18F6x110_LclkFreqType_OFFSET 23 +#define D18F6x110_LclkFreqType_WIDTH 1 +#define D18F6x110_LclkFreqType_MASK 0x800000 +#define D18F6x110_NclkFreq_OFFSET 24 +#define D18F6x110_NclkFreq_WIDTH 7 +#define D18F6x110_NclkFreq_MASK 0x7f000000 +#define D18F6x110_NclkFreqType_OFFSET 31 +#define D18F6x110_NclkFreqType_WIDTH 1 +#define D18F6x110_NclkFreqType_MASK 0x80000000 + +/// D18F6x110 +typedef union { + struct { ///< + UINT32 NclkFifoOff:3 ; ///< + UINT32 Reserved_3_3:1 ; ///< + UINT32 LclkFifoOff:3 ; ///< + UINT32 Reserved_7_7:1 ; ///< + UINT32 PllMult:6 ; ///< + UINT32 Reserved_14_14:1 ; ///< + UINT32 Enable:1 ; ///< + UINT32 LclkFreq:7 ; ///< + UINT32 LclkFreqType:1 ; ///< + UINT32 NclkFreq:7 ; ///< + UINT32 NclkFreqType:1 ; ///< + } Field; ///< + UINT32 Value; ///< +} D18F6x110_STRUCT; #endif diff --git a/src/vendorcode/amd/agesa/f14/Proc/GNB/Gfx/Family/0x14/F14GfxServices.c b/src/vendorcode/amd/agesa/f14/Proc/GNB/Gfx/Family/0x14/F14GfxServices.c index 139d47cb5a..8d0e84f58b 100644 --- a/src/vendorcode/amd/agesa/f14/Proc/GNB/Gfx/Family/0x14/F14GfxServices.c +++ b/src/vendorcode/amd/agesa/f14/Proc/GNB/Gfx/Family/0x14/F14GfxServices.c @@ -9,7 +9,7 @@ * @xrefitem bom "File Content Label" "Release Content" * @e project: AGESA * @e sub-project: GNB - * @e \$Revision: 39275 $ @e \$Date: 2010-10-09 08:22:05 +0800 (Sat, 09 Oct 2010) $ + * @e \$Revision: 48507 $ @e \$Date: 2011-03-09 13:25:11 -0700 (Wed, 09 Mar 2011) $ * */ /* @@ -52,6 +52,7 @@ #include "AGESA.h" #include "amdlib.h" #include "Ids.h" +#include "heapManager.h" #include "GeneralServices.h" #include "Gnb.h" #include "GnbPcie.h" @@ -60,8 +61,12 @@ #include "GfxIntegratedInfoTableInit.h" #include "GfxRegisterAcc.h" #include "GfxLib.h" +#include "GnbFuseTable.h" #include GNB_MODULE_DEFINITIONS (GnbGfxInitLibV1) -#include "GnbRegistersON.h" +#include "GnbCommonLib.h" +#include "GnbCommonLib.h" +#include "GnbGfxFamServices.h" +#include "GfxFamilyServices.h" #include "F14NbPowerGate.h" #include "cpuFamilyTranslation.h" #include "Filecode.h" @@ -118,6 +123,8 @@ GfxFmMapEngineToDisplayPath ( UINT8 PrimaryDisplayPathId; UINT8 SecondaryDisplayPathId; UINTN DisplayPathIndex; + UINT32 D18F3x1FC; + PrimaryDisplayPathId = 0xff; SecondaryDisplayPathId = 0xff; for (DisplayPathIndex = 0; DisplayPathIndex < (sizeof (DdiLaneConfigArray) / 4); DisplayPathIndex++) { @@ -133,6 +140,21 @@ GfxFmMapEngineToDisplayPath ( // Display config invalid for ON PrimaryDisplayPathId = 0xff; } + + GnbLibPciRead ( + MAKE_SBDFO ( 0, 0, 0x18, 3, 0x1FC), + AccessWidth32, + &D18F3x1FC, + GnbLibGetHeader (Gfx) + ); + + if ((D18F3x1FC & BIT4) == BIT4) { + if (Engine->Type.Ddi.DdiData.ConnectorType == ConnectorTypeAutoDetect || + (Engine->Type.Ddi.DdiData.ConnectorType == ConnectorTypeLvds)) { + PrimaryDisplayPathId = 0xff; + } + } + if (PrimaryDisplayPathId != 0xff) { ASSERT (Engine->Type.Ddi.DdiData.AuxIndex <= Aux3); IDS_HDT_CONSOLE (GFX_MISC, " Allocate Display Connector at Primary sPath[%d]\n", PrimaryDisplayPathId); @@ -187,6 +209,31 @@ GfxFmIntegratedInfoTableInit ( IN GFX_PLATFORM_CONFIG *Gfx ) { + PP_FUSE_ARRAY *PpFuseArray; + D18F4x15C_STRUCT D18F4x15C; + + PpFuseArray = GnbLocateHeapBuffer (AMD_PP_FUSE_TABLE_HANDLE, GnbLibGetHeader (Gfx)); + ASSERT (PpFuseArray != NULL); + if (PpFuseArray != NULL) { + if (PpFuseArray->GpuBoostCap == 1) { + GnbLibPciRead ( + MAKE_SBDFO ( 0, 0, 0x18, 4, D18F4x15C_ADDRESS), + AccessWidth32, + &D18F4x15C.Value, + GnbLibGetHeader (Gfx) + ); + + D18F4x15C.Field.BoostSrc = 1; + + GnbLibPciWrite ( + MAKE_SBDFO ( 0, 0, 0x18, 4, D18F4x15C_ADDRESS), + AccessS3SaveWidth32, + &D18F4x15C.Value, + GnbLibGetHeader (Gfx) + ); + } + } + IntegratedInfoTable->ulDDR_DLL_PowerUpTime = 2380; IntegratedInfoTable->ulDDR_PLL_PowerUpTime = 30000; IntegratedInfoTable->ulGMCRestoreResetTime = F14NbPowerGateGmcRestoreLatency (GnbLibGetHeader (Gfx)); @@ -221,6 +268,49 @@ GfxFmGmcAddressSwizzel ( /*----------------------------------------------------------------------------------------*/ /** + * Initialize Allow_Nb_Pstate High + * + * + * + * @param[in] Gfx Graphics configuration + */ + +VOID +GfxFmGmcAllowPstateHigh ( + IN GFX_PLATFORM_CONFIG *Gfx + ) +{ + GMMxCAC_STRUCT GMMxCAC; + GMMxCCC_STRUCT GMMxCCC; + GMMx6B30_STRUCT GMMx6B30; + GMMx7730_STRUCT GMMx7730; + CPU_LOGICAL_ID LogicalId; + + GetLogicalIdOfCurrentCore (&LogicalId, GnbLibGetHeader (Gfx)); + // + //A workaround for F14 A0. This has be fixed in the future vesions. + // + if ((LogicalId.Revision & AMD_F14_ON_A0) != 0) { + + //For PCIE Enhanced Mode + GMMx6B30.Value = GmmRegisterRead (GMMx6B30_ADDRESS, Gfx); + GMMx7730.Value = GmmRegisterRead (GMMx7730_ADDRESS, Gfx); + GMMx6B30.Field.DcAllowNbPstatesForceOne = 1; + GMMx7730.Field.DcAllowNbPstatesForceOne = 1; + GmmRegisterWrite (GMMx6B30_ADDRESS, GMMx6B30.Value, TRUE, Gfx); + GmmRegisterWrite (GMMx7730_ADDRESS, GMMx7730.Value, TRUE, Gfx); + //For Legacy mode + GMMxCAC.Value = GmmRegisterRead (GMMxCAC_ADDRESS, Gfx); + GMMxCCC.Value = GmmRegisterRead (GMMxCCC_ADDRESS, Gfx); + GMMxCAC.Field.NbPstateChangeForceOn = 1; + GMMxCCC.Field.NbPstateChangeForceOn = 1; + GmmRegisterWrite (GMMxCAC_ADDRESS, GMMxCAC.Value, TRUE, Gfx); + GmmRegisterWrite (GMMxCCC_ADDRESS, GMMxCCC.Value, TRUE, Gfx); + } +} + +/*----------------------------------------------------------------------------------------*/ +/** * Calculate COF for DFS out of Main PLL * * @@ -230,7 +320,7 @@ GfxFmGmcAddressSwizzel ( * @retval COF in 10khz */ -AGESA_STATUS +UINT32 GfxFmCalculateClock ( IN UINT8 Did, IN AMD_CONFIG_PARAMS *StdHeader @@ -240,19 +330,36 @@ GfxFmCalculateClock ( MainPllFreq10kHz = GfxLibGetMainPllFreq (StdHeader) * 100; return GfxLibCalculateClk (Did, MainPllFreq10kHz); } + +/*----------------------------------------------------------------------------------------*/ +/** + * Set idle voltage mode for GFX + * + * + * @param[in] Gfx Pointer to global GFX configuration + */ + +VOID +GfxFmSetIdleVoltageMode ( + IN GFX_PLATFORM_CONFIG *Gfx + ) +{ + +} + /*---------------------------------------------------------------------------------------- * GMC Disable Clock Gating *---------------------------------------------------------------------------------------- */ GMM_REG_ENTRY GmcDisableClockGating[] = { - { 0x20C0, 0x00000C80 }, - { 0x20B8, 0x00000400 }, - { 0x20BC, 0x00000400 }, - { 0x2640, 0x00000400 }, - { 0x263C, 0x00000400 }, - { 0x2638, 0x00000400 }, - { 0x15C0, 0x00081401 } + { GMMx20C0_ADDRESS, 0x00000C80 }, + { GMMx20B8_ADDRESS, 0x00000400 }, + { GMMx20BC_ADDRESS, 0x00000400 }, + { GMMx2640_ADDRESS, 0x00000400 }, + { GMMx263C_ADDRESS, 0x00000400 }, + { GMMx2638_ADDRESS, 0x00000400 }, + { GMMx15C0_ADDRESS, 0x00081401 } }; TABLE_INDIRECT_PTR GmcDisableClockGatingPtr = { @@ -265,13 +372,13 @@ TABLE_INDIRECT_PTR GmcDisableClockGatingPtr = { *---------------------------------------------------------------------------------------- */ GMM_REG_ENTRY GmcEnableClockGating[] = { - { 0x20C0, 0x00040C80 }, - { 0x20B8, 0x00040400 }, - { 0x20BC, 0x00040400 }, - { 0x2640, 0x00040400 }, - { 0x263C, 0x00040400 }, - { 0x2638, 0x00040400 }, - { 0x15C0, 0x000C1401 } + { GMMx20C0_ADDRESS, 0x00040C80 }, + { GMMx20B8_ADDRESS, 0x00040400 }, + { GMMx20BC_ADDRESS, 0x00040400 }, + { GMMx2640_ADDRESS, 0x00040400 }, + { GMMx263C_ADDRESS, 0x00040400 }, + { GMMx2638_ADDRESS, 0x00040400 }, + { GMMx15C0_ADDRESS, 0x000C1401 } }; @@ -318,7 +425,7 @@ TABLE_INDIRECT_PTR GmcPerformanceTuningTablePtr = { GMM_REG_ENTRY GmcMiscInitTable [] = { { GMMx25C8_ADDRESS, 0x007F605F }, { GMMx25CC_ADDRESS, 0x00007F7E }, - { 0x20B4, 0x00000000 }, + { GMMx20B4_ADDRESS, 0x00000000 }, { GMMx28C8_ADDRESS, 0x00000003 }, { GMMx202C_ADDRESS, 0x0003FFFF } }; @@ -334,8 +441,8 @@ TABLE_INDIRECT_PTR GmcMiscInitTablePtr = { */ GMM_REG_ENTRY GmcRemoveBlackoutTable [] = { { GMMx25C0_ADDRESS, 0x00000000 }, - { 0x20EC, 0x000001FC }, - { 0x20D4, 0x00000016 } + { GMMx20EC_ADDRESS, 0x000001FC }, + { GMMx20D4_ADDRESS, 0x00000016 } }; TABLE_INDIRECT_PTR GmcRemoveBlackoutTablePtr = { @@ -410,8 +517,8 @@ GMM_REG_ENTRY GmcRegisterEngineInitTable [] = { { GMMx2B90_ADDRESS, 0x002e09d7 }, { GMMx2B8C_ADDRESS, 0x0000015e }, { GMMx2B90_ADDRESS, 0x00170a26 }, - { 0x2B94, 0x5d976000 }, - { 0x2B98, 0x410af020 } + { GMMx2B94_ADDRESS, 0x5d976000 }, + { GMMx2B98_ADDRESS, 0x410af020 } }; TABLE_INDIRECT_PTR GmcRegisterEngineInitTablePtr = { @@ -483,10 +590,10 @@ REGISTER_COPY_ENTRY CnbToGncRegisterCopyTable [] = { GMMx284C_Dimm0AddrMap_WIDTH + GMMx284C_Dimm1AddrMap_WIDTH }, { - MAKE_SBDFO (0, 0, 0x18, 2, D18F2x094_ADDRESS), + MAKE_SBDFO (0, 0, 0x18, 2, D18F2x94_ADDRESS), GMMx284C_ADDRESS, - D18F2x094_BankSwizzleMode_OFFSET, - D18F2x094_BankSwizzleMode_WIDTH, + D18F2x94_BankSwizzleMode_OFFSET, + D18F2x94_BankSwizzleMode_WIDTH, GMMx284C_BankSwizzleMode_OFFSET, GMMx284C_BankSwizzleMode_WIDTH }, @@ -499,6 +606,14 @@ REGISTER_COPY_ENTRY CnbToGncRegisterCopyTable [] = { GMMx284C_BankSwap_WIDTH }, { + MAKE_SBDFO (0, 0, 0x18, 2, D18F2x110_ADDRESS), + GMMx2854_ADDRESS, + 0, + 31, + 0, + 31 + }, + { MAKE_SBDFO (0, 0, 0x18, 2, D18F2x114_ADDRESS), GMMx2858_ADDRESS, 0, diff --git a/src/vendorcode/amd/agesa/f14/Proc/GNB/Gfx/Family/GfxFamilyServices.h b/src/vendorcode/amd/agesa/f14/Proc/GNB/Gfx/Family/GfxFamilyServices.h index 130f5fc2b3..25a91561c2 100644 --- a/src/vendorcode/amd/agesa/f14/Proc/GNB/Gfx/Family/GfxFamilyServices.h +++ b/src/vendorcode/amd/agesa/f14/Proc/GNB/Gfx/Family/GfxFamilyServices.h @@ -9,7 +9,7 @@ * @xrefitem bom "File Content Label" "Release Content" * @e project: AGESA * @e sub-project: GNB - * @e \$Revision: 39275 $ @e \$Date: 2010-10-09 08:22:05 +0800 (Sat, 09 Oct 2010) $ + * @e \$Revision: 44325 $ @e \$Date: 2010-12-22 03:29:53 -0700 (Wed, 22 Dec 2010) $ * */ /* @@ -58,5 +58,10 @@ GfxFmGmcAddressSwizzel ( IN GFX_PLATFORM_CONFIG *Gfx ); +VOID +GfxFmGmcAllowPstateHigh ( + IN GFX_PLATFORM_CONFIG *Gfx + ); + #endif diff --git a/src/vendorcode/amd/agesa/f14/Proc/GNB/Gfx/GfxConfigData.c b/src/vendorcode/amd/agesa/f14/Proc/GNB/Gfx/GfxConfigData.c index 415dfb7baf..0326f3719e 100644 --- a/src/vendorcode/amd/agesa/f14/Proc/GNB/Gfx/GfxConfigData.c +++ b/src/vendorcode/amd/agesa/f14/Proc/GNB/Gfx/GfxConfigData.c @@ -56,6 +56,7 @@ #include "GnbGfx.h" #include GNB_MODULE_DEFINITIONS (GnbCommonLib) #include "GfxStrapsInit.h" +#include "GfxConfigData.h" #include "OptionGnb.h" #include "Filecode.h" #define FILECODE PROC_GNB_GFX_GFXCONFIGDATA_FILECODE diff --git a/src/vendorcode/amd/agesa/f14/Proc/GNB/Gfx/GfxConfigData.h b/src/vendorcode/amd/agesa/f14/Proc/GNB/Gfx/GfxConfigData.h index 024983fab8..284e01ff23 100644 --- a/src/vendorcode/amd/agesa/f14/Proc/GNB/Gfx/GfxConfigData.h +++ b/src/vendorcode/amd/agesa/f14/Proc/GNB/Gfx/GfxConfigData.h @@ -9,7 +9,7 @@ * @xrefitem bom "File Content Label" "Release Content" * @e project: AGESA * @e sub-project: GNB - * @e \$Revision: 39275 $ @e \$Date: 2010-10-09 08:22:05 +0800 (Sat, 09 Oct 2010) $ + * @e \$Revision: 46545 $ @e \$Date: 2011-02-04 13:42:42 -0700 (Fri, 04 Feb 2011) $ * */ /* @@ -48,19 +48,6 @@ #define _GFXCONFIGDATA_H_ AGESA_STATUS -GfxAllocateConfigData ( - IN AMD_CONFIG_PARAMS *StdHeader, - IN OUT GFX_PLATFORM_CONFIG **Gfx, - IN PLATFORM_CONFIGURATION *PlatformConfig - ); - -AGESA_STATUS -GfxLocateConfigData ( - IN AMD_CONFIG_PARAMS *StdHeader, - OUT GFX_PLATFORM_CONFIG **Gfx - ); - -AGESA_STATUS GfxEnableGmmAccess ( IN OUT GFX_PLATFORM_CONFIG *Gfx ); diff --git a/src/vendorcode/amd/agesa/f14/Proc/GNB/Gfx/GfxGmcInit.c b/src/vendorcode/amd/agesa/f14/Proc/GNB/Gfx/GfxGmcInit.c index c92e8198bd..42828472ca 100644 --- a/src/vendorcode/amd/agesa/f14/Proc/GNB/Gfx/GfxGmcInit.c +++ b/src/vendorcode/amd/agesa/f14/Proc/GNB/Gfx/GfxGmcInit.c @@ -9,7 +9,7 @@ * @xrefitem bom "File Content Label" "Release Content" * @e project: AGESA * @e sub-project: GNB - * @e \$Revision: 39275 $ @e \$Date: 2010-10-09 08:22:05 +0800 (Sat, 09 Oct 2010) $ + * @e \$Revision: 44325 $ @e \$Date: 2010-12-22 03:29:53 -0700 (Wed, 22 Dec 2010) $ * */ /* @@ -71,9 +71,9 @@ /// DCT channel information typedef struct { - D18F2x094_STRUCT D18F2x094; ///< Register 0x94 - D18F2x084_STRUCT D18F2x084; ///< Register 0x84 - D18F2x08C_STRUCT D18F2x08C; ///< Register 0x8C + D18F2x94_STRUCT D18F2x094; ///< Register 0x94 + D18F2x84_STRUCT D18F2x084; ///< Register 0x84 + D18F2x8C_STRUCT D18F2x08C; ///< Register 0x8C D18F2x0F4_x40_STRUCT D18F2x0F4_x40; ///< Register 0x40 D18F2x0F4_x41_STRUCT D18F2x0F4_x41; ///< Register 0x41 } DCT_CHANNEL_INFO; @@ -90,6 +90,88 @@ typedef struct { *---------------------------------------------------------------------------------------- */ +VOID +GfxGmcSetMemoryAddressTranslation ( + IN GFX_PLATFORM_CONFIG *Gfx + ); + +VOID +GfxGmcDisableClockGating ( + IN GFX_PLATFORM_CONFIG *Gfx + ); + +VOID +GfxGmcInitializeRegisterEngine ( + IN GFX_PLATFORM_CONFIG *Gfx + ); + +VOID +GfxGmcDctMemoryChannelInfo ( + IN UINT8 Channel, + OUT DCT_CHANNEL_INFO *DctChannelInfo, + IN GFX_PLATFORM_CONFIG *Gfx + ); + +VOID +GfxGmcInitializeSequencerModel ( + IN GFX_PLATFORM_CONFIG *Gfx + ); + +VOID +GfxGmcInitializeFbLocation ( + IN GFX_PLATFORM_CONFIG *Gfx + ); + +VOID +GfxGmcSecureGarlicAccess ( + IN GFX_PLATFORM_CONFIG *Gfx + ); + +VOID +GfxGmcPerformanceTuning ( + IN GFX_PLATFORM_CONFIG *Gfx + ); + +VOID +GfxGmcMiscInit ( + IN GFX_PLATFORM_CONFIG *Gfx + ); + +VOID +GfxGmcLockCriticalRegisters ( + IN GFX_PLATFORM_CONFIG *Gfx + ); + +VOID +GfxGmcRemoveBlackout ( + IN GFX_PLATFORM_CONFIG *Gfx + ); + +VOID +GfxGmcEnableClockGating ( + IN GFX_PLATFORM_CONFIG *Gfx + ); + +VOID +GfxGmcUmaSteering ( + IN GFX_PLATFORM_CONFIG *Gfx + ); + +VOID +GfxGmcInitializeC6Aperture ( + IN GFX_PLATFORM_CONFIG *Gfx + ); + +VOID +GfxGmcInitializePowerGating ( + IN GFX_PLATFORM_CONFIG *Gfx + ); + +AGESA_STATUS +GfxGmcInit ( + IN GFX_PLATFORM_CONFIG *Gfx + ); + /*---------------------------------------------------------------------------------------- * E X P O R T E D F U N C T I O N S *---------------------------------------------------------------------------------------- @@ -205,35 +287,35 @@ GfxGmcDctMemoryChannelInfo ( ) { GnbLibCpuPciIndirectRead ( - MAKE_SBDFO (0, 0, 0x18, 2, (Channel == 0) ? D18F2x0F0_ADDRESS : D18F2x1F0_ADDRESS), + MAKE_SBDFO (0, 0, 0x18, 2, (Channel == 0) ? D18F2xF0_ADDRESS : D18F2x1F0_ADDRESS), D18F2x0F4_x40_ADDRESS, &DctChannelInfo->D18F2x0F4_x40.Value, GnbLibGetHeader (Gfx) ); GnbLibCpuPciIndirectRead ( - MAKE_SBDFO (0, 0, 0x18, 2, (Channel == 0) ? D18F2x0F0_ADDRESS : D18F2x1F0_ADDRESS), + MAKE_SBDFO (0, 0, 0x18, 2, (Channel == 0) ? D18F2xF0_ADDRESS : D18F2x1F0_ADDRESS), D18F2x0F4_x41_ADDRESS, &DctChannelInfo->D18F2x0F4_x41.Value, GnbLibGetHeader (Gfx) ); GnbLibPciRead ( - MAKE_SBDFO (0, 0, 0x18, 2, (Channel == 0) ? D18F2x084_ADDRESS : D18F2x184_ADDRESS), + MAKE_SBDFO (0, 0, 0x18, 2, (Channel == 0) ? D18F2x84_ADDRESS : D18F2x184_ADDRESS), AccessWidth32, &DctChannelInfo->D18F2x084.Value, GnbLibGetHeader (Gfx) ); GnbLibPciRead ( - MAKE_SBDFO (0, 0, 0x18, 2, (Channel == 0) ? D18F2x094_ADDRESS : D18F2x194_ADDRESS), + MAKE_SBDFO (0, 0, 0x18, 2, (Channel == 0) ? D18F2x94_ADDRESS : D18F2x194_ADDRESS), AccessWidth32, &DctChannelInfo->D18F2x094.Value, GnbLibGetHeader (Gfx) ); GnbLibPciRead ( - MAKE_SBDFO (0, 0, 0x18, 2, (Channel == 0) ? D18F2x08C_ADDRESS : D18F2x18C_ADDRESS), + MAKE_SBDFO (0, 0, 0x18, 2, (Channel == 0) ? D18F2x8C_ADDRESS : D18F2x18C_ADDRESS), AccessWidth32, &DctChannelInfo->D18F2x08C.Value, GnbLibGetHeader (Gfx) @@ -717,6 +799,8 @@ GfxGmcInit ( GfxGmcEnableClockGating (Gfx); } GfxGmcInitializePowerGating (Gfx); + GfxFmGmcAllowPstateHigh (Gfx); IDS_HDT_CONSOLE (GNB_TRACE, "GfxGmcInit Exit\n"); return Status; } + diff --git a/src/vendorcode/amd/agesa/f14/Proc/GNB/Gfx/GfxInitAtMidPost.c b/src/vendorcode/amd/agesa/f14/Proc/GNB/Gfx/GfxInitAtMidPost.c index d9ca4c1c36..1ca08e4bfc 100644 --- a/src/vendorcode/amd/agesa/f14/Proc/GNB/Gfx/GfxInitAtMidPost.c +++ b/src/vendorcode/amd/agesa/f14/Proc/GNB/Gfx/GfxInitAtMidPost.c @@ -52,12 +52,14 @@ #include "amdlib.h" #include "Ids.h" #include "Gnb.h" +#include "GnbPcie.h" #include "GnbGfx.h" #include GNB_MODULE_DEFINITIONS (GnbGfxConfig) #include "GfxConfigData.h" #include "GfxStrapsInit.h" #include "GfxGmcInit.h" #include "GfxInitAtMidPost.h" +#include "GnbGfxFamServices.h" #include "Filecode.h" #define FILECODE PROC_GNB_GFX_GFXINITATMIDPOST_FILECODE /*---------------------------------------------------------------------------------------- @@ -78,7 +80,6 @@ */ - /*----------------------------------------------------------------------------------------*/ /** * Init GFX at Mid Post. @@ -124,7 +125,7 @@ GfxInitAtMidPost ( AGESA_STATUS_UPDATE (Status, AgesaStatus); } } - GfxSetIdleVoltageMode (Gfx); + GfxFmSetIdleVoltageMode (Gfx); } IDS_HDT_CONSOLE (GNB_TRACE, "GfxInitAtMidPost Exit [0x%x]\n", AgesaStatus); return AgesaStatus; diff --git a/src/vendorcode/amd/agesa/f14/Proc/GNB/Gfx/GfxInitAtPost.c b/src/vendorcode/amd/agesa/f14/Proc/GNB/Gfx/GfxInitAtPost.c index 891dcdf4eb..3bfa8a4431 100644 --- a/src/vendorcode/amd/agesa/f14/Proc/GNB/Gfx/GfxInitAtPost.c +++ b/src/vendorcode/amd/agesa/f14/Proc/GNB/Gfx/GfxInitAtPost.c @@ -55,6 +55,7 @@ #include "GnbPcie.h" #include "GnbGfx.h" #include GNB_MODULE_DEFINITIONS (GnbGfxInitLibV1) +#include GNB_MODULE_DEFINITIONS (GnbGfxConfig) #include "GfxStrapsInit.h" #include "GfxLib.h" #include "GfxConfigData.h" diff --git a/src/vendorcode/amd/agesa/f14/Proc/GNB/Gfx/GfxIntegratedInfoTableInit.c b/src/vendorcode/amd/agesa/f14/Proc/GNB/Gfx/GfxIntegratedInfoTableInit.c index 2c525fab53..a3db0c15e8 100644 --- a/src/vendorcode/amd/agesa/f14/Proc/GNB/Gfx/GfxIntegratedInfoTableInit.c +++ b/src/vendorcode/amd/agesa/f14/Proc/GNB/Gfx/GfxIntegratedInfoTableInit.c @@ -9,7 +9,7 @@ * @xrefitem bom "File Content Label" "Release Content" * @e project: AGESA * @e sub-project: GNB - * @e \$Revision: 41507 $ @e \$Date: 2010-11-05 23:13:47 +0800 (Fri, 05 Nov 2010) $ + * @e \$Revision: 48924 $ @e \$Date: 2011-03-14 12:45:15 -0600 (Mon, 14 Mar 2011) $ * */ /* @@ -65,6 +65,7 @@ #include "GfxConfigData.h" #include "GfxRegisterAcc.h" #include "GfxFamilyServices.h" +#include "GnbGfxFamServices.h" #include "GfxIntegratedInfoTableInit.h" #include "GnbRegistersON.h" #include "Filecode.h" @@ -81,14 +82,6 @@ *---------------------------------------------------------------------------------------- */ - - - -/*---------------------------------------------------------------------------------------- - * P R O T O T Y P E S O F L O C A L F U N C T I O N S - *---------------------------------------------------------------------------------------- - */ - ULONG ulCSR_M3_ARB_CNTL_DEFAULT[] = { 0x80040810, 0x00040810, @@ -131,6 +124,29 @@ ULONG ulCSR_M3_ARB_CNTL_FS3D[] = { }; + +/*---------------------------------------------------------------------------------------- + * P R O T O T Y P E S O F L O C A L F U N C T I O N S + *---------------------------------------------------------------------------------------- + */ + +UINT32 +GfxLibGetCsrPhySrPllPdMode ( + IN UINT8 Channel, + IN AMD_CONFIG_PARAMS *StdHeader + ); + +AGESA_STATUS +GfxIntegratedInfoTableEntry ( + IN AMD_CONFIG_PARAMS *StdHeader + ); + +UINT32 +GfxLibGetDisDllShutdownSR ( + IN UINT8 Channel, + IN AMD_CONFIG_PARAMS *StdHeader + ); + VOID GfxIntegratedInfoInitDispclkTable ( IN PP_FUSE_ARRAY *PpFuseArray, @@ -199,7 +215,7 @@ GfxLibGetCsrPhySrPllPdMode ( D18F2x09C_x0D0FE00A_STRUCT D18F2x09C_x0D0FE00A; GnbLibCpuPciIndirectRead ( - MAKE_SBDFO ( 0, 0, 0x18, 2, (Channel == 0) ? D18F2x098_ADDRESS : D18F2x198_ADDRESS), + MAKE_SBDFO ( 0, 0, 0x18, 2, (Channel == 0) ? D18F2x98_ADDRESS : D18F2x198_ADDRESS), D18F2x09C_x0D0FE00A_ADDRESS, &D18F2x09C_x0D0FE00A.Value, StdHeader @@ -223,10 +239,10 @@ GfxLibGetDisDllShutdownSR ( IN AMD_CONFIG_PARAMS *StdHeader ) { - D18F2x090_STRUCT D18F2x090; + D18F2x90_STRUCT D18F2x090; GnbLibPciRead ( - MAKE_SBDFO ( 0, 0, 0x18, 2, (Channel == 0) ? D18F2x090_ADDRESS : D18F2x190_ADDRESS), + MAKE_SBDFO ( 0, 0, 0x18, 2, (Channel == 0) ? D18F2x90_ADDRESS : D18F2x190_ADDRESS), AccessWidth32, &D18F2x090.Value, StdHeader @@ -308,6 +324,8 @@ GfxIntegratedInfoTableInit ( SystemInfoV1Table.sIntegratedSysInfo.usLvdsSSPercentage = Gfx->LvdsSpreadSpectrum; SystemInfoV1Table.sIntegratedSysInfo.usLvdsSSpreadRateIn10Hz = Gfx->LvdsSpreadSpectrumRate; + SystemInfoV1Table.sIntegratedSysInfo.usPCIEClkSSPercentage = Gfx->PcieRefClkSpreadSpectrum; +// SystemInfoV1Table.sIntegratedSysInfo.ucLvdsMisc = Gfx->LvdsMiscControl.Value; //Locate PCIe configuration data to get definitions of display connectors SystemInfoV1Table.sIntegratedSysInfo.sExtDispConnInfo.sHeader.usStructureSize = sizeof (ATOM_EXTERNAL_DISPLAY_CONNECTION_INFO); @@ -424,6 +442,9 @@ GfxIntegratedInfoInitSclkTable ( ) { UINTN Index; + UINTN TargetIndex; + UINTN ValidSclkStateMask; + UINT8 TempDID; UINT8 SclkVidArray[4]; UINTN AvailSclkIndex; ATOM_AVAILABLE_SCLK_LIST *AvailSclkList; @@ -466,6 +487,33 @@ GfxIntegratedInfoInitSclkTable ( } } } while (Sorting); + + if (PpFuseArray->GpuBoostCap == 1) { + IntegratedInfoTable->SclkDpmThrottleMargin = PpFuseArray->SclkDpmThrottleMargin; + IntegratedInfoTable->SclkDpmTdpLimitPG = PpFuseArray->SclkDpmTdpLimitPG; + IntegratedInfoTable->EnableBoost = PpFuseArray->GpuBoostCap; + IntegratedInfoTable->SclkDpmBoostMargin = PpFuseArray->SclkDpmBoostMargin; + IntegratedInfoTable->SclkDpmTdpLimitBoost = (PpFuseArray->SclkDpmTdpLimit)[5]; + IntegratedInfoTable->ulBoostEngineCLock = GfxFmCalculateClock ((PpFuseArray->SclkDpmDid)[5], GnbLibGetHeader (Gfx)); + IntegratedInfoTable->ulBoostVid_2bit = (PpFuseArray->SclkDpmVid)[5]; + + ValidSclkStateMask = 0; + TargetIndex = 0; + for (Index = 0; Index < 6; Index++) { + ValidSclkStateMask |= (PpFuseArray->SclkDpmValid)[Index]; + } + TempDID = 0x7F; + for (Index = 0; Index < 6; Index++) { + if ((ValidSclkStateMask & ((UINTN)1 << Index)) != 0) { + if ((PpFuseArray->SclkDpmDid)[Index] <= TempDID) { + TempDID = (PpFuseArray->SclkDpmDid)[Index]; + TargetIndex = Index; + } + } + } + IntegratedInfoTable->GnbTdpLimit = (PpFuseArray->SclkDpmTdpLimit)[TargetIndex]; + } + } /*----------------------------------------------------------------------------------------*/ @@ -491,8 +539,8 @@ GfxFillHtcData ( &D18F3x64.Value, GnbLibGetHeader (Gfx) ); - IntegratedInfoTable->ucHtcTmpLmt = (UCHAR)D18F3x64.Field.HtcTmpLmt; - IntegratedInfoTable->ucHtcHystLmt = (UCHAR)D18F3x64.Field.HtcHystLmt; + IntegratedInfoTable->ucHtcTmpLmt = (UCHAR) (D18F3x64.Field.HtcTmpLmt / 2 + 52); + IntegratedInfoTable->ucHtcHystLmt = (UCHAR) (D18F3x64.Field.HtcHystLmt / 2); } /*----------------------------------------------------------------------------------------*/ diff --git a/src/vendorcode/amd/agesa/f14/Proc/GNB/Gfx/GfxStrapsInit.c b/src/vendorcode/amd/agesa/f14/Proc/GNB/Gfx/GfxStrapsInit.c index 350e9b6bf5..06a780b21b 100644 --- a/src/vendorcode/amd/agesa/f14/Proc/GNB/Gfx/GfxStrapsInit.c +++ b/src/vendorcode/amd/agesa/f14/Proc/GNB/Gfx/GfxStrapsInit.c @@ -9,7 +9,7 @@ * @xrefitem bom "File Content Label" "Release Content" * @e project: AGESA * @e sub-project: GNB - * @e \$Revision: 40151 $ @e \$Date: 2010-10-20 06:38:17 +0800 (Wed, 20 Oct 2010) $ + * @e \$Revision: 44325 $ @e \$Date: 2010-12-22 03:29:53 -0700 (Wed, 22 Dec 2010) $ * */ /* @@ -298,18 +298,3 @@ GfxSetBootUpVoltage ( IDS_HDT_CONSOLE (GNB_TRACE, "GfxSetBootUpVoltage Exit\n"); return AGESA_SUCCESS; } - -/*----------------------------------------------------------------------------------------*/ -/** - * Set idle voltage mode for GFX - * - * - * @param[in] Gfx Pointer to global GFX configuration - */ - -VOID -GfxSetIdleVoltageMode ( - IN GFX_PLATFORM_CONFIG *Gfx - ) -{ -} diff --git a/src/vendorcode/amd/agesa/f14/Proc/GNB/Gfx/GfxStrapsInit.h b/src/vendorcode/amd/agesa/f14/Proc/GNB/Gfx/GfxStrapsInit.h index 9954934b71..4ca1e58775 100644 --- a/src/vendorcode/amd/agesa/f14/Proc/GNB/Gfx/GfxStrapsInit.h +++ b/src/vendorcode/amd/agesa/f14/Proc/GNB/Gfx/GfxStrapsInit.h @@ -69,10 +69,5 @@ GfxSetBootUpVoltage ( IN GFX_PLATFORM_CONFIG *Gfx ); -VOID -GfxSetIdleVoltageMode ( - IN GFX_PLATFORM_CONFIG *Gfx - ); - #endif diff --git a/src/vendorcode/amd/agesa/f14/Proc/GNB/GnbInitAtEarly.c b/src/vendorcode/amd/agesa/f14/Proc/GNB/GnbInitAtEarly.c index 730a5004ad..d9a2d7e133 100644 --- a/src/vendorcode/amd/agesa/f14/Proc/GNB/GnbInitAtEarly.c +++ b/src/vendorcode/amd/agesa/f14/Proc/GNB/GnbInitAtEarly.c @@ -54,6 +54,7 @@ #include "OptionGnb.h" #include "GnbLibFeatures.h" +#include "GnbInterface.h" #include "Filecode.h" #define FILECODE PROC_GNB_GNBINITATEARLY_FILECODE diff --git a/src/vendorcode/amd/agesa/f14/Proc/GNB/GnbInitAtEnv.c b/src/vendorcode/amd/agesa/f14/Proc/GNB/GnbInitAtEnv.c index cb632c85ce..139ac3e17c 100644 --- a/src/vendorcode/amd/agesa/f14/Proc/GNB/GnbInitAtEnv.c +++ b/src/vendorcode/amd/agesa/f14/Proc/GNB/GnbInitAtEnv.c @@ -9,7 +9,7 @@ * @xrefitem bom "File Content Label" "Release Content" * @e project: AGESA * @e sub-project: GNB - * @e \$Revision: 41504 $ @e \$Date: 2010-11-05 21:59:13 +0800 (Fri, 05 Nov 2010) $ + * @e \$Revision: 47417 $ @e \$Date: 2011-02-18 12:48:20 -0700 (Fri, 18 Feb 2011) $ * */ /* @@ -52,6 +52,7 @@ #include "Gnb.h" #include "OptionGnb.h" #include "GnbLibFeatures.h" +#include "GnbInterface.h" #include "Filecode.h" #define FILECODE PROC_GNB_GNBINITATENV_FILECODE /*---------------------------------------------------------------------------------------- @@ -89,6 +90,9 @@ GnbInitDataStructAtEnvDef ( GnbEnvConfigPtr->Gnb3dStereoPinIndex = UserOptions.CfgGnb3dStereoPinIndex; GnbEnvConfigPtr->LvdsSpreadSpectrum = UserOptions.CfgLvdsSpreadSpectrum; GnbEnvConfigPtr->LvdsSpreadSpectrumRate = UserOptions.CfgLvdsSpreadSpectrumRate; + GnbEnvConfigPtr->LvdsMiscControl.Value = 0; + GnbEnvConfigPtr->LvdsMiscControl.Value = UserOptions.CfgLvdsMiscControl.Value; + GnbEnvConfigPtr->PcieRefClkSpreadSpectrum = UserOptions.CfgPcieRefClkSpreadSpectrum; } /*----------------------------------------------------------------------------------------*/ diff --git a/src/vendorcode/amd/agesa/f14/Proc/GNB/GnbInitAtLate.c b/src/vendorcode/amd/agesa/f14/Proc/GNB/GnbInitAtLate.c index 2d3f8fc457..8db9a1b422 100644 --- a/src/vendorcode/amd/agesa/f14/Proc/GNB/GnbInitAtLate.c +++ b/src/vendorcode/amd/agesa/f14/Proc/GNB/GnbInitAtLate.c @@ -52,6 +52,7 @@ #include "Gnb.h" #include "OptionGnb.h" #include "GnbLibFeatures.h" +#include "GnbInterface.h" #include "Filecode.h" #define FILECODE PROC_GNB_GNBINITATLATE_FILECODE /*---------------------------------------------------------------------------------------- diff --git a/src/vendorcode/amd/agesa/f14/Proc/GNB/GnbInitAtMid.c b/src/vendorcode/amd/agesa/f14/Proc/GNB/GnbInitAtMid.c index 867691bda4..f2ede888c5 100644 --- a/src/vendorcode/amd/agesa/f14/Proc/GNB/GnbInitAtMid.c +++ b/src/vendorcode/amd/agesa/f14/Proc/GNB/GnbInitAtMid.c @@ -52,6 +52,7 @@ #include "Gnb.h" #include "OptionGnb.h" #include "GnbLibFeatures.h" +#include "GnbInterface.h" #include "Filecode.h" #define FILECODE PROC_GNB_GNBINITATMID_FILECODE /*---------------------------------------------------------------------------------------- diff --git a/src/vendorcode/amd/agesa/f14/Proc/GNB/GnbInitAtPost.c b/src/vendorcode/amd/agesa/f14/Proc/GNB/GnbInitAtPost.c index bbb26c64b8..ce5209f717 100644 --- a/src/vendorcode/amd/agesa/f14/Proc/GNB/GnbInitAtPost.c +++ b/src/vendorcode/amd/agesa/f14/Proc/GNB/GnbInitAtPost.c @@ -53,6 +53,7 @@ #include "OptionGnb.h" #include "Ids.h" #include "GnbLibFeatures.h" +#include "GnbInterface.h" #include "Filecode.h" #define FILECODE PROC_GNB_GNBINITATPOST_FILECODE /*---------------------------------------------------------------------------------------- diff --git a/src/vendorcode/amd/agesa/f14/Proc/GNB/GnbInitAtReset.c b/src/vendorcode/amd/agesa/f14/Proc/GNB/GnbInitAtReset.c index 72104891b5..c903bf4e9e 100644 --- a/src/vendorcode/amd/agesa/f14/Proc/GNB/GnbInitAtReset.c +++ b/src/vendorcode/amd/agesa/f14/Proc/GNB/GnbInitAtReset.c @@ -50,6 +50,7 @@ */ #include "AGESA.h" #include "Gnb.h" +#include "GnbInterface.h" #include "Filecode.h" #define FILECODE PROC_GNB_GNBINITATRESET_FILECODE /*---------------------------------------------------------------------------------------- diff --git a/src/vendorcode/amd/agesa/f14/Proc/GNB/Modules/GnbCommonLib/GnbLib.c b/src/vendorcode/amd/agesa/f14/Proc/GNB/Modules/GnbCommonLib/GnbLib.c index 5e8b67e603..8f983dbe70 100644 --- a/src/vendorcode/amd/agesa/f14/Proc/GNB/Modules/GnbCommonLib/GnbLib.c +++ b/src/vendorcode/amd/agesa/f14/Proc/GNB/Modules/GnbCommonLib/GnbLib.c @@ -74,6 +74,15 @@ * P R O T O T Y P E S O F L O C A L F U N C T I O N S *---------------------------------------------------------------------------------------- */ +VOID +GnbLibPciIndirectReadField ( + IN UINT32 Address, + IN UINT32 IndirectAddress, + IN UINT8 FieldOffset, + IN UINT8 FieldWidth, + OUT UINT32 *Value, + IN VOID *Config + ); /*----------------------------------------------------------------------------------------*/ diff --git a/src/vendorcode/amd/agesa/f14/Proc/GNB/Modules/GnbCommonLib/GnbLibCpuAcc.c b/src/vendorcode/amd/agesa/f14/Proc/GNB/Modules/GnbCommonLib/GnbLibCpuAcc.c index 8b9b93f428..f8743587a4 100644 --- a/src/vendorcode/amd/agesa/f14/Proc/GNB/Modules/GnbCommonLib/GnbLibCpuAcc.c +++ b/src/vendorcode/amd/agesa/f14/Proc/GNB/Modules/GnbCommonLib/GnbLibCpuAcc.c @@ -51,6 +51,7 @@ #include "Porting.h" #include "AMD.h" #include "GnbLibPciAcc.h" +#include "GnbLibCpuAcc.h" #include "Filecode.h" #define FILECODE PROC_GNB_MODULES_GNBCOMMONLIB_GNBLIBCPUACC_FILECODE /*---------------------------------------------------------------------------------------- diff --git a/src/vendorcode/amd/agesa/f14/Proc/GNB/Modules/GnbCommonLib/GnbLibHeap.c b/src/vendorcode/amd/agesa/f14/Proc/GNB/Modules/GnbCommonLib/GnbLibHeap.c index 5890ffe3a4..0f45f7d557 100644 --- a/src/vendorcode/amd/agesa/f14/Proc/GNB/Modules/GnbCommonLib/GnbLibHeap.c +++ b/src/vendorcode/amd/agesa/f14/Proc/GNB/Modules/GnbCommonLib/GnbLibHeap.c @@ -52,6 +52,7 @@ #include "AMD.h" #include "heapManager.h" #include "GnbLibPciAcc.h" +#include "GnbLibHeap.h" #include "Filecode.h" #define FILECODE PROC_GNB_MODULES_GNBCOMMONLIB_GNBLIBHEAP_FILECODE /*---------------------------------------------------------------------------------------- diff --git a/src/vendorcode/amd/agesa/f14/Proc/GNB/Modules/GnbCommonLib/GnbLibPci.h b/src/vendorcode/amd/agesa/f14/Proc/GNB/Modules/GnbCommonLib/GnbLibPci.h index df5e47e37b..6e5d1f3c40 100644 --- a/src/vendorcode/amd/agesa/f14/Proc/GNB/Modules/GnbCommonLib/GnbLibPci.h +++ b/src/vendorcode/amd/agesa/f14/Proc/GNB/Modules/GnbCommonLib/GnbLibPci.h @@ -78,7 +78,7 @@ typedef SCAN_STATUS (*GNB_SCAN_CALLBACK) ( typedef struct _GNB_PCI_SCAN_DATA { GNB_SCAN_CALLBACK GnbScanCallback; ///< Callback for each found device AMD_CONFIG_PARAMS *StdHeader; ///< Standard configuration header -}; +} Unused_GNB_PCI_SCAN_DATA; #define PCIE_CAP_ID 0x10 #define PCIE_LINK_CAP_REGISTER 0x0C @@ -117,6 +117,13 @@ GnbLibFindPciCapability ( IN AMD_CONFIG_PARAMS *StdHeader ); +UINT16 +GnbLibFindPcieExtendedCapability ( + IN UINT32 Address, + IN UINT16 ExtendedCapabilityId, + IN AMD_CONFIG_PARAMS *StdHeader + ); + VOID GnbLibPciScan ( IN PCI_ADDR Start, diff --git a/src/vendorcode/amd/agesa/f14/Proc/GNB/Modules/GnbGfxConfig/GfxConfigEnv.c b/src/vendorcode/amd/agesa/f14/Proc/GNB/Modules/GnbGfxConfig/GfxConfigEnv.c index 38e4b6abcd..dc73e2d26d 100644 --- a/src/vendorcode/amd/agesa/f14/Proc/GNB/Modules/GnbGfxConfig/GfxConfigEnv.c +++ b/src/vendorcode/amd/agesa/f14/Proc/GNB/Modules/GnbGfxConfig/GfxConfigEnv.c @@ -54,7 +54,9 @@ #include "heapManager.h" #include "Gnb.h" #include "GnbGfx.h" +#include "GnbGfxConfig.h" #include GNB_MODULE_DEFINITIONS (GnbCommonLib) +#include "GfxConfigData.h" #include "GfxConfigPost.h" #include "OptionGnb.h" #include "Filecode.h" @@ -77,6 +79,10 @@ extern GNB_BUILD_OPTIONS GnbBuildOptions; * P R O T O T Y P E S O F L O C A L F U N C T I O N S *---------------------------------------------------------------------------------------- */ +AGESA_STATUS +GfxConfigEnvInterface ( + IN AMD_CONFIG_PARAMS *StdHeader + ); @@ -133,7 +139,7 @@ GfxLocateConfigData ( IDS_ERROR_TRAP; return AGESA_FATAL; } - (*Gfx)->StdHeader = (PVOID) StdHeader; + (*Gfx)->StdHeader = StdHeader; return AGESA_SUCCESS; } @@ -166,6 +172,8 @@ GfxConfigEnvInterface ( Gfx->Gnb3dStereoPinIndex = EnvParamsPtr->GnbEnvConfiguration.Gnb3dStereoPinIndex; Gfx->LvdsSpreadSpectrum = EnvParamsPtr->GnbEnvConfiguration.LvdsSpreadSpectrum; Gfx->LvdsSpreadSpectrumRate = EnvParamsPtr->GnbEnvConfiguration.LvdsSpreadSpectrumRate; + Gfx->LvdsMiscControl.Value = EnvParamsPtr->GnbEnvConfiguration.LvdsMiscControl.Value; + Gfx->PcieRefClkSpreadSpectrum = EnvParamsPtr->GnbEnvConfiguration.PcieRefClkSpreadSpectrum; GfxGetUmaInfo (&Gfx->UmaInfo, StdHeader); } GNB_DEBUG_CODE ( diff --git a/src/vendorcode/amd/agesa/f14/Proc/GNB/Modules/GnbGfxConfig/GfxConfigPost.c b/src/vendorcode/amd/agesa/f14/Proc/GNB/Modules/GnbGfxConfig/GfxConfigPost.c index 12a8dc6bd4..a8d4957992 100644 --- a/src/vendorcode/amd/agesa/f14/Proc/GNB/Modules/GnbGfxConfig/GfxConfigPost.c +++ b/src/vendorcode/amd/agesa/f14/Proc/GNB/Modules/GnbGfxConfig/GfxConfigPost.c @@ -77,6 +77,10 @@ extern GNB_BUILD_OPTIONS GnbBuildOptions; * P R O T O T Y P E S O F L O C A L F U N C T I O N S *---------------------------------------------------------------------------------------- */ +AGESA_STATUS +GfxConfigPostInterface ( + IN AMD_CONFIG_PARAMS *StdHeader + ); /*----------------------------------------------------------------------------------------*/ @@ -113,7 +117,7 @@ GfxConfigPostInterface ( Gfx->GfxControllerMode = GfxControllerLegacyBridgeMode; Gfx->GfxPciAddress.AddressValue = MAKE_SBDFO (0, 1, 5, 0, 0); } - Gfx->StdHeader = (PVOID) StdHeader; + Gfx->StdHeader = StdHeader; Gfx->GnbHdAudio = PostParamsPtr->PlatformConfig.GnbHdAudio; Gfx->AbmSupport = PostParamsPtr->PlatformConfig.AbmSupport; Gfx->DynamicRefreshRate = PostParamsPtr->PlatformConfig.DynamicRefreshRate; diff --git a/src/vendorcode/amd/agesa/f14/Proc/GNB/Modules/GnbGfxInitLibV1/GfxEnumConnectors.c b/src/vendorcode/amd/agesa/f14/Proc/GNB/Modules/GnbGfxInitLibV1/GfxEnumConnectors.c index 0a0828ee32..453576d623 100644 --- a/src/vendorcode/amd/agesa/f14/Proc/GNB/Modules/GnbGfxInitLibV1/GfxEnumConnectors.c +++ b/src/vendorcode/amd/agesa/f14/Proc/GNB/Modules/GnbGfxInitLibV1/GfxEnumConnectors.c @@ -59,6 +59,7 @@ #include GNB_MODULE_DEFINITIONS (GnbPcieInitLibV1) #include GNB_MODULE_DEFINITIONS (GnbPcieConfig) #include "GnbGfxFamServices.h" +#include "GfxEnumConnectors.h" #include "GnbRegistersON.h" #include "Filecode.h" #define FILECODE PROC_GNB_MODULES_GNBGFXINITLIBV1_GFXENUMCONNECTORS_FILECODE @@ -104,6 +105,17 @@ typedef struct { *---------------------------------------------------------------------------------------- */ +EXT_CONNECTOR_INFO* +GfxIntegratedExtConnectorInfo ( + IN UINT8 ConnectorType + ); + +EXT_DISPLAY_DEVICE_INFO* +GfxIntegratedExtDisplayDeviceInfo ( + IN UINT8 DisplayDeviceEnum, + IN UINT8 DisplayDeviceIndex + ); + AGESA_STATUS GfxIntegratedEnumConnectorsForDevice ( IN UINT8 DisplayDeviceEnum, diff --git a/src/vendorcode/amd/agesa/f14/Proc/GNB/Modules/GnbGfxInitLibV1/GfxPowerPlayTable.c b/src/vendorcode/amd/agesa/f14/Proc/GNB/Modules/GnbGfxInitLibV1/GfxPowerPlayTable.c index e42a83f675..feb612305f 100644 --- a/src/vendorcode/amd/agesa/f14/Proc/GNB/Modules/GnbGfxInitLibV1/GfxPowerPlayTable.c +++ b/src/vendorcode/amd/agesa/f14/Proc/GNB/Modules/GnbGfxInitLibV1/GfxPowerPlayTable.c @@ -91,12 +91,81 @@ typedef struct { BOOLEAN Valid; ///< State valid UINT32 Sclk; ///< Sclk in kHz UINT8 Vid; ///< VID index + UINT16 Tdp; ///< Tdp limit } DPM_STATE; /*---------------------------------------------------------------------------------------- * P R O T O T Y P E S O F L O C A L F U N C T I O N S *---------------------------------------------------------------------------------------- */ +UINT16 +GfxPowerPlayLocateTdp ( + IN PP_FUSE_ARRAY *PpFuses, + IN UINT32 Sclk, + IN AMD_CONFIG_PARAMS *StdHeader + ); + +SW_STATE* +GfxPowerPlayCreateSwState ( + IN OUT SW_STATE *SwStateArray + ); + +UINT8 +GfxPowerPlayCreateDpmState ( + IN DPM_STATE *DpmStateArray, + IN UINT32 Sclk, + IN UINT8 Vid, + IN UINT16 Tdp + ); + +UINT8 +GfxPowerPlayAddDpmState ( + IN DPM_STATE *DpmStateArray, + IN UINT32 Sclk, + IN UINT8 Vid, + IN UINT16 Tdp + ); + +VOID +GfxPowerPlayAddDpmStateToSwState ( + IN OUT SW_STATE *SwStateArray, + IN UINT8 DpmStateIndex + ); + +UINT32 +GfxPowerPlayCopyStateInfo ( + IN OUT STATE_ARRAY *StateArray, + IN SW_STATE *SwStateArray, + IN AMD_CONFIG_PARAMS *StdHeader + ); + +UINT32 +GfxPowerPlayCopyClockInfo ( + IN CLOCK_INFO_ARRAY *ClockInfoArray, + IN DPM_STATE *DpmStateArray, + IN AMD_CONFIG_PARAMS *StdHeader + ); + +UINT32 +GfxPowerPlayCopyNonClockInfo ( + IN NON_CLOCK_INFO_ARRAY *NonClockInfoArray, + IN SW_STATE *SwStateArray, + IN AMD_CONFIG_PARAMS *StdHeader + ); + +BOOLEAN +GfxPowerPlayIsFusedStateValid ( + IN UINT8 Index, + IN PP_FUSE_ARRAY *PpFuses, + IN GFX_PLATFORM_CONFIG *Gfx + ); + +UINT16 +GfxPowerPlayGetClassificationFromFuses ( + IN UINT8 Index, + IN PP_FUSE_ARRAY *PpFuses, + IN GFX_PLATFORM_CONFIG *Gfx + ); VOID GfxIntegratedDebugDumpPpTable ( @@ -106,6 +175,45 @@ GfxIntegratedDebugDumpPpTable ( /*----------------------------------------------------------------------------------------*/ /** + * Locate existing tdp + * + * + * @param[in ] PpFuses Pointer to PP_FUSE_ARRAY + * @param[in] Sclk Sclk in 10kHz + * @param[in] StdHeader Standard configuration header + * @retval Tdp limit in DPM state array + */ + +UINT16 +GfxPowerPlayLocateTdp ( + IN PP_FUSE_ARRAY *PpFuses, + IN UINT32 Sclk, + IN AMD_CONFIG_PARAMS *StdHeader + ) +{ + UINT8 Index; + UINT32 DpmIndex; + UINT32 DpmSclk; + UINT32 DeltaSclk; + UINT32 MinDeltaSclk; + + DpmIndex = 0; + MinDeltaSclk = 0xFFFFFFFF; + for (Index = 0; Index < MAX_NUM_OF_FUSED_DPM_STATES; Index++) { + if (PpFuses->SclkDpmDid[Index] != 0) { + DpmSclk = GfxFmCalculateClock (PpFuses->SclkDpmDid[Index], StdHeader); + DeltaSclk = (DpmSclk > Sclk) ? (DpmSclk - Sclk) : (Sclk - DpmSclk); + if (DeltaSclk < MinDeltaSclk) { + MinDeltaSclk = MinDeltaSclk; + DpmIndex = Index; + } + } + } + return PpFuses->SclkDpmTdpLimit[DpmIndex]; +} + +/*----------------------------------------------------------------------------------------*/ +/** * Create new software state * * @@ -136,6 +244,7 @@ GfxPowerPlayCreateSwState ( * @param[in, out] DpmStateArray Pointer to DPM state array * @param[in] Sclk SCLK in kHz * @param[in] Vid Vid index + * @param[in] Tdp Tdp limit * @retval Index of state entry in DPM state array */ @@ -143,7 +252,8 @@ UINT8 GfxPowerPlayCreateDpmState ( IN DPM_STATE *DpmStateArray, IN UINT32 Sclk, - IN UINT8 Vid + IN UINT8 Vid, + IN UINT16 Tdp ) { UINT8 Index; @@ -152,6 +262,7 @@ GfxPowerPlayCreateDpmState ( DpmStateArray[Index].Sclk = Sclk; DpmStateArray[Index].Vid = Vid; DpmStateArray[Index].Valid = TRUE; + DpmStateArray[Index].Tdp = Tdp; return Index; } } @@ -166,6 +277,7 @@ GfxPowerPlayCreateDpmState ( * @param[in, out] DpmStateArray Pointer to DPM state array * @param[in] Sclk SCLK in kHz * @param[in] Vid Vid index + * @param[in] Tdp Tdp limit * @retval Index of state entry in DPM state array */ @@ -173,7 +285,8 @@ UINT8 GfxPowerPlayAddDpmState ( IN DPM_STATE *DpmStateArray, IN UINT32 Sclk, - IN UINT8 Vid + IN UINT8 Vid, + IN UINT16 Tdp ) { UINT8 Index; @@ -182,7 +295,7 @@ GfxPowerPlayAddDpmState ( return Index; } } - return GfxPowerPlayCreateDpmState (DpmStateArray, Sclk, Vid); + return GfxPowerPlayCreateDpmState (DpmStateArray, Sclk, Vid, Tdp); } /*----------------------------------------------------------------------------------------*/ @@ -250,7 +363,6 @@ GfxPowerPlayCopyStateInfo ( * @param[in] DpmStateArray Pointer to DPM state array * @param[in] StdHeader Standard configuration header */ - UINT32 GfxPowerPlayCopyClockInfo ( IN CLOCK_INFO_ARRAY *ClockInfoArray, @@ -266,6 +378,7 @@ GfxPowerPlayCopyClockInfo ( ClockInfoArray->ClockInfo[ClkStateIndex].ucEngineClockHigh = (UINT8) (DpmStateArray[Index].Sclk >> 16); ClockInfoArray->ClockInfo[ClkStateIndex].usEngineClockLow = (UINT16) (DpmStateArray[Index].Sclk); ClockInfoArray->ClockInfo[ClkStateIndex].vddcIndex = DpmStateArray[Index].Vid; + ClockInfoArray->ClockInfo[ClkStateIndex].tdpLimit = DpmStateArray[Index].Tdp; ClkStateIndex++; } } @@ -346,7 +459,6 @@ GfxPowerPlayIsFusedStateValid ( * @param[in] Gfx Gfx configuration info * @retval State classification */ - UINT16 GfxPowerPlayGetClassificationFromFuses ( IN UINT8 Index, @@ -416,6 +528,7 @@ GfxPowerPlayBuildTable ( UINT32 NonClockArrayLength; SW_STATE *State; PP_FUSE_ARRAY *PpFuses; + UINT32 Sclk; PpFuses = GnbLocateHeapBuffer (AMD_PP_FUSE_TABLE_HANDLE, GnbLibGetHeader (Gfx)); ASSERT (PpFuses != NULL); @@ -446,10 +559,9 @@ GfxPowerPlayBuildTable ( } for (DpmFuseIndex = 0; DpmFuseIndex < MAX_NUM_OF_FUSED_DPM_STATES; DpmFuseIndex++) { if ((PpFuses->SclkDpmValid[Index] & (1 << DpmFuseIndex)) != 0 ) { - UINT32 Sclk; Sclk = (PpFuses->SclkDpmDid[DpmFuseIndex] != 0) ? GfxFmCalculateClock (PpFuses->SclkDpmDid[DpmFuseIndex], GnbLibGetHeader (Gfx)) : 0; if (Sclk != 0) { - ClkStateIndex = GfxPowerPlayAddDpmState (DpmStateArray, Sclk, PpFuses->SclkDpmVid[DpmFuseIndex]); + ClkStateIndex = GfxPowerPlayAddDpmState (DpmStateArray, Sclk, PpFuses->SclkDpmVid[DpmFuseIndex], PpFuses->SclkDpmTdpLimit[DpmFuseIndex]); GfxPowerPlayAddDpmStateToSwState (State, ClkStateIndex); } } @@ -459,13 +571,15 @@ GfxPowerPlayBuildTable ( // Create Boot State State = GfxPowerPlayCreateSwState (SwStateArray); State->Classification = ATOM_PPLIB_CLASSIFICATION_BOOT; - ClkStateIndex = GfxPowerPlayAddDpmState (DpmStateArray, 200 * 100, 0); + Sclk = 200 * 100; + ClkStateIndex = GfxPowerPlayAddDpmState (DpmStateArray, Sclk, 0, GfxPowerPlayLocateTdp (PpFuses, Sclk, GnbLibGetHeader (Gfx))); GfxPowerPlayAddDpmStateToSwState (State, ClkStateIndex); // Create Thermal State State = GfxPowerPlayCreateSwState (SwStateArray); State->Classification = ATOM_PPLIB_CLASSIFICATION_THERMAL; - ClkStateIndex = GfxPowerPlayAddDpmState (DpmStateArray, 200 * 100, 0); + Sclk = GfxFmCalculateClock (PpFuses->SclkThermDid, GnbLibGetHeader (Gfx)); + ClkStateIndex = GfxPowerPlayAddDpmState (DpmStateArray, Sclk, 0, GfxPowerPlayLocateTdp (PpFuses, Sclk, GnbLibGetHeader (Gfx))); GfxPowerPlayAddDpmStateToSwState (State, ClkStateIndex); //Copy state info to actual PP table @@ -562,11 +676,11 @@ GfxIntegratedDebugDumpPpTable ( IDS_HDT_CONSOLE (GFX_MISC, " SCLK = %d\n", ClockInfoArrayPtr->ClockInfo[Index].usEngineClockLow | (ClockInfoArrayPtr->ClockInfo[Index].ucEngineClockHigh << 16) ); - IDS_HDT_CONSOLE (GFX_MISC, " Cac = %d\n", - ClockInfoArrayPtr->ClockInfo[Index].leakage - ); IDS_HDT_CONSOLE (GFX_MISC, " VID index = %d\n", ClockInfoArrayPtr->ClockInfo[Index].vddcIndex ); + IDS_HDT_CONSOLE (GFX_MISC, " tdpLimit = %d\n", + ClockInfoArrayPtr->ClockInfo[Index].tdpLimit + ); } } diff --git a/src/vendorcode/amd/agesa/f14/Proc/GNB/Modules/GnbGfxInitLibV1/GfxPowerPlayTable.h b/src/vendorcode/amd/agesa/f14/Proc/GNB/Modules/GnbGfxInitLibV1/GfxPowerPlayTable.h index 6fe93d7298..7aea7dc865 100644 --- a/src/vendorcode/amd/agesa/f14/Proc/GNB/Modules/GnbGfxInitLibV1/GfxPowerPlayTable.h +++ b/src/vendorcode/amd/agesa/f14/Proc/GNB/Modules/GnbGfxInitLibV1/GfxPowerPlayTable.h @@ -106,8 +106,7 @@ typedef struct _ATOM_PPLIB_SUMO_CLOCK_INFO { USHORT usEngineClockLow; ///< Sclk [15:0] (Sclk in 10khz) UCHAR ucEngineClockHigh; ///< Sclk [23:16](Sclk in 10khz) UCHAR vddcIndex; ///< 2-bit VDDC index; - UCHAR leakage; ///< Absolute Cac value; - UCHAR rsv; ///< Reserved + USHORT tdpLimit; ///< TDP Limit USHORT rsv1; ///< Reserved ULONG rsv2[2]; ///< Reserved } ATOM_PPLIB_SUMO_CLOCK_INFO; diff --git a/src/vendorcode/amd/agesa/f14/Proc/GNB/Modules/GnbNbInitLibV1/GnbNbInitLibV1.c b/src/vendorcode/amd/agesa/f14/Proc/GNB/Modules/GnbNbInitLibV1/GnbNbInitLibV1.c index 468e57f74c..07b0961914 100644 --- a/src/vendorcode/amd/agesa/f14/Proc/GNB/Modules/GnbNbInitLibV1/GnbNbInitLibV1.c +++ b/src/vendorcode/amd/agesa/f14/Proc/GNB/Modules/GnbNbInitLibV1/GnbNbInitLibV1.c @@ -53,6 +53,7 @@ #include "amdlib.h" #include "Gnb.h" #include GNB_MODULE_DEFINITIONS (GnbCommonLib) +#include "GnbNbInitLibV1.h" #include "GnbRegistersON.h" #include "Filecode.h" #define FILECODE PROC_GNB_MODULES_GNBNBINITLIBV1_GNBNBINITLIBV1_FILECODE diff --git a/src/vendorcode/amd/agesa/f14/Proc/GNB/Modules/GnbPcieAlibV1/PcieAlib.c b/src/vendorcode/amd/agesa/f14/Proc/GNB/Modules/GnbPcieAlibV1/PcieAlib.c index b28e1a9189..a1fd4190ec 100644 --- a/src/vendorcode/amd/agesa/f14/Proc/GNB/Modules/GnbPcieAlibV1/PcieAlib.c +++ b/src/vendorcode/amd/agesa/f14/Proc/GNB/Modules/GnbPcieAlibV1/PcieAlib.c @@ -74,6 +74,8 @@ */ extern UINT8 AlibSsdt[]; +extern AGESA_STATUS PcieFmAlibBuildAcpiTable (VOID *AlibSsdtPtr, AMD_CONFIG_PARAMS *StdHeader); +; /*---------------------------------------------------------------------------------------- * T Y P E D E F S A N D S T R U C T U R E S @@ -88,7 +90,15 @@ extern UINT8 AlibSsdt[]; VOID STATIC -PcieAlibSetPortGenCapabilityCallback ( +PcieAlibSetPortMaxSpeedCallback ( + IN PCIe_ENGINE_CONFIG *Engine, + IN OUT VOID *Buffer, + IN PCIe_PLATFORM_CONFIG *Pcie + ); + +VOID +STATIC +PcieAlibSetPortOverrideSpeedCallback ( IN PCIe_ENGINE_CONFIG *Engine, IN OUT VOID *Buffer, IN PCIe_PLATFORM_CONFIG *Pcie @@ -177,13 +187,14 @@ PcieAlibBuildAcpiTable ( // Copy template to buffer LibAmdMemCopy (AlibSsdtBuffer, &AlibSsdt[0], AlibSsdtlength, StdHeader); // Set PCI MMIO configuration - AmlObjName = '10DA'; +// AmlObjName = '10DA'; + AmlObjName = Int32FromChar ('1', '0', 'D', 'A'); AmlObjPtr = GnbLibFind (AlibSsdtBuffer, AlibSsdtlength, (UINT8*) &AmlObjName, sizeof (AmlObjName)); if (AmlObjPtr != NULL) { - UINT64 MsrRegister; - LibAmdMsrRead (MSR_MMIO_Cfg_Base, &MsrRegister, StdHeader); - if ((MsrRegister & BIT0) != 0 && (MsrRegister & 0xFFFFFFFF00000000) == 0) { - *(UINT32*)((UINT8*)AmlObjPtr + 5) = (UINT32)(MsrRegister & 0xFFFFF00000); + UINT64 MsrReg; + LibAmdMsrRead (MSR_MMIO_Cfg_Base, &MsrReg, StdHeader); + if ((MsrReg & BIT0) != 0 && (MsrReg & 0xFFFFFFFF00000000) == 0) { + *(UINT32*)((UINT8*)AmlObjPtr + 5) = (UINT32)(MsrReg & 0xFFFFF00000); } else { Status = AGESA_ERROR; } @@ -193,7 +204,8 @@ PcieAlibBuildAcpiTable ( // Set voltage configuration PpFuseArray = GnbLocateHeapBuffer (AMD_PP_FUSE_TABLE_HANDLE, StdHeader); if (PpFuseArray != NULL) { - AmlObjName = '30DA'; +// AmlObjName = '30DA'; + AmlObjName = Int32FromChar ('3', '0', 'D', 'A'); AmlObjPtr = GnbLibFind (AlibSsdtBuffer, AlibSsdtlength, (UINT8*) &AmlObjName, sizeof (AmlObjName)); ASSERT (AmlObjPtr != NULL); if (AmlObjPtr != NULL) { @@ -222,7 +234,8 @@ PcieAlibBuildAcpiTable ( BootUpVidIndex = (UINT8) Index; } } - AmlObjName = '40DA'; +// AmlObjName = '40DA'; + AmlObjName = Int32FromChar ('4', '0', 'D', 'A'); AmlObjPtr = GnbLibFind (AlibSsdtBuffer, AlibSsdtlength, (UINT8*) &AmlObjName, sizeof (AmlObjName)); ASSERT (AmlObjPtr != NULL); if (AmlObjPtr != NULL) { @@ -230,7 +243,8 @@ PcieAlibBuildAcpiTable ( } else { Status = AGESA_ERROR; } - AmlObjName = '50DA'; +// AmlObjName = '50DA'; + AmlObjName = Int32FromChar ('5', '0', 'D', 'A'); AmlObjPtr = GnbLibFind (AlibSsdtBuffer, AlibSsdtlength, (UINT8*) &AmlObjName, sizeof (AmlObjName)); ASSERT (AmlObjPtr != NULL); if (AmlObjPtr != NULL) { @@ -240,7 +254,8 @@ PcieAlibBuildAcpiTable ( } // Set PCIe configuration if (PcieLocateConfigurationData (StdHeader, &Pcie) == AGESA_SUCCESS) { - AmlObjName = '20DA'; +// AmlObjName = '20DA'; + AmlObjName = Int32FromChar ('2', '0', 'D', 'A'); AmlObjPtr = GnbLibFind (AlibSsdtBuffer, AlibSsdtlength, (UINT8*) &AmlObjName, sizeof (AmlObjName)); ASSERT (AmlObjPtr != NULL); if (AmlObjPtr != NULL) { @@ -248,20 +263,36 @@ PcieAlibBuildAcpiTable ( } else { Status = AGESA_ERROR; } - AmlObjName = '60DA'; +// AmlObjName = '60DA'; + AmlObjName = Int32FromChar ('6', '0', 'D', 'A'); + AmlObjPtr = GnbLibFind (AlibSsdtBuffer, AlibSsdtlength, (UINT8*) &AmlObjName, sizeof (AmlObjName)); + ASSERT (AmlObjPtr != NULL); + if (AmlObjPtr != NULL) { + PcieConfigRunProcForAllEngines ( + DESCRIPTOR_ALLOCATED | DESCRIPTOR_PCIE_ENGINE, + PcieAlibSetPortMaxSpeedCallback, + (UINT8*)((UINT8*)AmlObjPtr + 7), + Pcie + ); + } else { + Status = AGESA_ERROR; + } +// AmlObjName = '80DA'; + AmlObjName = Int32FromChar ('6', '0', 'D', 'A'); AmlObjPtr = GnbLibFind (AlibSsdtBuffer, AlibSsdtlength, (UINT8*) &AmlObjName, sizeof (AmlObjName)); ASSERT (AmlObjPtr != NULL); if (AmlObjPtr != NULL) { PcieConfigRunProcForAllEngines ( DESCRIPTOR_ALLOCATED | DESCRIPTOR_PCIE_ENGINE, - PcieAlibSetPortGenCapabilityCallback, + PcieAlibSetPortOverrideSpeedCallback, (UINT8*)((UINT8*)AmlObjPtr + 7), Pcie ); } else { Status = AGESA_ERROR; } - AmlObjName = '70DA'; +// AmlObjName = '70DA'; + AmlObjName = Int32FromChar ('6', '0', 'D', 'A'); AmlObjPtr = GnbLibFind (AlibSsdtBuffer, AlibSsdtlength, (UINT8*) &AmlObjName, sizeof (AmlObjName)); ASSERT (AmlObjPtr != NULL); if (AmlObjPtr != NULL) { @@ -278,7 +309,10 @@ PcieAlibBuildAcpiTable ( ASSERT (FALSE); Status = AGESA_ERROR; } - if (Status == AGESA_ERROR) { + if (Status == AGESA_SUCCESS) { + Status = PcieFmAlibBuildAcpiTable (AlibSsdtBuffer, StdHeader); + } + if (Status != AGESA_SUCCESS) { //Shrink table length to size of the header ((ACPI_TABLE_HEADER*) AlibSsdtBuffer)->TableLength = sizeof (ACPI_TABLE_HEADER); } @@ -288,7 +322,7 @@ PcieAlibBuildAcpiTable ( /*----------------------------------------------------------------------------------------*/ /** - * Callback to init max port Gen capability + * Callback to init max port speed capability * * * @@ -301,16 +335,47 @@ PcieAlibBuildAcpiTable ( VOID STATIC -PcieAlibSetPortGenCapabilityCallback ( +PcieAlibSetPortMaxSpeedCallback ( IN PCIe_ENGINE_CONFIG *Engine, IN OUT VOID *Buffer, IN PCIe_PLATFORM_CONFIG *Pcie ) { - UINT8 *PsppMaxPortCapbilityArray; - PsppMaxPortCapbilityArray = (UINT8*) Buffer; + UINT8 *PsppMaxPortSpeedPackage; + PsppMaxPortSpeedPackage = (UINT8*) Buffer; if (Engine->Type.Port.PortData.LinkHotplug != HotplugDisabled || PcieConfigCheckPortStatus (Engine, INIT_STATUS_PCIE_TRAINING_SUCCESS)) { - PsppMaxPortCapbilityArray[(Engine->Type.Port.Address.Address.Device - 2) * 2 + 1] = (UINT8) PcieFmGetLinkSpeedCap (PCIE_PORT_GEN_CAP_MAX, Engine, Pcie) + 1; + PsppMaxPortSpeedPackage[(Engine->Type.Port.Address.Address.Device - 2) * 2 + 1] = (UINT8) PcieFmGetLinkSpeedCap (PCIE_PORT_GEN_CAP_MAX, Engine, Pcie); + } +} + +/*----------------------------------------------------------------------------------------*/ +/** + * Callback to init max port speed capability + * + * + * + * + * @param[in] Engine Pointer to engine config descriptor + * @param[in, out] Buffer Not used + * @param[in] Pcie Pointer to global PCIe configuration + * + */ + +VOID +STATIC +PcieAlibSetPortOverrideSpeedCallback ( + IN PCIe_ENGINE_CONFIG *Engine, + IN OUT VOID *Buffer, + IN PCIe_PLATFORM_CONFIG *Pcie + ) +{ + UINT8 *PsppOverridePortSpeedPackage; + PsppOverridePortSpeedPackage = (UINT8*) Buffer; + if (Engine->Type.Port.PortData.LinkHotplug != HotplugDisabled || PcieConfigCheckPortStatus (Engine, INIT_STATUS_PCIE_TRAINING_SUCCESS)) { + PsppOverridePortSpeedPackage[(Engine->Type.Port.Address.Address.Device - 2) * 2 + 1] = Engine->Type.Port.PortData.MiscControls.LinkSafeMode; + } + if (Engine->Type.Port.PortData.LinkHotplug == HotplugBasic && !PcieConfigCheckPortStatus (Engine, INIT_STATUS_PCIE_TRAINING_SUCCESS)) { + PsppOverridePortSpeedPackage[(Engine->Type.Port.Address.Address.Device - 2) * 2 + 1] = PcieGen1; } } @@ -344,7 +409,8 @@ PcieAlibSetPortInfoCallback ( PortInfoPackage->PortInfo[PortIndex].StartCoreLane = (UINT8) Engine->Type.Port.StartCoreLane; PortInfoPackage->PortInfo[PortIndex].EndCoreLane = (UINT8) Engine->Type.Port.EndCoreLane; PortInfoPackage->PortInfo[PortIndex].PortId = Engine->Type.Port.PortId; - PortInfoPackage->PortInfo[PortIndex].WrapperId = 0x0130 | (PcieEngineGetParentWrapper (Engine)->WrapId); +// PortInfoPackage->PortInfo[PortIndex].WrapperId = 0x0130 | (PcieEngineGetParentWrapper (Engine)->WrapId); + PortInfoPackage->PortInfo[PortIndex].WrapperId = 0x0130u | (PcieEngineGetParentWrapper (Engine)->WrapId); PortInfoPackage->PortInfo[PortIndex].LinkHotplug = Engine->Type.Port.PortData.LinkHotplug; PortInfoPackage->PortInfo[PortIndex].MaxSpeedCap = (UINT8) PcieFmGetLinkSpeedCap (PCIE_PORT_GEN_CAP_MAX, Engine, Pcie); } diff --git a/src/vendorcode/amd/agesa/f14/Proc/GNB/Modules/GnbPcieAlibV1/PcieAlibConfig.esl b/src/vendorcode/amd/agesa/f14/Proc/GNB/Modules/GnbPcieAlibV1/PcieAlibConfig.esl index e595c28036..5150ee1d22 100644 --- a/src/vendorcode/amd/agesa/f14/Proc/GNB/Modules/GnbPcieAlibV1/PcieAlibConfig.esl +++ b/src/vendorcode/amd/agesa/f14/Proc/GNB/Modules/GnbPcieAlibV1/PcieAlibConfig.esl @@ -65,4 +65,39 @@ #define DEF_PSPP_STATE_AC 0 #define DEF_PSPP_STATE_DC 1 +#define DEF_TRAINING_STATE_COMPLETE 0 +#define DEF_TRAINING_STATE_DETECT_PRESENCE 1 +#define DEF_TRAINING_STATE_PRESENCE_DETECTED 2 +#define DEF_TRAINING_GEN2_WORKAROUND 3 +#define DEF_TRAINING_STATE_NOT_PRESENT 4 +#define DEF_TRAINING_DEVICE_PRESENT 5 +#define DEF_TRAINING_STATE_RELEASE_TRAINING 6 +#define DEF_TRAINING_STATE_REQUEST_RESET 7 +#define DEF_TRAINING_STATE_EXIT 8 + +#define DEF_LINK_SPEED_GEN1 1 +#define DEF_LINK_SPEED_GEN2 2 + +#define DEF_HOTPLUG_STATUS_DEVICE_NOT_PRESENT 0 +#define DEF_HOTPLUG_STATUS_DEVICE_PRESENT 1 + +#define DEF_PORT_NOT_ALLOCATED 0 +#define DEF_PORT_ALLOCATED 1 + +#define DEF_PCIE_LANE_POWERON 1 +#define DEF_PCIE_LANE_POWEROFF 0 +#define DEF_PCIE_LANE_POWEROFFUNUSED 2 + +#define DEF_SCARTCH_PSPP_START_OFFSET 0 +#define DEF_SCARTCH_PSPP_POLICY_OFFSET 1 +#define DEF_SCARTCH_PSPP_ACDC_OFFSET 5 +#define DEF_SCARTCH_PSPP_ACDC_OVR_OFFSET 6 +#define DEF_SCARTCH_PSPP_REQ_OFFSET 16 + +#define DEF_LINKWIDTH_ACTIVE 0 +#define DEF_LINKWIDTH_MAX_PHY 1 + +#define TRUE 1 +#define FALSE 0 + #endif diff --git a/src/vendorcode/amd/agesa/f14/Proc/GNB/Modules/GnbPcieAlibV1/PcieAlibCore.esl b/src/vendorcode/amd/agesa/f14/Proc/GNB/Modules/GnbPcieAlibV1/PcieAlibCore.esl index 7b785a80e8..ab67b9e02e 100644 --- a/src/vendorcode/amd/agesa/f14/Proc/GNB/Modules/GnbPcieAlibV1/PcieAlibCore.esl +++ b/src/vendorcode/amd/agesa/f14/Proc/GNB/Modules/GnbPcieAlibV1/PcieAlibCore.esl @@ -78,6 +78,7 @@ Buffer () {0,0,0,0,0,0,0,0,0,0}, //dev6 Buffer () {0,0,0,0,0,0,0,0,0,0}, //dev7 Buffer () {0,0,0,0,0,0,0,0,0,0}, //dev8 + Buffer () {0,0,0,0,0,0,0,0,0,0}, //dev9 } ) @@ -86,6 +87,9 @@ varPortInfo ) + + Name (varStringBuffer, Buffer (256) {}) + /*----------------------------------------------------------------------------------------*/ /** * Master control method @@ -128,20 +132,12 @@ /*----------------------------------------------------------------------------------------*/ /** - * Read PCI config register - * - * Arg0 - Port Index - * - */ - - /*----------------------------------------------------------------------------------------*/ - /** * Read PCI config register through MMIO * * Arg0 - PCI address Bus/device/func * Arg1 - Register offset */ - Method (procPciDwordRead, 2, NotSerialized) { + Method (procPciDwordRead, 2, Serialized) { Add (varPcieBase, ShiftLeft (Arg0, 12), Local0) Add (Arg1, Local0, Local0) OperationRegion(varOperationRegionMmio, SystemMemory, Local0, 0x4) @@ -159,7 +155,7 @@ * Arg1 - Register offset * Arg2 - Value */ - Method (procPciDwordWrite, 3, NotSerialized) { + Method (procPciDwordWrite, 3, Serialized) { Add (varPcieBase, ShiftLeft (Arg0, 12), Local0) Add (Arg1, Local0, Local0) OperationRegion(varOperationRegionMmio, SystemMemory, Local0, 0x4) @@ -178,7 +174,7 @@ * Arg2 - AND mask * Arg3 - OR mask */ - Method (procPciDwordRMW, 4, NotSerialized) { + Method (procPciDwordRMW, 4, Serialized) { Store (procPciDwordRead (Arg0, Arg1), Local0) Or (And (Local0, Arg2), Arg3, Local0) procPciDwordWrite (Arg0, Arg1, Local0) @@ -310,14 +306,15 @@ Store (1, Local0) while (LEqual (Local0, 1)) { Store (And (procPciDwordRead (Arg0, Local1), 0xFF), Local1) - if (LNotEqual (Local1, 0)) { + if (LEqual (Local1, 0)) { + break + } if (LEqual (And (procPciDwordRead (Arg0, Local1), 0xFF), Arg1)) { Store (0, Local0) } else { Increment (Local1) } } - } return (Local1) } @@ -328,7 +325,7 @@ * Arg0 - Aspm * Arg1 - 0: Read, 1: Write */ - Method (procPcieSbAspmControl, 2, NotSerialized) { + Method (procPcieSbAspmControl, 2, Serialized) { // Create an opregion for PM IO Registers OperationRegion (PMIO, SystemIO, 0xCD6, 0x2) Field (PMIO, ByteAcc, NoLock, Preserve) @@ -359,15 +356,5 @@ Or (And (Local0, 0xfffffffc), Arg0, Local0) Store (Local0, ABDA) } - - } - -#ifdef ALIB_DEBUG - Name (ABUF, Buffer (256) {}) - Name (AFUN, 0xff) - Method (ADBG, 0, Serialized) { - ALIB (AFUN, ABUF); } - Alias (procPciDwordRead, AXPR) -#endif diff --git a/src/vendorcode/amd/agesa/f14/Proc/GNB/Modules/GnbPcieAlibV1/PcieAlibHotplug.esl b/src/vendorcode/amd/agesa/f14/Proc/GNB/Modules/GnbPcieAlibV1/PcieAlibHotplug.esl index fead211aed..5fa1a9774e 100644 --- a/src/vendorcode/amd/agesa/f14/Proc/GNB/Modules/GnbPcieAlibV1/PcieAlibHotplug.esl +++ b/src/vendorcode/amd/agesa/f14/Proc/GNB/Modules/GnbPcieAlibV1/PcieAlibHotplug.esl @@ -12,37 +12,45 @@ * */ /* - ***************************************************************************** - * - * Copyright (c) 2011, Advanced Micro Devices, Inc. - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * * Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * * Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * * Neither the name of Advanced Micro Devices, Inc. nor the names of - * its contributors may be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY - * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND - * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - * *************************************************************************** - * - */ +***************************************************************************** +* +* Copyright (c) 2011, Advanced Micro Devices, Inc. +* All rights reserved. +* +* Redistribution and use in source and binary forms, with or without +* modification, are permitted provided that the following conditions are met: +* * Redistributions of source code must retain the above copyright +* notice, this list of conditions and the following disclaimer. +* * Redistributions in binary form must reproduce the above copyright +* notice, this list of conditions and the following disclaimer in the +* documentation and/or other materials provided with the distribution. +* * Neither the name of Advanced Micro Devices, Inc. nor the names of +* its contributors may be used to endorse or promote products derived +* from this software without specific prior written permission. +* +* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND +* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +* DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY +* DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES +* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; +* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND +* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS +* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +* +**************************************************************************** +* +*/ + External(\_SB.ALIC, MethodObj) + + Name (varStartPhyLane, 0) + Name (varEndPhyLane, 0) + Name (varStartCoreLane, 0) + Name (varEndCoreLane, 0) + Name (varWrapperId, 0) + Name (varPortId, 0) /*----------------------------------------------------------------------------------------*/ /** @@ -50,12 +58,12 @@ * * Arg0 - Data Buffer */ - Method (procPcieSetBusWidth, 1, Serialized) { + Method (procPcieSetBusWidth, 1, NotSerialized) { Store (Buffer (256) {}, Local7) CreateWordField (Local7, 0x0, varReturnBufferLength) CreateWordField (Local7, 0x2, varReturnBusWidth) CreateByteField (Arg0, 0x2, varArgBusWidth) - //@todo deternime correct lane bitmap (check for reversal) gate/ungate unused lanes + //deternime correct lane bitmap (check for reversal) gate/ungate unused lanes Store (3, varReturnBufferLength) Store (varArgBusWidth, varReturnBusWidth) return (Local7) @@ -66,202 +74,310 @@ /** * PCIe port hotplug * - * Arg0 - Data Buffer - * Local7 - Return buffer + * Arg0 - Data Buffer + * Retval - Return buffer */ Method (procPciePortHotplug, 1, Serialized) { Store ("PciePortHotplug Enter", Debug) - Store (Buffer (256) {}, Local7) - CreateWordField (Local7, 0x0, varReturnBufferLength) - CreateByteField (Local7, 0x2, varReturnStatus) - CreateByteField (Local7, 0x3, varReturnDeviceStatus) - CreateWordField (Arg0, 0x2, varPortBdf) - CreateByteField (Arg0, 0x4, varHotplugState) - Subtract (ShiftRight (varPortBdf, 3), 2, Local1); - if (LEqual(varHotplugState, 1)) { + Store (DerefOf (Index (Arg0, 4)), varHotplugStateLocal0) + Store (DerefOf (Index (Arg0, 2)), varPortIndexLocal1) + + Subtract (ShiftRight (varPortBdfLocal1, 3), 2, varPortIndexLocal1) + if (LEqual(varHotplugStateLocal0, 1)) { // Enable port - Store (procPciePortEnable (Local1), varHotplugState); + Store (DEF_TRAINING_STATE_RELEASE_TRAINING, Local2) } else { // Disable port - Store (procPciePortDisable (Local1), varHotplugState); + Store (DEF_TRAINING_STATE_NOT_PRESENT, Local2) } + + Store (procPciePortTraining (varPortIndexLocal1, Local2), varHotplugStateLocal0) + + Store (Buffer (10) {}, Local7) + CreateWordField (Local7, 0x0, varReturnBufferLength) + CreateByteField (Local7, 0x2, varReturnStatus) + CreateByteField (Local7, 0x3, varReturnDeviceStatus) Store (0x4, varReturnBufferLength) Store (0x0, varReturnStatus) - Store (varHotplugState, varReturnDeviceStatus) + Store (varHotplugStateLocal0, varReturnDeviceStatus) Store ("PciePortHotplug Exit", Debug) return (Local7) } - + Name (varSpeedRequest, Buffer (10) {0,0,0,0,0,0,0,0,0,0}) + /*----------------------------------------------------------------------------------------*/ /** - * Enable PCIe port - * - * 1) Ungate lanes - * 2) Enable Lanes - * 3) Train port - * 4) Disable unused lanes - * 5) Gate unused lanes + * Train PCIe port + * * * Arg0 - Port Index - * + * Arg1 - Initial state */ - Method (procPciePortEnable, 1, NotSerialized) { - Store ("PciePortEnable Enter", Debug) - Name (varLinkIsLinkReversed, 0) + Method (procPciePortTraining, 2, Serialized) { + Store ("PciePortTraining Enter", Debug) + Store (DEF_HOTPLUG_STATUS_DEVICE_NOT_PRESENT, varResultLocal4) Store (procPcieGetPortInfo (Arg0), Local7) - CreateByteField (Local7, DEF_OFFSET_LINK_HOTPLUG, varHotplugType) - if (LNotEqual (varHotplugType, DEF_BASIC_HOTPLUG)) { + // Check if port supports basic hotplug + Store (DerefOf (Index (Local7, DEF_OFFSET_LINK_HOTPLUG)), varTempLocal1) + if (LNotEqual (varTempLocal1, DEF_BASIC_HOTPLUG)) { Store (" No action.[Hotplug type]", Debug) - Store ("PciePortEnable Exit", Debug) - return (1) + Store ("procPciePortTraining Exit", Debug) + return (varResultLocal4) } - // Poweron phy lanes - CreateByteField (Local7, DEF_OFFSET_START_PHY_LANE, varStartPhyLane) - CreateByteField (Local7, DEF_OFFSET_END_PHY_LANE, varEndPhyLane) - procPcieLanePowerControl (varStartPhyLane, varEndPhyLane, 0) - // Enable lanes - CreateByteField (Local7, DEF_OFFSET_START_CORE_LANE, varStartCoreLane) - CreateByteField (Local7, DEF_OFFSET_END_CORE_LANE, varEndCoreLane) - procPcieLaneEnableControl (Arg0, varStartPhyLane, varEndPhyLane, 0) - //Release training - procPcieTrainingControl (Arg0, 0) - //Train link - Store (procPcieCheckDevicePrecence (Arg0), Local1) - if (LEqual (Local1, 1)) { - Store (" Device detected", Debug) - Store (procPcieIsPortReversed (Arg0), varLinkIsLinkReversed) - Subtract (procPcieGetLinkWidth (Arg0, 1), procPcieGetLinkWidth (Arg0, 0), Local2) - if (LNotEqual (Local2, 0)) { - //There is unused lanes after device plugged - if (LNotEqual(varLinkIsLinkReversed, 0)) { - Add (varStartCoreLane, Local2, Local3) - Store (varEndCoreLane, Local4) - } else { - Subtract (varEndCoreLane, Local2, Local4) - Store (varStartCoreLane, Local3) + Store (Arg1, varStateLocal2) + while (LNotEqual (varStateLocal2, DEF_TRAINING_STATE_EXIT)) { + if (LEqual (varStateLocal2, DEF_TRAINING_STATE_RELEASE_TRAINING)) { + Store (" State: Release training", Debug) + // Remove link speed override + Store (0, Index (varOverrideLinkSpeed, Arg0)) + // Enable link width upconfigure + procPciePortIndirectRegisterRMW (Arg0, 0xA2, Not (0x2000), 0x0000) + // Request Max link speed for hotplug by going to AC state + Store (0, varPsppAcDcOverride) + procApplyPsppState () + // Power on/enable port lanes + procPcieLaneControl (Arg0, DEF_PCIE_LANE_POWERON) + // Release training + procPcieTrainingControl (Arg0, 0) + // Move to next state to check presence detection + Store (DEF_TRAINING_STATE_DETECT_PRESENCE, varStateLocal2) + // Initialize retry count + Store(0, varCountLocal3) + } + if (LEqual (varStateLocal2, DEF_TRAINING_STATE_DETECT_PRESENCE)) { + Store (" State: Detect presence", Debug) + And (procPciePortIndirectRegisterRead (Arg0, 0xa5), 0x3f, varTempLocal1) + if (LGreater (varTempLocal1, 0x4)) { + // device connection detected move to next state + Store (DEF_TRAINING_STATE_PRESENCE_DETECTED, varStateLocal2) + // reset retry counter + Store(0, varCountLocal3) + continue } - procPcieLaneEnableControl (Arg0, Local3, Local4, 1) - if (LGreater (varStartPhyLane, varEndPhyLane)) { - Store (varEndPhyLane, Local3) - Store (varStartPhyLane, Local4) + if (LLess (varCountLocal3, 80)) { + Sleep (1) + Increment (varCountLocal3) } else { - Store (varEndPhyLane, Local4) - Store (varStartPhyLane, Local3) + // detection time expired move to device not present state + Store (DEF_TRAINING_STATE_NOT_PRESENT, varStateLocal2) } - if (LNotEqual(varLinkIsLinkReversed, 0)) { - Add (Local3, Local2, Local3) - } else { - Subtract (Local4, Local2, Local4) + } + if (LEqual (varStateLocal2, DEF_TRAINING_STATE_PRESENCE_DETECTED)) { + Store (" State: Device detected", Debug) + Store (procPciePortIndirectRegisterRead (Arg0, 0xa5), varTempLocal1) + And (varTempLocal1, 0x3f, varTempLocal1) + if (LEqual (varTempLocal1, 0x10)) { + Store (DEF_TRAINING_DEVICE_PRESENT, varStateLocal2) + continue + } + if (LLess (varCountLocal3, 80)) { + Sleep (1) + Increment (varCountLocal3) + continue + } + Store (DEF_TRAINING_STATE_NOT_PRESENT, varStateLocal2) + + if (LEqual (DeRefOf (Index (varOverrideLinkSpeed, Arg0)), DEF_LINK_SPEED_GEN1)) { + // GEN2 workaround already applied but device not trained successfully move device not present state + continue + } + + if (LEqual (procPcieCheckForGen2Workaround (Arg0), TRUE)) { + Store (" Request Gen2 workaround", Debug) + procPciePortIndirectRegisterRMW (Arg0, 0xA2, Not (0x2000), 0x2000) + Store (DEF_LINK_SPEED_GEN1, Index (varOverrideLinkSpeed, Arg0)) + procPcieSetLinkSpeed (Arg0, DEF_LINK_SPEED_GEN1) + Store (DEF_TRAINING_STATE_REQUEST_RESET, varStateLocal2) } - procPcieLanePowerControl (Local3, Local4, 1) } - Store ("PciePortEnable Exit", Debug) - return (1) - } - Store (" Device detection fail", Debug) - procPciePortDisable (Arg0) - Store ("PciePortEnable Exit", Debug) - return (0) + if (LEqual (varStateLocal2, DEF_TRAINING_STATE_NOT_PRESENT)) { + Store (" State: Device not present", Debug) + procPcieTrainingControl (Arg0, 1) + procPcieLaneControl (Arg0, DEF_PCIE_LANE_POWEROFF) + // Exclude device from PSPP managment since it is not present + Store (DEF_LINK_SPEED_GEN1, Index (varOverrideLinkSpeed, Arg0)) + Store (DEF_TRAINING_STATE_COMPLETE, varStateLocal2) + } + if (LEqual (varStateLocal2, DEF_TRAINING_STATE_REQUEST_RESET)) { + Store (" State: Request Reset", Debug) + if (CondRefOf (\_SB.ALIC, Local6)) { + Store (" Call ALIC method", Debug) + //varTempLocal1 contain port BDF + Store(ShiftLeft (Add (Arg0, 2), 3), varTempLocal1) + \_SB.ALIC (varTempLocal1, 0) + Sleep (2) + \_SB.ALIC (varTempLocal1, 1) + Store (0, varCountLocal3) + Store (DEF_TRAINING_STATE_DETECT_PRESENCE, varStateLocal2) + continue + } + Store (DEF_TRAINING_STATE_NOT_PRESENT, varStateLocal2) + } + if (LEqual (varStateLocal2, DEF_TRAINING_DEVICE_PRESENT)) { + Store (" State: Device present", Debug) + Store (DEF_HOTPLUG_STATUS_DEVICE_PRESENT, varResultLocal4) + Store (DEF_TRAINING_STATE_COMPLETE, varStateLocal2) + procPcieLaneControl (Arg0, DEF_PCIE_LANE_POWEROFFUNUSED) + } + if (LEqual (varStateLocal2, DEF_TRAINING_STATE_COMPLETE)) { + + Store (1, varPsppAcDcOverride) + procApplyPsppState () + + Store (DEF_TRAINING_STATE_EXIT, varStateLocal2) + } + } + Store ("PciePortTraining Exit", Debug) + return (varResultLocal4) } - /*----------------------------------------------------------------------------------------*/ + + /*----------------------------------------------------------------------------------------*/ /** - * Disable PCIe port - * - * 1) Hold training - * 2) Disable lanes - * 3) Gate lanes + * Lane control * - * Arg0 - Port Index - * + * Arg0 - Port Index + * Arg1 - 0 - Power off all lanes / 1 - Power on all Lanes / 2 Power off unused lanes */ - Method (procPciePortDisable, 1, NotSerialized) { - Store ("PciePortDisable Enter", Debug) + + Method (procPcieLaneControl, 2, Serialized) { + Store ("PcieLaneControl Enter", Debug) + Store (Concatenate (" Arg0 : ", ToHexString (Arg0), varStringBuffer), Debug) + Store (Concatenate (" Arg1 : ", ToHexString (Arg1), varStringBuffer), Debug) Store (procPcieGetPortInfo (Arg0), Local7) - CreateByteField (Local7, DEF_OFFSET_LINK_HOTPLUG, varHotplugType) - if (LNotEqual (varHotplugType, DEF_BASIC_HOTPLUG)) { - Store (" No action. [Hotplug type]", Debug) - Store ("PciePortDisable Exit", Debug) - return (0) +#ifdef PCIE_PHY_LANE_POWER_GATE_SUPPORT + Store (DerefOf (Index (Local7, DEF_OFFSET_START_PHY_LANE)), varStartPhyLane) + Store (DerefOf (Index (Local7, DEF_OFFSET_END_PHY_LANE)), varEndPhyLane) +#endif + Store (DerefOf (Index (Local7, DEF_OFFSET_START_CORE_LANE)), varStartCoreLane) + Store (DerefOf (Index (Local7, DEF_OFFSET_END_CORE_LANE)), varEndCoreLane) + + if (LEqual (Arg1, DEF_PCIE_LANE_POWEROFF)) { + procPcieLaneEnableControl (Arg0, varStartCoreLane, varEndCoreLane, 1) +#ifdef PCIE_PHY_LANE_POWER_GATE_SUPPORT + procPcieLanePowerControl (varStartPhyLane, varEndPhyLane, 1) +#endif + } + if (LEqual (Arg1, DEF_PCIE_LANE_POWERON)) { +#ifdef PCIE_PHY_LANE_POWER_GATE_SUPPORT + procPcieLanePowerControl (varStartPhyLane, varEndPhyLane, 0) +#endif + procPcieLaneEnableControl (Arg0, varStartCoreLane, varEndCoreLane, 0) + } + if (LNotEqual (Arg1, DEF_PCIE_LANE_POWEROFFUNUSED)) { + return (0) + } + Store (procPcieGetLinkWidth (Arg0, DEF_LINKWIDTH_ACTIVE), varActiveLinkWidthLocal2) + if (LLessEqual (procPcieGetLinkWidth (Arg0, DEF_LINKWIDTH_MAX_PHY), varActiveLinkWidthLocal2)) { + // Active link equal max link width, nothing needs to be done + return (0) + } + Store (procPcieIsPortReversed (Arg0), varIsReversedLocal1) + //There is unused lanes after device plugged + if (LEqual(varIsReversedLocal1, FALSE)) { + Store (" Port Not Reversed", Debug) + // Link not reversed + Add (varStartCoreLane, varActiveLinkWidthLocal2, Local3) + Store (varEndCoreLane, Local4) + } else { + // Link reversed + Store (" Port Reversed", Debug) + Subtract (varEndCoreLane, varActiveLinkWidthLocal2, Local4) + Store (varStartCoreLane, Local3) + } + procPcieLaneEnableControl (Arg0, Local3, Local4, 1) +#ifdef PCIE_PHY_LANE_POWER_GATE_SUPPORT + if (LGreater (varStartPhyLane, varEndPhyLane)) { + Store (varEndPhyLane, Local3) + Store (varStartPhyLane, Local4) + } else { + Store (varEndPhyLane, Local4) + Store (varStartPhyLane, Local3) } - //Hold training - procPcieTrainingControl (Arg0, 1) - CreateByteField (Local7, DEF_OFFSET_START_CORE_LANE, varStartCoreLane) - CreateByteField (Local7, DEF_OFFSET_END_CORE_LANE, varEndCoreLane) - // Disable lane - procPcieLaneEnableControl (Arg0, varStartCoreLane, varEndCoreLane, 1) - CreateByteField (Local7, DEF_OFFSET_START_PHY_LANE, varStartPhyLane) - CreateByteField (Local7, DEF_OFFSET_END_PHY_LANE, varEndPhyLane) - // Poweroff phy lanes - procPcieLanePowerControl (varStartPhyLane, varEndPhyLane, 1) - - Store ("PciePortDisable Exit", Debug) + if (LEqual(varIsReversedLocal1, FALSE)) { + // Not reversed + Add (Local3, varActiveLinkWidthLocal2, Local3) + } else { + // Link reversed + Subtract (Local4, varActiveLinkWidthLocal2, Local4) + } + procPcieLanePowerControl (Local3, Local4, 1) +#endif return (0) } + /*----------------------------------------------------------------------------------------*/ /** + * Check if GEN2 workaround applicable + * + * Arg0 - Port Index + * Retval - TRUE / FALSE + */ + + Method (procPcieCheckForGen2Workaround, 1, NotSerialized) { + Store (Buffer (16) {}, Local1) + Store (0x0, Local0) + while (LLessEqual (Local0, 0x3)) { + Store (procPciePortIndirectRegisterRead (Arg0, Add (Local0, 0xA5)), Local2) + Store (Local2, Index (Local1, Multiply (Local0, 4))) + Store (ShiftRight (Local2, 8), Index (Local1, Add (Multiply (Local0, 4), 1))) + Store (ShiftRight (Local2, 16), Index (Local1, Add (Multiply (Local0, 4), 2))) + Store (ShiftRight (Local2, 24), Index (Local1, Add (Multiply (Local0, 4), 3))) + Increment (Local0) + } + Store (0, Local0) + while (LLess (Local0, 15)) { + if (LAnd (LEqual (DeRefOf (Index (Local1, Local0)), 0x2a), LEqual (DeRefOf (Index (Local1, Add (Local0, 1))), 0x9))) { + return (TRUE) + } + Increment (Local0) + } + return (FALSE) + } + + /*----------------------------------------------------------------------------------------*/ + /** * Is port reversed - * + * * Arg0 - Port Index - * Retval - 0 - Not reversed / 1 - Reversed + * Retval - 0 - Not reversed / !=0 - Reversed */ - Method (procPcieIsPortReversed , 1, NotSerialized) { + Method (procPcieIsPortReversed , 1, Serialized) { Store (procPcieGetPortInfo (Arg0), Local7) - CreateByteField (Local7, DEF_OFFSET_START_PHY_LANE, varStartPhyLane) - CreateByteField (Local7, DEF_OFFSET_END_PHY_LANE, varEndPhyLane) + + Store (DerefOf (Index (Local7, DEF_OFFSET_START_PHY_LANE)), varStartPhyLane) + Store (DerefOf (Index (Local7, DEF_OFFSET_END_PHY_LANE)), varEndPhyLane) Store (0, Local0) if (LGreater (varStartPhyLane, varEndPhyLane)) { Store (1, Local0) } And (procPciePortIndirectRegisterRead (Arg0, 0x50), 0x1, Local1) - return (Xor (Local0, Local1)) + return (And (Xor (Local0, Local1), 0x1)) } /*----------------------------------------------------------------------------------------*/ /** * Training Control - * + * * Arg0 - Port Index - * Arg1 - Hold Training (1) / Release Training (0) + * Arg1 - Hold Training (1) / Release Training (0) */ Method (procPcieTrainingControl , 2, NotSerialized) { Store ("PcieTrainingControl Enter", Debug) Store (procPcieGetPortInfo (Arg0), Local7) - CreateByteField (Local7, DEF_OFFSET_PORT_ID, varPortId) - CreateWordField (Local7, DEF_OFFSET_WRAPPER_ID, varWrapperId) + Store (DerefOf (Index (Local7, DEF_OFFSET_PORT_ID)), varPortId) + Store ( + Or (ShiftLeft (DerefOf (Index (Local7, Add (DEF_OFFSET_WRAPPER_ID, 1))), 8), DerefOf (Index (Local7, DEF_OFFSET_WRAPPER_ID))), + varWrapperId + ) procIndirectRegisterRMW (0x0, 0xE0, Or (ShiftLeft (varWrapperId, 16), Add (0x800, Multiply (0x100, varPortId))), Not (0x1), Arg1); Store ("PcieTrainingControl Exit", Debug) } - /*----------------------------------------------------------------------------------------*/ - /** - * Check device presence - * - * Arg0 - Port Index - * Retval - 1 - Device present, 0 - Device not present - */ - Method (procPcieCheckDevicePrecence, 1, NotSerialized) { - Store ("PcieCheckDevicePrecence Enter", Debug) - Store (0, Local0) - Store (0, Local7) - while (LLess (Local0, 320)) { // @todo for debug only should be 80 - And (procPciePortIndirectRegisterRead (Arg0, 0xa5), 0x3f, Local1) - if (LEqual (Local1, 0x10)) { - Store (1, Local7) - Store (320, Local0) - Break - } - Stall (250) - Increment (Local0) - } - //Store (Concatenate ("Device Presence Status :", ToHexString (Local7)), Debug) - Store ("PcieCheckDevicePrecence Exit", Debug) - return (Local7) - } - - /*----------------------------------------------------------------------------------------*/ +Name (varLinkWidthBuffer, Buffer () {0, 1, 2, 4, 8, 12, 16}) +/*----------------------------------------------------------------------------------------*/ /** * Get actual negotiated/PHY or core link width * @@ -270,23 +386,29 @@ * Retval - Link Width */ Method (procPcieGetLinkWidth, 2, NotSerialized) { - if (LEqual (Arg0, 0)){ - //Get negotiated length + Store ("PcieGetLinkWidth Enter", Debug) + Store (Concatenate (" Arg0 : ", ToHexString (Arg0), varStringBuffer), Debug) + Store (Concatenate (" Arg1 : ", ToHexString (Arg1), varStringBuffer), Debug) + + if (LEqual (Arg1, DEF_LINKWIDTH_ACTIVE)){ + //Get negotiated length And (ShiftRight (procPciePortIndirectRegisterRead (Arg0, 0xA2), 4), 0x7, Local0) - Store (DeRefOf (Index (Buffer (){0, 1, 2, 4, 8, 12, 16}, Local0)), Local1) + Store (DeRefOf (Index (varLinkWidthBuffer, Local0)), Local1) + Store (Concatenate (" Active Link Width :", ToHexString (Local1), varStringBuffer), Debug) } else { //Get phy length Store (procPcieGetPortInfo (Arg0), Local7) - CreateByteField (Local7, DEF_OFFSET_START_PHY_LANE, varStartPhyLane) - CreateByteField (Local7, DEF_OFFSET_END_PHY_LANE, varEndPhyLane) + Store (DerefOf (Index (Local7, DEF_OFFSET_START_PHY_LANE)), varStartPhyLane) + Store (DerefOf (Index (Local7, DEF_OFFSET_END_PHY_LANE)), varEndPhyLane) if (LGreater (varStartPhyLane, varEndPhyLane)) { Subtract (varStartPhyLane, varEndPhyLane, Local1) } else { Subtract (varEndPhyLane, varStartPhyLane, Local1) } - Increment (Local1) + Increment (Local1) + Store (Concatenate (" PHY Link Width :", ToHexString (Local1), varStringBuffer), Debug) } - //Store (Concatenate ("Link Width :", ToHexString (Local7)), Debug) + Store ("PcieGetLinkWidth Exit", Debug) return (Local1) } @@ -297,16 +419,21 @@ * Arg0 - Port Index * Arg1 - Start Lane * Arg2 - End Lane - * Arg3 - Enable(0) / Disable(1) + * Arg3 - Enable(0) / Disable(1) */ - Method (procPcieLaneEnableControl, 4, NotSerialized) { + Method (procPcieLaneEnableControl, 4, Serialized) { Store ("PcieLaneEnableControl Enter", Debug) - Name (varStartCoreLane, 0) - Name (varEndCoreLane, 0) + Store (Concatenate (" Arg0 : ", ToHexString (Arg0), varStringBuffer), Debug) + Store (Concatenate (" Arg1 : ", ToHexString (Arg1), varStringBuffer), Debug) + Store (Concatenate (" Arg2 : ", ToHexString (Arg2), varStringBuffer), Debug) + Store (Concatenate (" Arg3 : ", ToHexString (Arg3), varStringBuffer), Debug) Store (procPcieGetPortInfo (Arg0), Local7) Store (Arg1, varStartCoreLane) Store (Arg2, varEndCoreLane) - CreateWordField (Local7, DEF_OFFSET_WRAPPER_ID, varWrapperId) + Store ( + Or (ShiftLeft (DerefOf (Index (Local7, Add (DEF_OFFSET_WRAPPER_ID, 1))), 8), DerefOf (Index (Local7, DEF_OFFSET_WRAPPER_ID))), + varWrapperId + ) if (LGreater (varStartCoreLane, varEndCoreLane)) { Subtract (varStartCoreLane, varEndCoreLane, Local1) Store (varEndCoreLane, Local2) @@ -314,13 +441,13 @@ Subtract (varEndCoreLane, varStartCoreLane, Local1) Store (varStartCoreLane, Local2) } - ShiftLeft (Subtract (ShiftLeft (1, Add (Local1, 1)), 1), Local2, Local1) - //Store (Concatenate ("Lane Bitmap :", ToHexString (Local1)), Debug) - if (Lequal (Arg3, 0)) { - procIndirectRegisterRMW (0x0, 0xE0, Or (ShiftLeft (varWrapperId, 16), 0x8023), 0xffffffff, Local1); - } else { - procIndirectRegisterRMW (0x0, 0xE0, Or (ShiftLeft (varWrapperId, 16), 0x8023), Not (Local1), 0x0); + ShiftLeft (Subtract (ShiftLeft (1, Add (Local1, 1)), 1), Local2, varLaneBitmapOrMaskLocal3) + Store (Not (varLaneBitmapOrMaskLocal3), varLaneBitmapAndMaskLocal4) + Store (Concatenate ("Lane Bitmap : ", ToHexString (varLaneBitmapOrMaskLocal3), varStringBuffer), Debug) + if (Lequal (Arg3, 1)) { + Store (0, varLaneBitmapOrMaskLocal3) } + procIndirectRegisterRMW (0x0, 0xE0, Or (ShiftLeft (varWrapperId, 16), 0x8023), varLaneBitmapAndMaskLocal4, varLaneBitmapOrMaskLocal3); Stall (10) Store ("PcieLaneEnableControl Exit", Debug) } diff --git a/src/vendorcode/amd/agesa/f14/Proc/GNB/Modules/GnbPcieAlibV1/PcieAlibPspp.esl b/src/vendorcode/amd/agesa/f14/Proc/GNB/Modules/GnbPcieAlibV1/PcieAlibPspp.esl index 70d6a93b84..2bfabc9077 100644 --- a/src/vendorcode/amd/agesa/f14/Proc/GNB/Modules/GnbPcieAlibV1/PcieAlibPspp.esl +++ b/src/vendorcode/amd/agesa/f14/Proc/GNB/Modules/GnbPcieAlibV1/PcieAlibPspp.esl @@ -12,36 +12,36 @@ * */ /* - ***************************************************************************** - * - * Copyright (c) 2011, Advanced Micro Devices, Inc. - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * * Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * * Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * * Neither the name of Advanced Micro Devices, Inc. nor the names of - * its contributors may be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY - * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND - * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - * *************************************************************************** - * - */ +***************************************************************************** +* +* Copyright (c) 2011, Advanced Micro Devices, Inc. +* All rights reserved. +* +* Redistribution and use in source and binary forms, with or without +* modification, are permitted provided that the following conditions are met: +* * Redistributions of source code must retain the above copyright +* notice, this list of conditions and the following disclaimer. +* * Redistributions in binary form must reproduce the above copyright +* notice, this list of conditions and the following disclaimer in the +* documentation and/or other materials provided with the distribution. +* * Neither the name of Advanced Micro Devices, Inc. nor the names of +* its contributors may be used to endorse or promote products derived +* from this software without specific prior written permission. +* +* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND +* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +* DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY +* DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES +* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; +* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND +* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS +* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +* +**************************************************************************** +* +*/ /*----------------------------------------------------------------------------------------*/ /** @@ -112,26 +112,23 @@ /*----------------------------------------------------------------------------------------*/ /** - * Max Port GEN capability + * Max Port link speed * */ - Name ( - AD06, - Package () { - 0x00, - 0x00, - 0x00, - 0x00, - 0x00, - 0x00, - 0x00 - } - ) + Name (AD06, Package () {0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}) + + Alias (AD06, varMaxLinkSpeed) - Alias ( - AD06, - varPsppMaxPortCapabilityArray - ) + + /*----------------------------------------------------------------------------------------*/ + /** + * Max link speed that was changed during runtime (hotplug for instance) + * + */ + + Name (AD08, Package () {0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}) + + Alias (AD08, varOverrideLinkSpeed) /*----------------------------------------------------------------------------------------*/ /** @@ -141,10 +138,7 @@ * 1 (Started) */ - Name ( - varPsppPolicyService, - 0x0 - ) + Name (varPsppPolicyService, 0x0 ) /*----------------------------------------------------------------------------------------*/ /** @@ -154,85 +148,100 @@ * 1 (DC) */ - Name ( - varPsppAcDcState, - 0x0 - ) + Name (varPsppAcDcState, 0x0) + Name (varPsppAcDcOverride, 0x1) + /*----------------------------------------------------------------------------------------*/ + /** + * Client ID array + * + */ - Name ( - varPsppClientIdArray, - Package () { - 0x0000, - 0x0000, - 0x0000, - 0x0000, - 0x0000, - 0x0000, - 0x0000 - } - ) + Name (varPsppClientIdArray, + Package () {0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000} + ) - Name ( - varPsppClientCapabilityArray, - Package () { - 0x00, - 0x00, - 0x00, - 0x00, - 0x00, - 0x00, - 0x00 - } - ) + Name (varDefaultPsppClientIdArray, + Package () {0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000} + ) + /*----------------------------------------------------------------------------------------*/ + /** + * LInk speed requested by device driver + * + */ + Name (varRequestedLinkSpeed, Package () {0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}) + + /*----------------------------------------------------------------------------------------*/ + /** + * Current link speed + * + */ + Name (AD09, Package () {0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 }) + Alias (AD09, varCurrentLinkSpeed) + /*----------------------------------------------------------------------------------------*/ + /** + * Template link speed + * + */ Name ( - varPsppCurrentCapabilityArray, - Package () { - 0x00, - 0x00, - 0x00, - 0x00, - 0x00, - 0x00, - 0x00 - } - ) - Name ( - varDefaultGen1CapabilityArray, + varGen1LinkSpeedTemplate, Package () { - 0x2, - 0x2, - 0x2, - 0x2, - 0x2, - 0x2, - 0x2 - } - ) + DEF_LINK_SPEED_GEN1, + DEF_LINK_SPEED_GEN1, + DEF_LINK_SPEED_GEN1, + DEF_LINK_SPEED_GEN1, + DEF_LINK_SPEED_GEN1, + DEF_LINK_SPEED_GEN1, + DEF_LINK_SPEED_GEN1, + DEF_LINK_SPEED_GEN1 + }) + /*----------------------------------------------------------------------------------------*/ + /** + * Template link speed + * + */ + Name (varLowVoltageRequest, Package () {0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0 }) /*----------------------------------------------------------------------------------------*/ /** + * Global varuable + * + */ + Name (varPortIndex, 0) + /*----------------------------------------------------------------------------------------*/ + /** * Report AC/DC state * * Arg0 - Data Buffer */ Method (procPsppReportAcDsState, 1, Serialized) { Store ("PsppReportAcDsState Enter", Debug) - CreateByteField (Arg0, 0x2, varArgAcDcState) - Store ("AC/DC state = ", Debug) - Store (varArgAcDcState, Debug) - if (LEqual (varArgAcDcState, varPsppAcDcState)) { + Store (DeRefOf (Index (Arg0, 0x2)), varArgAcDcStateLocal1) + Store (Concatenate (" AC/DC state: ", ToHexString (varArgAcDcStateLocal1), varStringBuffer), Debug) + + Store (procPsppGetAcDcState(), varCurrentAcDcStateLocal0) + Store (varArgAcDcStateLocal1, varPsppAcDcState) + + Or (ShiftLeft (1, DEF_SCARTCH_PSPP_ACDC_OFFSET), ShiftLeft (1, DEF_SCARTCH_PSPP_ACDC_OVR_OFFSET), Local2) + Or (ShiftLeft (varPsppAcDcState, DEF_SCARTCH_PSPP_ACDC_OFFSET), ShiftLeft (varPsppAcDcOverride, DEF_SCARTCH_PSPP_ACDC_OVR_OFFSET), Local3) + procIndirectRegisterRMW (0x0, 0x60, 0xF4, Not (Local2), And (Local2, Local3)) + + + if (LEqual (varArgAcDcStateLocal1, varCurrentAcDcStateLocal0)) { Store (" No action. [AC/DC state not changed]", Debug) Store ("PsppReportAcDsState Exit", Debug) return (0) } - Store (varArgAcDcState, varPsppAcDcState) + + // Disable both APM (boost) and PDM flow on DC event enable it on AC. + procApmPdmActivate(varPsppAcDcState) + // Set DPM state for Power Saving, due to this policy will not attend ApplyPsppState service. if (LEqual (varPsppPolicy, DEF_PSPP_POLICY_POWERSAVING)) { - procNbLclkDpmActivate(1, varPsppAcDcState) + procNbLclkDpmActivate(1, procPsppGetAcDcState()) } if (LOr (LLessEqual (varPsppPolicy, DEF_PSPP_POLICY_PERFORMANCE), LGreaterEqual (varPsppPolicy, DEF_PSPP_POLICY_POWERSAVING))) { Store (" No action. [Policy type]", Debug) @@ -255,15 +264,31 @@ * * Arg0 - Data Buffer */ - Method (procPsppPerformanceRequest, 1) { - Store ("PsppPerformanceRequest Enter", Debug) + Method (procPsppPerformanceRequest, 1, NotSerialized) { + Store (procPsppProcessPerformanceRequest (Arg0), Local7) + Store (DeRefOf (Index (Local7, 2)), varReturnStatusLocal0) + if (LNotEqual (varReturnStatusLocal0, 2)) { + return (Local7) + } + procApplyPsppState () + return (Local7) + } + /*----------------------------------------------------------------------------------------*/ + /** + * PCIe Performance Request + * + * Arg0 - Data Buffer + */ + Method (procPsppProcessPerformanceRequest, 1, NotSerialized) { + Store ("PsppProcessPerformanceRequest Enter", Debug) Name (varClientBus, 0) - Name (varPortIndex, 0) - Store (Buffer (256) {}, Local7) + Store (0, varPortIndex) + Store (Buffer (10) {}, Local7) CreateWordField (Local7, 0x0, varReturnBufferLength) Store (3, varReturnBufferLength) CreateByteField (Local7, 0x2, varReturnStatus) Store (1, varReturnStatus) + if (LOr (LLessEqual (varPsppPolicy, DEF_PSPP_POLICY_PERFORMANCE), LGreaterEqual (varPsppPolicy, DEF_PSPP_POLICY_POWERSAVING))) { Store (" No action. [Policy type]", Debug) Store ("PsppPerformanceRequest Exit", Debug) @@ -280,56 +305,58 @@ CreateByteField (Arg0, 0x8, varRequestType) CreateByteField (Arg0, 0x9, varRequestData) - Store (" Client ID:", Debug) - Store (varClientId, Debug) - Store (" Valid Flags:", Debug) - Store (varValidFlag, Debug) - Store (" Flags:", Debug) - Store (varFlag, Debug) - Store (" Request Type:", Debug) - Store (varRequestType, Debug) - Store (" Request Data:", Debug) - Store (varRequestData, Debug) + Store (Concatenate (" Client ID : ", ToHexString (varClientId), varStringBuffer), Debug) + Store (Concatenate (" Valid Flags : ", ToHexString (varValidFlag), varStringBuffer), Debug) + Store (Concatenate (" Flags : ", ToHexString (varFlag), varStringBuffer), Debug) + Store (Concatenate (" Request Type: ", ToHexString (varRequestType), varStringBuffer), Debug) + Store (Concatenate (" Request Data: ", ToHexString (varRequestData), varStringBuffer), Debug) + And (ShiftRight (varClientId, 8), 0xff, varClientBus) - While (LLessEqual (varPortIndex, varMaxPortIndexNumber)) { - if (LEqual (DeRefOf (Index (varPsppMaxPortCapabilityArray, varPortIndex)), 0)) { - Increment (varPortIndex) - Continue - } - Store (procPciDwordRead (ShiftLeft (Add( varPortIndex, 2), 3), 0x18), Local1) - And (ShiftRight (Local1, 16), 0xff, Local2) //Local2 Port Subordinate Bus number - And (ShiftRight (Local1, 8), 0xff, Local1) //Local1 Port Secondary Bus number - if (LAnd (LLess (varClientBus, Local1), LGreater (varClientBus, Local2))) { - Increment (varPortIndex) - Continue - } - Store ("Performance request for port index", Debug) - Store (varPortIndex, Debug) - - if (LEqual (DeRefOf (Index (varPsppClientIdArray, varPortIndex)), 0x0000)) { - Store (varClientId, Index (varPsppClientIdArray, varPortIndex)) - } ElseIf (LNotEqual (DeRefOf (Index (varPsppClientIdArray, varPortIndex)), varClientId)) { - // We already have registered client - Store (" No action. [Unsupported request]", Debug) - Store ("PsppPerformanceRequest Exit", Debug) - return (Local7) - } - if (LEqual (varRequestData, 0)) { - Store (0x0000, Index (varPsppClientIdArray, varPortIndex)) - } else { - if (LEqual (And (varValidFlag, varFlag), 0x1)) { - Store (DerefOf (Index (varPsppMaxPortCapabilityArray, varPortIndex)), Index (varPsppClientCapabilityArray, varPortIndex)) - } else { - Store (varRequestData, Index (varPsppClientCapabilityArray, varPortIndex)) + while (LLessEqual (varPortIndex, varMaxPortIndexNumber)) { + if (LEqual (procChecPortAllocated (varPortIndex), DEF_PORT_ALLOCATED)) { + Store (procPciDwordRead (ShiftLeft (Add( varPortIndex, 2), 3), 0x18), Local1) + And (ShiftRight (Local1, 16), 0xff, varSubordinateBusLocal2) //Local2 Port Subordinate Bus number + And (ShiftRight (Local1, 8), 0xff, varSecondaryBusLocal1) //Local1 Port Secondary Bus number + if (LAnd (LGreaterEqual (varClientBus, Local1), LLessEqual(varClientBus, Local2))) { + break } } - procApplyPsppState () - Store (2, varReturnStatus) + Increment (varPortIndex) + } + if (LGreater (varPortIndex, varMaxPortIndexNumber)) { + Store ("PsppPerformanceRequest Exit", Debug) + return (Local7) + } + + Store (Concatenate (" Performance request for port index : ", ToHexString (varPortIndex), Local6), Debug) + + if (LEqual (DeRefOf (Index (varPsppClientIdArray, varPortIndex)), 0x0000)) { + Store (varClientId, Index (varPsppClientIdArray, varPortIndex)) + } ElseIf (LNotEqual (DeRefOf (Index (varPsppClientIdArray, varPortIndex)), varClientId)) { + // We already have registered client + Store (" No action. [Unsupported request]", Debug) Store ("PsppPerformanceRequest Exit", Debug) return (Local7) } - Store ("PsppPerformanceRequest Exit", Debug) + Store (0, Index (varLowVoltageRequest, varPortIndex)) + if (LEqual (varRequestData, 0)) { + Store (0x0000, Index (varPsppClientIdArray, varPortIndex)) + } + if (LEqual (varRequestData, 1)) { + Store (1, Index (varLowVoltageRequest, varPortIndex)) + } + if (LEqual (varRequestData, 2)) { + Store (DEF_LINK_SPEED_GEN1, Index (varRequestedLinkSpeed, varPortIndex)) + } + if (LEqual (varRequestData, 3)) { + Store (DEF_LINK_SPEED_GEN2, Index (varRequestedLinkSpeed, varPortIndex)) + } + if (LEqual (And (varValidFlag, varFlag), 0x1)) { + Store (DerefOf (Index (varMaxLinkSpeed, varPortIndex)), Index (varRequestedLinkSpeed, varPortIndex)) + } + Store (2, varReturnStatus) + Store ("PsppProcessPerformanceRequest Exit", Debug) return (Local7) } @@ -339,39 +366,84 @@ * * Arg0 - Data Buffer */ + + Method (procChecPortAllocated, 1, Serialized) { + if (LEqual (DeRefOf (Index (varMaxLinkSpeed, Arg0)), 0)) { + return (DEF_PORT_NOT_ALLOCATED) + } + return (DEF_PORT_ALLOCATED) + } + + /*----------------------------------------------------------------------------------------*/ + /** + * PSPP Start/Stop Management Request + * + * Arg0 - Data Buffer + */ Method (procPsppControl, 1, Serialized) { Store ("PsppControl Enter", Debug) Store (Buffer (256) {}, Local7) - CreateWordField (Local7, 0x0, varReturnBufferLength) - Store (3, varReturnBufferLength) - CreateByteField (Local7, 0x2, varReturnStatus) - CreateByteField (Arg0, 0x2, varArgPsppRequest) - Store (varArgPsppRequest, varPsppPolicyService) + Store (3, Index (Local7, 0x0)) // Return Buffer Length + Store (0, Index (Local7, 0x1)) // Return Buffer Length + Store (0, Index (Local7, 0x2)) // Return Status + + Store (DerefOf (Index (Arg0, 0x2)), varPsppPolicyService) + + Store (procIndirectRegisterRead (0x0, 0x60, 0xF4), varPsppScratchLocal0) + + if (LEqual (varPsppPolicyService, DEF_PSPP_POLICY_START)) { + if (LEqual (And (varPsppScratchLocal0, 1), DEF_PSPP_POLICY_START)) { + // Policy already started + Store (" No action. [Policy already started]", Debug) + Store ("PsppControl Exit", Debug) + return (Local7) + } + Or (varPsppScratchLocal0, DEF_PSPP_POLICY_START, varPsppScratchLocal0) + } + if (LEqual (varPsppPolicyService, DEF_PSPP_POLICY_STOP)) { + if (LEqual (And (varPsppScratchLocal0, 1), DEF_PSPP_POLICY_STOP)) { + // Policy already stopped + Store (" No action. [Policy already stopped]", Debug) + Store ("PsppControl Exit", Debug) + return (Local7) + } + And (varPsppScratchLocal0, Not (DEF_PSPP_POLICY_START), varPsppScratchLocal0) + } + Or (varPsppScratchLocal0, Shiftleft (varPsppPolicy, DEF_SCARTCH_PSPP_POLICY_OFFSET), varPsppScratchLocal0) + procIndirectRegisterWrite (0x0, 0x60, 0xF4, varPsppScratchLocal0) + + procCopyPackage (RefOf (varDefaultPsppClientIdArray), RefOf (varPsppClientIdArray)) + + // Reevaluate APM/PDM state here on S3 resume while staying on DC. + procApmPdmActivate(varPsppAcDcState) + // Set DPM state for PSPP Power Saving, due to this policy will not attend ApplyPsppState service. if (LEqual (varPsppPolicy, DEF_PSPP_POLICY_POWERSAVING)) { - procNbLclkDpmActivate(1, varPsppAcDcState) + procNbLclkDpmActivate(DEF_LINK_SPEED_GEN1, procPsppGetAcDcState()) } //Reevaluate PCIe speed for all devices base on PSPP state switch to boot up voltage if (LAnd (LGreater (varPsppPolicy, DEF_PSPP_POLICY_PERFORMANCE), LLess (varPsppPolicy, DEF_PSPP_POLICY_POWERSAVING))) { // Load default speed capability state if (LEqual (varPsppPolicy, DEF_PSPP_POLICY_BALANCEHIGH)) { - procCopyPackage (RefOf (varPsppMaxPortCapabilityArray), RefOf (varPsppCurrentCapabilityArray)) + procCopyPackage (RefOf (varMaxLinkSpeed), RefOf (varCurrentLinkSpeed)) + Store (0, varPortIndex) + while (LLessEqual (varPortIndex, varMaxPortIndexNumber)) { + if (LNotEqual (DeRefOf (Index (varOverrideLinkSpeed, varPortIndex)), 0)) { + Store (DeRefOf (Index (varOverrideLinkSpeed, varPortIndex)), Index (varCurrentLinkSpeed, varPortIndex)) + } + Increment (varPortIndex) + } } else { - procCopyPackage (RefOf (varDefaultGen1CapabilityArray), RefOf (varPsppCurrentCapabilityArray)) - } - // Unregister all clients - if (LEqual (varPsppPolicyService, DEF_PSPP_POLICY_STOP)) { - Name (varDefaultPsppClientIdArray, Package () {0x0, 0x0, 0x0, 0x0, 0x0, 0x0}) - procCopyPackage (RefOf (varDefaultPsppClientIdArray), RefOf (varPsppClientIdArray)) + procCopyPackage (RefOf (varGen1LinkSpeedTemplate), RefOf (varCurrentLinkSpeed)) } procApplyPsppState () } - Store (3, varReturnBufferLength) - Store (0, varReturnStatus) Store ("PsppControl Exit", Debug) return (Local7) } + Name (varNewLinkSpeed, Package () {0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}) + /*----------------------------------------------------------------------------------------*/ /** * Evaluate PCIe speed on all links according to PSPP state and client requests @@ -381,47 +453,46 @@ */ Method (procApplyPsppState, 0, Serialized) { Store ("ApplyPsppState Enter", Debug) - Name (varPortIndex, 0) - Name (varLowPowerMode, 0) - Name (varPcieCapabilityArray, Package () {0x02, 0x02, 0x02, 0x02, 0x02, 0x02, 0x02}) - Store (0, varPortIndex) - While (LLessEqual (varPortIndex, varMaxPortIndexNumber)) { - if (LNotEqual (DeRefOf (Index (varPsppMaxPortCapabilityArray, varPortIndex)), 0)) { - Store (procGetPortRequestedCapability (varPortIndex), Index (varPcieCapabilityArray, varPortIndex)) + + procCopyPackage (RefOf (varGen1LinkSpeedTemplate), RefOf (varNewLinkSpeed)) + while (LLessEqual (varPortIndex, varMaxPortIndexNumber)) { + if (LEqual (procChecPortAllocated(varPortIndex), DEF_PORT_ALLOCATED)) { + Store (procGetPortRequestedCapability (varPortIndex), Index (varNewLinkSpeed, varPortIndex)) } Increment (varPortIndex) } - if (LNotEqual(Match (varPcieCapabilityArray, MEQ, 0x01, MTR, 0, 0), ONES)) { - procCopyPackage (RefOf (varDefaultGen1CapabilityArray), RefOf (varPcieCapabilityArray)) + if (LNotEqual(Match (varLowVoltageRequest, MEQ, 0x01, MTR, 0, 0), ONES)) { + procCopyPackage (RefOf (varGen1LinkSpeedTemplate), RefOf (varNewLinkSpeed)) } - if (LNotEqual(Match (varPcieCapabilityArray, MEQ, 0x03, MTR, 0, 0), ONES)) { + if (LNotEqual(Match (varNewLinkSpeed, MEQ, DEF_LINK_SPEED_GEN2, MTR, 0, 0), ONES)) { // Set GEN2 voltage Store ("Set GEN2 VID", Debug) procPcieSetVoltage (varGen2Vid, 1) - procPcieAdjustPll (2) - procNbLclkDpmActivate(2, varPsppAcDcState) + procPcieAdjustPll (DEF_LINK_SPEED_GEN2) + procNbLclkDpmActivate(DEF_LINK_SPEED_GEN2, procPsppGetAcDcState()) } Store (0, varPortIndex) - While (LLessEqual (varPortIndex, varMaxPortIndexNumber)) { - if (LEqual (DeRefOf (Index (varPsppMaxPortCapabilityArray, varPortIndex)), 0)) { + while (LLessEqual (varPortIndex, varMaxPortIndexNumber)) { + if (LEqual (procChecPortAllocated(varPortIndex), DEF_PORT_NOT_ALLOCATED)) { Increment (varPortIndex) - Continue + continue } - Store (procGetPortCurrentCapability (varPortIndex), Local0) - Store (DerefOf (Index (varPcieCapabilityArray, varPortIndex)), Local2) - if (LEqual (Local0, Local2)) { + Store (DerefOf (Index (varCurrentLinkSpeed, varPortIndex)), varCurrentLinkSpeedLocal0) + Store (DerefOf (Index (varNewLinkSpeed, varPortIndex)), varNewLinkSpeedLocal2) + if (LEqual (varCurrentLinkSpeedLocal0, varNewLinkSpeedLocal2)) { Increment (varPortIndex) - Continue + continue } - procSetPortCapabilityAndSpeed (varPortIndex, Local2, 0) + Store (varNewLinkSpeedLocal2, Index (varCurrentLinkSpeed, varPortIndex)) + procSetPortCapabilityAndSpeed (varPortIndex, varNewLinkSpeedLocal2) Increment (varPortIndex) } - if (LEqual(Match (varPcieCapabilityArray, MEQ, 0x03, MTR, 0, 0), ONES)) { + if (LEqual(Match (varNewLinkSpeed, MEQ, DEF_LINK_SPEED_GEN2, MTR, 0, 0), ONES)) { // Set GEN1 voltage Store ("Set GEN1 VID", Debug) - procNbLclkDpmActivate(1, varPsppAcDcState) - procPcieAdjustPll (1) + procNbLclkDpmActivate(DEF_LINK_SPEED_GEN1, procPsppGetAcDcState()) + procPcieAdjustPll (DEF_LINK_SPEED_GEN1) procPcieSetVoltage (varGen1Vid, 0) } Store ("ApplyPsppState Exit", Debug) @@ -434,200 +505,218 @@ * */ Method (procGetPortRequestedCapability, 1) { - Store (0x3, Local0) + Store (DEF_LINK_SPEED_GEN2, Local0) if (LEqual (DerefOf (Index (varPsppClientIdArray, Arg0)), 0x0000)) { - if (LOr (LEqual (varPsppAcDcState, DEF_PSPP_STATE_DC), LEqual (varPsppPolicy, DEF_PSPP_POLICY_BALANCELOW))) { + if (LOr (LEqual (procPsppGetAcDcState(), DEF_PSPP_STATE_DC), LEqual (varPsppPolicy, DEF_PSPP_POLICY_BALANCELOW))) { // Default policy cap to GEN1 - Store (0x2, Local0) + Store (DEF_LINK_SPEED_GEN1, Local0) + } + if (LNotEqual (DerefOf (Index (varOverrideLinkSpeed, Arg0)), 0)) { + Store (DerefOf (Index (varOverrideLinkSpeed, Arg0)), Local0) } } else { - Store (DerefOf (Index (varPsppClientCapabilityArray, Arg0)), Local0) + Store (DerefOf (Index (varRequestedLinkSpeed, Arg0)), Local0) } return (Local0) } /*----------------------------------------------------------------------------------------*/ /** - * Read PCI config register + * Set capability and speed * * Arg0 - Port Index - * + * Arg1 - Link speed */ - Method (procGetPortCurrentCapability, 1) { - return (DerefOf (Index (varPsppCurrentCapabilityArray, Arg0))) + Method (procSetPortCapabilityAndSpeed, 2, NotSerialized) { + Store ("SetPortCapabilityAndSpeed Enter", Debug) + Store (Concatenate (" Port Index : ", ToHexString (Arg0), varStringBuffer), Debug) + Store (Concatenate (" Speed : ", ToHexString (Arg1), varStringBuffer), Debug) + + //UnHide UMI port + if (LEqual (Arg0, 6)) { + procIndirectRegisterRMW (0x0, 0x60, 0x80, Not (0x40), 0x40); + } + + procPcieSetLinkSpeed (Arg0, Arg1) + + // Programming for LcInitSpdChgWithCsrEn + if (LNotEqual (DeRefOf (Index (varPsppClientIdArray, Arg0)), 0x0000)) { + // Registered port, LcInitSpdChgWithCsrEn = 0. + procPciePortIndirectRegisterRMW (Arg0, 0xA1, Not (0x00001000), 0x0) + } else { + procPciePortIndirectRegisterRMW (Arg0, 0xA1, Not (0x00001000), 0x00001000) + } + + // Determine port PCI address and check port present + Store (ShiftLeft (Add( Arg0, 2), 3), varPortBdfLocal1) + And (procPciDwordRead (varPortBdfLocal1, 0x70), 0x400000, varPortPresentLocal3) + if (LNotEqual (varPortPresentLocal3, 0)) { + procDisableAndSaveAspm (Arg0) + Store (1, Local2) + while (Local2) { + //retrain port + procPciDwordRMW (varPortBdfLocal1, 0x68, Not (0x00000000), 0x20) + Sleep (30) + while (And (procPciDwordRead (varPortBdfLocal1, 0x68), 0x08000000)) { + Sleep (10) + } + Store (0, Local2) + if (LEqual (Arg1, DEF_LINK_SPEED_GEN1)) { + Store (procPciePortIndirectRegisterRead (Arg0, 0xA4), varLcCurrentDataRateLocal4) + if (LNotEqual (And (varLcCurrentDataRateLocal4, 0x800), 0)) { + Store (1, Local2) + } + } + } + procRestoreAspm (Arg0) + } else { + Store (" Device not present. Set capability and speed only", Debug) + } + //Hide UMI port + if (LEqual (Arg0, 6)) { + procIndirectRegisterRMW (0x0, 0x60, 0x80, Not (0x40), 0x00); + } + Store ("SetPortCapabilityAndSpeed Exit", Debug) } + Name (varPcieLinkControlArray, Package () {0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0}) + Name (varPcieLinkControlOffset, 0) + Name (varPcieLinkControlData, 0) + /*----------------------------------------------------------------------------------------*/ /** - * Set capability and speed + * Disable and save ASPM state * * Arg0 - Port Index - * Arg1 - Capability - * Arg2 - Speed */ - Method (procSetPortCapabilityAndSpeed, 3) { - Store ("SetPortCapabilityAndSpeed Enter", Debug) - if (LOr (LEqual (Arg1, 0x2), LEqual (Arg1, 0x3))) { - Store ("Port Index = ", Debug) - Store (Arg0, Debug) - Store ("Cap = ", Debug) - Store (Arg1, Debug) - Store ("Speed = ", Debug) - Store (Arg2, Debug) - - Name (varDxF0xE4_xA4, 0x20000001) - Name (varPortPresent, 0x00000000) - Name (varDxF0x88, 0x00000002) - Name (varAXCFGx68_PmCtrl, 0x00000000) - Name (varLcCurrentDataRate,0x00000000) - Name (varSecondaryBus, 0x00000000) - Name (varHeaderType, 0x00000000) - Name (varMultiFunction, 0x00000000) - Name (varPcieLinkControlOffset, 0x00000000) - Name (varPcieLinkControlData, 0x00000000) - Name (varPcieLinkControlArray, Package () {0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0}) - - - //If request for UMI unhihe port congig space - if (LEqual (Arg0, 6)) { - procIndirectRegisterRMW (0x0, 0x60, 0x80, Not (0x40), 0x40); + Method (procDisableAndSaveAspm, 1, Serialized) { + Store (0, varPcieLinkControlOffset) + Store (0, varPcieLinkControlData) + + Store (ShiftLeft (Add( Arg0, 2), 3), varPortBdfLocal1) + if (LEqual (Arg0, 6)) { + Store (" Disable SB ASPM", Debug) + Store (procPcieSbAspmControl (0, 0), Index (varPcieLinkControlArray, 0)) + Store (Concatenate (" PcieLinkControl Data : ", ToHexString (DerefOf(Index (varPcieLinkControlArray, 0))), varStringBuffer), Debug) + procPcieSbAspmControl (0, 1) + return (0) + } - } - Store (Arg1, Index (varPsppCurrentCapabilityArray, Arg0)) - if (LEqual (Arg1, 0x2)) { - //Gen1 - Store (0x00000000, varDxF0xE4_xA4) - Store (0x21, varDxF0x88) - } + Store (procPciDwordRead (varPortBdfLocal1, 0x18), varTempLocal3) + Store (And (ShiftRight (varTempLocal3, 8), 0xFF), varTempLocal3) - // Programming for LcInitSpdChgWithCsrEn - if (LNotEqual (DeRefOf (Index (varPsppClientIdArray, Arg0)), 0x0000)) { - // Registered port, LcInitSpdChgWithCsrEn = 0. - procPciePortIndirectRegisterRMW (Arg0, 0xA1, Not (0x00001000), 0x0) - } else { - procPciePortIndirectRegisterRMW (Arg0, 0xA1, Not (0x00001000), 0x00001000) + Store (Concatenate (" Disable EP ASPM on Secondary Bus : ", ToHexString (varTempLocal3), varStringBuffer), Debug) + + Store (ShiftLeft (varTempLocal3, 8), varEndpointBdfLocal2) + Store (procPciDwordRead (varEndpointBdfLocal2, 0xC), varTempLocal3) + Store (And (ShiftRight (varTempLocal3, 16), 0xFF), varTempLocal3) + + Store (Concatenate (" EP Header type : ", ToHexString (varTempLocal3), varStringBuffer), Debug) + + if (LNotEqual (And (varTempLocal3, 0x80), 0)) { + Store (0x7, varMaxFunctionLocal0) + } else { + Store (0x0, varMaxFunctionLocal0) + } + Store (0, varFunctionLocal4) + while (LLessEqual (varFunctionLocal4, varMaxFunctionLocal0)) { + //Find PcieLinkControl register offset = PcieCapPtr + 0x10 + Store (procFindPciCapability (Add (varEndpointBdfLocal2, varFunctionLocal4), 0x10), varPcieLinkControlOffset) + if (LEqual (varPcieLinkControlOffset, 0)) { + Increment (varFunctionLocal4) + continue } + Add (varPcieLinkControlOffset, 0x10, varPcieLinkControlOffset) - // Initialize port - procPciePortIndirectRegisterRMW (Arg0, 0xA4, Not (0x20000001), varDxF0xE4_xA4) - //set target link speed - Store (ShiftLeft (Add( Arg0, 2), 3), Local0) - procPciDwordRMW (Local0, 0x88, Not (0x0000002f), varDxF0x88) - - // Determine port PCI address and check port present - Store (ShiftLeft (Add( Arg0, 2), 3), Local0) - And (procPciDwordRead (Local0, 0x70), 0x400000, varPortPresent) - if (LNotEqual (varPortPresent, 0)) { - //Disable ASPM on EP - if (LNotEqual (Arg0, 6)) { - Store (procPciDwordRead (Local0, 0x18), Local3) - Store (And (ShiftRight (Local3, 8), 0xFF), varSecondaryBus) - Store ("Disable EP ASPM on SecondaryBus = ", Debug) - Store (varSecondaryBus, Debug) - Store (ShiftLeft (varSecondaryBus, 8), Local3) - Store (procPciDwordRead (Local3, 0xC), Local3) - Store (And (ShiftRight (Local3, 16), 0xFF), varHeaderType) - Store ("Header Type = ", Debug) - Store (varHeaderType, Debug) - - if (LNotEqual (And (varHeaderType, 0x80), 0)) { - Store (0x7, varMultiFunction) - } - - Store (ShiftLeft (varSecondaryBus, 8), Local3) - Store (0, Local2) - while (LLessEqual (Local2, varMultiFunction)) { - - //Find PcieLinkControl register offset = PcieCapPtr + 0x10 - Store (procFindPciCapability (Local3, 0x10), varPcieLinkControlOffset) - if (LNotEqual (varPcieLinkControlOffset, 0)) { - Add (varPcieLinkControlOffset, 0x10, varPcieLinkControlOffset) - - Store ("Function number of SecondaryBus = ", Debug) - Store (Local2, Debug) - Store ("Find PcieLinkControl register offset = ", Debug) - Store (varPcieLinkControlOffset, Debug) - // Save ASPM on EP - Store (procPciDwordRead (Local3, varPcieLinkControlOffset), varPcieLinkControlData) - Store (And (varPcieLinkControlData, 0x3), Index (varPcieLinkControlArray, Local2)) - Store ("PcieLinkControlData = ", Debug) - Store (varPcieLinkControlData, Debug) - Store ("Save ASPM = ", Debug) - Store (DerefOf (Index (varPcieLinkControlArray, Local2)), Debug) - // Disable ASPM - if (LNotEqual (And (varPcieLinkControlData, 0x3), 0x0)) { - procPciDwordRMW (Local3, varPcieLinkControlOffset, Not (0x00000003), 0x00) - Store ("Disable ASPM on EP Complete!!", Debug) - } - } - Increment (Local2) - Increment (Local3) - } + Store (Concatenate (" Function number of Secondary Bus : ", ToHexString (varFunctionLocal4), varStringBuffer), Debug) + Store (Concatenate (" PcieLinkControl register offset : ", ToHexString (varPcieLinkControlOffset), varStringBuffer), Debug) + // Save ASPM on EP + Store (procPciDwordRead (Add (varEndpointBdfLocal2, varFunctionLocal4) , varPcieLinkControlOffset), varPcieLinkControlData) + Store (And (varPcieLinkControlData, 0x3), Index (varPcieLinkControlArray, varFunctionLocal4)) - } else { + Store (Concatenate (" PcieLinkControl Data : ", ToHexString (varPcieLinkControlData), varStringBuffer), Debug) - Store (procPcieSbAspmControl (0, 0), varAXCFGx68_PmCtrl) - And (varAXCFGx68_PmCtrl, 0x3, Local1) - if (LNotEqual (Local1, 0x0)) { - procPcieSbAspmControl (0, 1) - } - } - Store (1, Local2) - while (Local2) { - //retrain port - procPciDwordRMW (Local0, 0x68, Not (0x00000000), 0x20) - Sleep (30) - while (And (procPciDwordRead (Local0, 0x68), 0x08000000)) {Sleep (10)} - Store (0, Local2) - if (LEqual (Arg1, 0x2)) { // if Gen1 - Store (procPciePortIndirectRegisterRead (Arg0, 0xA4), varLcCurrentDataRate) - if (LNotEqual (And (varLcCurrentDataRate, 0x800), 0)) { - Store (1, Local2) - } - } - } - //restore ASPM setting - if (LNotEqual (Arg0, 6)) { - // Restore EP - //if (LNotEqual (varPcieLinkControlOffset, 0)) { - // procPciDwordWrite (Local3, varPcieLinkControlOffset, varPcieLinkControlData) - //} - Store (ShiftLeft (varSecondaryBus, 8), Local3) - Store (0, Local2) - while (LLessEqual (Local2, varMultiFunction)) { - - //Find PcieLinkControl register offset = PcieCapPtr + 0x10 - Store (procFindPciCapability (Local3, 0x10), varPcieLinkControlOffset) - if (LNotEqual (varPcieLinkControlOffset, 0)) { - Add (varPcieLinkControlOffset, 0x10, varPcieLinkControlOffset) - - Store ("Restore Function number of SecondaryBus = ", Debug) - Store (Local2, Debug) - Store ("Restore Find PcieLinkControl register offset = ", Debug) - Store (varPcieLinkControlOffset, Debug) - Store ("Restore ASPM = ", Debug) - Store (DerefOf (Index (varPcieLinkControlArray, Local2)), Debug) - procPciDwordWrite (Local3, varPcieLinkControlOffset, DerefOf (Index (varPcieLinkControlArray, Local2))) - } - Increment (Local2) - Increment (Local3) - } + procPciDwordRMW (Add (varEndpointBdfLocal2, varFunctionLocal4), varPcieLinkControlOffset, Not (0x00000003), 0x00) + Store ("Disable ASPM on EP Complete!!", Debug) + Increment (varFunctionLocal4) + } + } + /*----------------------------------------------------------------------------------------*/ + /** + * Restore ASPM + * + * Arg0 - Port Index + */ + Method (procRestoreAspm, 1, Serialized) { - } else { - // Restore SB - procPcieSbAspmControl (varAXCFGx68_PmCtrl, 1) - } - } else { - Store (" Device not present. Set capability and speed only", Debug) - } - //If request for UMI hide port congig space - if (LEqual (Arg0, 6)) { - procIndirectRegisterRMW (0x0, 0x60, 0x80, Not (0x40), 0x00); + Store (0, varPcieLinkControlOffset) + Store (0, varPcieLinkControlData) + + + // Restore SB ASPM + if (LEqual (Arg0, 6)) { + Store (" Restore SB ASPM", Debug) + Store (Concatenate (" PcieLinkControl Data : ", ToHexString (DerefOf(Index (varPcieLinkControlArray, 0))), varStringBuffer), Debug) + procPcieSbAspmControl (DerefOf(Index (varPcieLinkControlArray, 0)), 1) + return (0) + } + Store (ShiftLeft (Add( Arg0, 2), 3), varPortBdfLocal1) + // Restore EP ASPM + Store (procPciDwordRead (varPortBdfLocal1, 0x18), varTempLocal3) + Store (And (ShiftRight (varTempLocal3, 8), 0xFF), varTempLocal3) + + Store (Concatenate (" Disable EP ASPM on SecondaryBus : ", ToHexString (varTempLocal3), varStringBuffer), Debug) + + Store (ShiftLeft (varTempLocal3, 8), varEndpointBdfLocal2) + Store (procPciDwordRead (varEndpointBdfLocal2, 0xC), varTempLocal3) + Store (And (ShiftRight (varTempLocal3, 16), 0xFF), varTempLocal3) + + Store (Concatenate (" EP Header type : ", ToHexString (varTempLocal3), varStringBuffer), Debug) + + if (LNotEqual (And (varTempLocal3, 0x80), 0)) { + Store (0x7, varMaxFunctionLocal0) + } else { + Store (0x0, varMaxFunctionLocal0) + } + Store (0, varFunctionLocal4) + while (LLessEqual (varFunctionLocal4, varMaxFunctionLocal0)) { + //Find PcieLinkControl register offset = PcieCapPtr + 0x10 + Store (procFindPciCapability (Add (varEndpointBdfLocal2, varFunctionLocal4), 0x10), varPcieLinkControlOffset) + if (LEqual (varPcieLinkControlOffset, 0)) { + Increment (varFunctionLocal4) + continue } + Add (varPcieLinkControlOffset, 0x10, varPcieLinkControlOffset) + + Store (Concatenate (" Restore Function number of SecondaryBus : ", ToHexString (varFunctionLocal4), varStringBuffer), Debug) + Store (Concatenate (" Restore PcieLinkControl register offset : ", ToHexString (varPcieLinkControlOffset), varStringBuffer), Debug) + Store (Concatenate (" PcieLinkControl Data : ", ToHexString (DerefOf (Index (varPcieLinkControlArray, varFunctionLocal4))), varStringBuffer), Debug) + + procPciDwordWrite (Add (varEndpointBdfLocal2, varFunctionLocal4), varPcieLinkControlOffset, DerefOf (Index (varPcieLinkControlArray, varFunctionLocal4))) + Increment (varFunctionLocal4) + } + } + + /*----------------------------------------------------------------------------------------*/ + /** + * Request VID + * + * Arg0 - Port Index + * Arg1 - PCIe speed + */ + + Method (procPcieSetLinkSpeed, 2) { + Store (ShiftLeft (Add( Arg0, 2), 3), Local0) + if (LEqual (Arg1, DEF_LINK_SPEED_GEN1)) { + procPciDwordRMW (Local0, 0x88, Not (0x0000002f), 0x21) + procPciePortIndirectRegisterRMW (Arg0, 0xA4, Not (0x20000001), 0x0) + } else { + procPciePortIndirectRegisterRMW (Arg0, 0xA4, Not (0x20000001), 0x20000001) + procPciDwordRMW (Local0, 0x88, Not (0x0000002f), 0x2) } - Store ("SetPortCapabilityAndSpeed Exit", Debug) } - Mutex (varVoltageChangeMutex, 0) + + /*----------------------------------------------------------------------------------------*/ /** * Request VID @@ -636,18 +725,17 @@ * Arg1 - 0 = do not wait intil voltage is set * 1 = wait until voltage is set */ - Method (procPcieSetVoltage, 2) { - Store ("PcieSetVoltage(procPcieSetVoltage) Enter", Debug) - Acquire(varVoltageChangeMutex, 0xFFFF) + Method (procPcieSetVoltage, 2, Serialized) { + Store ("PcieSetVoltage Enter", Debug) Store (procIndirectRegisterRead (0x0, 0x60, 0xEA), Local1) //Enable voltage change Or (Local1, 0x2, Local1) procIndirectRegisterWrite (0x0, 0x60, 0xEA, Local1) //Clear voltage index And (Local1, Not (ShiftLeft (0x3, 3)), Local1) + + Store (Concatenate (" Voltage Index:", ToHexString (Arg0), Local6), Debug) //Set new voltage index - Store (" Voltage Index:", Debug) - Store (Arg0, Debug) Or (Local1, ShiftLeft (Arg0, 3), Local1) //Togle request And (Not (Local1), 0x4, Local2) @@ -658,8 +746,7 @@ And (procIndirectRegisterRead (0x0, 0x60, 0xEB), 0x1, Local1) } } - Release (varVoltageChangeMutex) - Store ("PcieSetVoltage(procPcieSetVoltage) Exit", Debug) + Store ("PcieSetVoltage Exit", Debug) } /*----------------------------------------------------------------------------------------*/ @@ -680,3 +767,14 @@ } } + /*----------------------------------------------------------------------------------------*/ + /** + * Read PCIe port indirect register + * + * Arg0 - Ref Source Pckage + * Arg1 - Ref to Destination Package + * + */ + Method (procPsppGetAcDcState, 0 , NotSerialized) { + Return (And (varPsppAcDcState, varPsppAcDcOverride)) + } diff --git a/src/vendorcode/amd/agesa/f14/Proc/GNB/Modules/GnbPcieConfig/PcieConfigData.c b/src/vendorcode/amd/agesa/f14/Proc/GNB/Modules/GnbPcieConfig/PcieConfigData.c index 30ebb61e28..d911847f71 100644 --- a/src/vendorcode/amd/agesa/f14/Proc/GNB/Modules/GnbPcieConfig/PcieConfigData.c +++ b/src/vendorcode/amd/agesa/f14/Proc/GNB/Modules/GnbPcieConfig/PcieConfigData.c @@ -52,11 +52,13 @@ #include "Ids.h" #include "amdlib.h" #include "heapManager.h" +#include "OptionGnb.h" #include "Gnb.h" #include "GnbPcie.h" #include "GnbPcieFamServices.h" #include GNB_MODULE_DEFINITIONS (GnbCommonLib) #include GNB_MODULE_DEFINITIONS (GnbPcieConfig) +#include "PcieConfigData.h" #include "PcieMapTopology.h" #include "PcieInputParser.h" #include "Filecode.h" @@ -70,6 +72,7 @@ #define REBASE_PTR( Ptr, OldBase, NewBase) *(UINTN *)Ptr = (*(UINTN *)Ptr + (UINTN) NewBase - (UINTN) OldBase); extern BUILD_OPT_CFG UserOptions; +extern GNB_BUILD_OPTIONS ROMDATA GnbBuildOptions; /*---------------------------------------------------------------------------------------- * T Y P E D E F S A N D S T R U C T U R E S @@ -139,7 +142,7 @@ PcieConfigurationInit ( return AGESA_FATAL; } LibAmdMemFill (Pcie, 0x00, sizeof (PCIe_PLATFORM_CONFIG) + ComplexesDataLength, StdHeader); - Pcie->StdHeader = (PVOID) StdHeader; + Pcie->StdHeader = StdHeader; Pcie->This = (UINTN) (Pcie); Buffer = (UINT8 *) (Pcie) + sizeof (PCIe_PLATFORM_CONFIG); ComplexIndex = 0; @@ -150,7 +153,7 @@ PcieConfigurationInit ( IDS_ERROR_TRAP; return AGESA_FATAL; } - Pcie->ComplexList[ComplexIndex].SiliconList = (PPCIe_SILICON_CONFIG) Buffer; + Pcie->ComplexList[ComplexIndex].SiliconList = (PCIe_SILICON_CONFIG *) &Buffer; PcieFmBuildComplexConfiguration (Buffer, StdHeader); for (Index = 0; Index < NumberOfComplexes; Index++) { ComplexDescriptor = PcieInputParserGetComplexDescriptor (ComplexList, Index); @@ -165,11 +168,13 @@ PcieConfigurationInit ( } } Pcie->ComplexList[ComplexIndex - 1].Flags |= DESCRIPTOR_TERMINATE_LIST; - Pcie->LinkReceiverDetectionPooling = PCIE_LINK_RECEIVER_DETECTION_POOLING; - Pcie->LinkL0Pooling = PCIE_LINK_L0_POOLING; - Pcie->LinkGpioResetAssertionTime = PCIE_LINK_GPIO_RESET_ASSERT_TIME; - Pcie->LinkResetToTrainingTime = PCIE_LINK_RESET_TO_TRAINING_TIME; + Pcie->LinkReceiverDetectionPooling = GnbBuildOptions.LinkReceiverDetectionPooling; + Pcie->LinkL0Pooling = GnbBuildOptions.LinkL0Pooling; + Pcie->LinkGpioResetAssertionTime = GnbBuildOptions.LinkGpioResetAssertionTime; + Pcie->LinkResetToTrainingTime = GnbBuildOptions.LinkResetToTrainingTime; Pcie->GfxCardWorkaround = GfxWorkaroundEnable; + Pcie->TrainingExitState = LinkStateTrainingCompleted; + Pcie->TrainingAlgorithm = GnbBuildOptions.TrainingAlgorithm; if ((UserOptions.CfgAmdPlatformType & AMD_PLATFORM_MOBILE) != 0) { Pcie->GfxCardWorkaround = GfxWorkaroundDisable; } @@ -217,7 +222,7 @@ PcieLocateConfigurationData ( } (*Pcie)->This = (UINTN)(*Pcie); } - (*Pcie)->StdHeader = (PVOID) StdHeader; + (*Pcie)->StdHeader = StdHeader; return AGESA_SUCCESS; } diff --git a/src/vendorcode/amd/agesa/f14/Proc/GNB/Modules/GnbPcieConfig/PcieConfigData.h b/src/vendorcode/amd/agesa/f14/Proc/GNB/Modules/GnbPcieConfig/PcieConfigData.h index f40a123a52..c3e1cd39a9 100644 --- a/src/vendorcode/amd/agesa/f14/Proc/GNB/Modules/GnbPcieConfig/PcieConfigData.h +++ b/src/vendorcode/amd/agesa/f14/Proc/GNB/Modules/GnbPcieConfig/PcieConfigData.h @@ -47,6 +47,10 @@ #ifndef _PCIECONFIGDATA_H_ #define _PCIECONFIGDATA_H_ +AGESA_STATUS +PcieConfigurationInit ( + IN AMD_CONFIG_PARAMS *StdHeader + ); AGESA_STATUS PcieLocateConfigurationData ( diff --git a/src/vendorcode/amd/agesa/f14/Proc/GNB/Modules/GnbPcieConfig/PcieConfigLib.c b/src/vendorcode/amd/agesa/f14/Proc/GNB/Modules/GnbPcieConfig/PcieConfigLib.c index 616e1d5e2a..cbae86d7a9 100644 --- a/src/vendorcode/amd/agesa/f14/Proc/GNB/Modules/GnbPcieConfig/PcieConfigLib.c +++ b/src/vendorcode/amd/agesa/f14/Proc/GNB/Modules/GnbPcieConfig/PcieConfigLib.c @@ -158,7 +158,7 @@ PcieConfigGetEnginePhyLaneBitMap ( UINT32 LaneBitMap; LaneBitMap = 0; if (PcieLibIsEngineAllocated (Engine)) { - LaneBitMap = ((1 << PcieConfigGetNumberOfPhyLane (Engine)) - 1) << (PcieUtilGetLoPhyLane (Engine) - PcieEngineGetParentWrapper (Engine)->StartPhyLane); + LaneBitMap = ((1 << PcieConfigGetNumberOfPhyLane (Engine)) - 1) << (PcieLibGetLoPhyLane (Engine) - PcieEngineGetParentWrapper (Engine)->StartPhyLane); } return LaneBitMap; } diff --git a/src/vendorcode/amd/agesa/f14/Proc/GNB/Modules/GnbPcieConfig/PcieInputParser.c b/src/vendorcode/amd/agesa/f14/Proc/GNB/Modules/GnbPcieConfig/PcieInputParser.c index 6a9da54ee7..1f762c35a2 100644 --- a/src/vendorcode/amd/agesa/f14/Proc/GNB/Modules/GnbPcieConfig/PcieInputParser.c +++ b/src/vendorcode/amd/agesa/f14/Proc/GNB/Modules/GnbPcieConfig/PcieInputParser.c @@ -52,6 +52,7 @@ #include "Ids.h" #include "Gnb.h" #include "GnbPcie.h" +#include "PcieInputParser.h" #include "Filecode.h" #define FILECODE PROC_GNB_MODULES_GNBPCIECONFIG_PCIEINPUTPARSER_FILECODE /*---------------------------------------------------------------------------------------- @@ -70,7 +71,15 @@ * P R O T O T Y P E S O F L O C A L F U N C T I O N S *---------------------------------------------------------------------------------------- */ +UINTN +PcieInputParserGetLengthOfPcieEnginesList ( + IN PCIe_COMPLEX_DESCRIPTOR *Complex + ); +UINTN +PcieInputParserGetLengthOfDdiEnginesList ( + IN PCIe_COMPLEX_DESCRIPTOR *Complex + ); /*----------------------------------------------------------------------------------------*/ diff --git a/src/vendorcode/amd/agesa/f14/Proc/GNB/Modules/GnbPcieConfig/PcieMapTopology.c b/src/vendorcode/amd/agesa/f14/Proc/GNB/Modules/GnbPcieConfig/PcieMapTopology.c index 70215514e2..30451717a0 100644 --- a/src/vendorcode/amd/agesa/f14/Proc/GNB/Modules/GnbPcieConfig/PcieMapTopology.c +++ b/src/vendorcode/amd/agesa/f14/Proc/GNB/Modules/GnbPcieConfig/PcieMapTopology.c @@ -77,6 +77,12 @@ *---------------------------------------------------------------------------------------- */ +AGESA_STATUS +PcieEnginesToWrapper ( + IN PCIE_ENGINE_TYPE EngineType, + IN PCIe_COMPLEX_DESCRIPTOR *ComplexDescriptor, + IN PCIe_WRAPPER_CONFIG *Wrapper + ); AGESA_STATUS STATIC diff --git a/src/vendorcode/amd/agesa/f14/Proc/GNB/Modules/GnbPcieInitLibV1/PcieAspm.c b/src/vendorcode/amd/agesa/f14/Proc/GNB/Modules/GnbPcieInitLibV1/PcieAspm.c index 07b42315d8..80210d1700 100644 --- a/src/vendorcode/amd/agesa/f14/Proc/GNB/Modules/GnbPcieInitLibV1/PcieAspm.c +++ b/src/vendorcode/amd/agesa/f14/Proc/GNB/Modules/GnbPcieInitLibV1/PcieAspm.c @@ -88,6 +88,20 @@ PcieAspmCallback ( ); VOID +PcieAspmEnableOnFunction ( + IN PCI_ADDR Function, + IN PCIE_ASPM_TYPE Aspm, + IN AMD_CONFIG_PARAMS *StdHeader + ); + +VOID +PcieAspmEnableOnDevice ( + IN PCI_ADDR Device, + IN PCIE_ASPM_TYPE Aspm, + IN AMD_CONFIG_PARAMS *StdHeader + ); + +VOID PcieAspmEnableOnLink ( IN PCI_ADDR Downstream, IN PCI_ADDR Upstream, @@ -217,7 +231,7 @@ PcieAspmEnableOnFunction ( GnbLibPciRMW ( Function.AddressValue | (PcieCapPtr + PCIE_LINK_CTRL_REGISTER) , AccessS3SaveWidth8, - ~(BIT0 & BIT1), + ~(UINT32)(BIT0 & BIT1), Aspm, StdHeader ); diff --git a/src/vendorcode/amd/agesa/f14/Proc/GNB/Modules/GnbPcieInitLibV1/PcieAspmBlackList.c b/src/vendorcode/amd/agesa/f14/Proc/GNB/Modules/GnbPcieInitLibV1/PcieAspmBlackList.c index ecb6b4344a..8192b3d0c4 100644 --- a/src/vendorcode/amd/agesa/f14/Proc/GNB/Modules/GnbPcieInitLibV1/PcieAspmBlackList.c +++ b/src/vendorcode/amd/agesa/f14/Proc/GNB/Modules/GnbPcieInitLibV1/PcieAspmBlackList.c @@ -94,7 +94,8 @@ UINT16 AspmBrDeviceTable[] = { 0x10DE, 0x016A, (UINT16) ~(AspmL1 | AspmL0s), 0x10DE, 0x0392, (UINT16) ~(AspmL1 | AspmL0s), 0x168C, 0xFFFF, (UINT16) ~(AspmL0s), - 0x1B4B, 0x91A3, (UINT16) ~(AspmL0s) + 0x1B4B, 0x91A3, (UINT16) ~(AspmL0s), + 0x1B4B, 0x9123, (UINT16) ~(AspmL0s) }; /*----------------------------------------------------------------------------------------*/ diff --git a/src/vendorcode/amd/agesa/f14/Proc/GNB/Modules/GnbPcieInitLibV1/PciePifServices.c b/src/vendorcode/amd/agesa/f14/Proc/GNB/Modules/GnbPcieInitLibV1/PciePifServices.c index 717a80a158..86335120fb 100644 --- a/src/vendorcode/amd/agesa/f14/Proc/GNB/Modules/GnbPcieInitLibV1/PciePifServices.c +++ b/src/vendorcode/amd/agesa/f14/Proc/GNB/Modules/GnbPcieInitLibV1/PciePifServices.c @@ -399,7 +399,7 @@ PciePifSetPllModeForL1 ( D0F0xE4_PIF_0012.Field.TxPowerStateInTxs2 = PifPowerStateLS2; D0F0xE4_PIF_0012.Field.PllPowerStateInTxs2 = PifPowerStateOff; D0F0xE4_PIF_0012.Field.PllPowerStateInOff = PifPowerStateOff; - D0F0xE4_PIF_0012.Field.PllRampUpTime = 0x0; + D0F0xE4_PIF_0012.Field.PllRampUpTime = 0x1; PcieRegisterWrite ( Wrapper, PIF_SPACE (Wrapper->WrapId, (Nibble >> 1), D0F0xE4_PIF_0012_ADDRESS + (Nibble & 0x1)), diff --git a/src/vendorcode/amd/agesa/f14/Proc/GNB/Modules/GnbPcieInitLibV1/PciePortRegAcc.c b/src/vendorcode/amd/agesa/f14/Proc/GNB/Modules/GnbPcieInitLibV1/PciePortRegAcc.c index 491e148d15..55a205d890 100644 --- a/src/vendorcode/amd/agesa/f14/Proc/GNB/Modules/GnbPcieInitLibV1/PciePortRegAcc.c +++ b/src/vendorcode/amd/agesa/f14/Proc/GNB/Modules/GnbPcieInitLibV1/PciePortRegAcc.c @@ -55,6 +55,7 @@ #include "GnbPcie.h" #include "GnbPcieFamServices.h" #include GNB_MODULE_DEFINITIONS (GnbCommonLib) +#include "PciePortRegAcc.h" #include "Filecode.h" #define FILECODE PROC_GNB_MODULES_GNBPCIEINITLIBV1_PCIEPORTREGACC_FILECODE /*---------------------------------------------------------------------------------------- diff --git a/src/vendorcode/amd/agesa/f14/Proc/GNB/Modules/GnbPcieInitLibV1/PciePortServices.c b/src/vendorcode/amd/agesa/f14/Proc/GNB/Modules/GnbPcieInitLibV1/PciePortServices.c index b2c490f122..19bd1c5a25 100644 --- a/src/vendorcode/amd/agesa/f14/Proc/GNB/Modules/GnbPcieInitLibV1/PciePortServices.c +++ b/src/vendorcode/amd/agesa/f14/Proc/GNB/Modules/GnbPcieInitLibV1/PciePortServices.c @@ -240,7 +240,6 @@ PcieLinkSafeMode ( IN PCIe_PLATFORM_CONFIG *Pcie ) { - Engine->Type.Port.PortData.LinkSpeedCapability = PcieGen1; PcieSetLinkSpeedCap (PcieGen1, Engine, Pcie); PciePortRegisterRMW ( Engine, diff --git a/src/vendorcode/amd/agesa/f14/Proc/GNB/Modules/GnbPcieInitLibV1/PciePowerMgmt.c b/src/vendorcode/amd/agesa/f14/Proc/GNB/Modules/GnbPcieInitLibV1/PciePowerMgmt.c index 0dae507a47..a5a9e354f8 100644 --- a/src/vendorcode/amd/agesa/f14/Proc/GNB/Modules/GnbPcieInitLibV1/PciePowerMgmt.c +++ b/src/vendorcode/amd/agesa/f14/Proc/GNB/Modules/GnbPcieInitLibV1/PciePowerMgmt.c @@ -258,6 +258,7 @@ PciePwrClockGating ( WRAP_SPACE (Wrapper->WrapId, D0F0xE4_WRAP_8014_ADDRESS), Pcie ); + D0F0xE4_WRAP_8012.Value = PcieRegisterRead ( Wrapper, WRAP_SPACE (Wrapper->WrapId, D0F0xE4_WRAP_8012_ADDRESS), diff --git a/src/vendorcode/amd/agesa/f14/Proc/GNB/Modules/GnbPcieInitLibV1/PcieSbLink.c b/src/vendorcode/amd/agesa/f14/Proc/GNB/Modules/GnbPcieInitLibV1/PcieSbLink.c index 122a9e305b..09f9bab4ae 100644 --- a/src/vendorcode/amd/agesa/f14/Proc/GNB/Modules/GnbPcieInitLibV1/PcieSbLink.c +++ b/src/vendorcode/amd/agesa/f14/Proc/GNB/Modules/GnbPcieInitLibV1/PcieSbLink.c @@ -154,15 +154,18 @@ PcieSbAgetAlinkIoAddress ( ) { UINT8 AlinkPortIndex; + if (AlinkPort == NULL) { + return AGESA_UNSUPPORTED; + } AlinkPortIndex = 0xE0; GnbLibIoWrite (0xCD6, AccessWidth8, &AlinkPortIndex, StdHeader); GnbLibIoRead (0xCD7, AccessWidth8, AlinkPort, StdHeader); AlinkPortIndex = 0xE1; GnbLibIoWrite (0xCD6, AccessWidth8, &AlinkPortIndex, StdHeader); GnbLibIoRead (0xCD7, AccessWidth8, (VOID*) ((UINT8*) AlinkPort + 1), StdHeader); - if (&AlinkPort == 0) { - return AGESA_UNSUPPORTED; - } +// if (&AlinkPort == 0) { +// return AGESA_UNSUPPORTED; +// } return AGESA_SUCCESS; } @@ -192,7 +195,7 @@ PcieNbAspmEnable ( GnbLibPciRMW ( Function.AddressValue | (PcieCapPtr + PCIE_LINK_CTRL_REGISTER) , AccessS3SaveWidth8, - ~(BIT0 | BIT1), + ~(UINT32)(BIT0 | BIT1), Aspm, StdHeader ); diff --git a/src/vendorcode/amd/agesa/f14/Proc/GNB/Modules/GnbPcieInitLibV1/PcieSiliconServices.c b/src/vendorcode/amd/agesa/f14/Proc/GNB/Modules/GnbPcieInitLibV1/PcieSiliconServices.c index c298337840..eafcce494f 100644 --- a/src/vendorcode/amd/agesa/f14/Proc/GNB/Modules/GnbPcieInitLibV1/PcieSiliconServices.c +++ b/src/vendorcode/amd/agesa/f14/Proc/GNB/Modules/GnbPcieInitLibV1/PcieSiliconServices.c @@ -185,7 +185,7 @@ PcieSiliconUnHidePorts ( Silicon->Address.AddressValue | D0F0x60_ADDRESS, D0F0x64_x0C_ADDRESS | IOC_WRITE_ENABLE, AccessS3SaveWidth32, - ~(BIT2 | BIT3 | BIT4 | BIT5 | BIT6 | BIT7), + ~(UINT32)(BIT2 | BIT3 | BIT4 | BIT5 | BIT6 | BIT7), 0x0, GnbLibGetHeader (Pcie) ); @@ -193,7 +193,7 @@ PcieSiliconUnHidePorts ( Silicon->Address.AddressValue | D0F0x60_ADDRESS, D0F0x64_x00_ADDRESS | IOC_WRITE_ENABLE, AccessS3SaveWidth32, - ~BIT6, + ~(UINT32)BIT6, BIT6, GnbLibGetHeader (Pcie) ); @@ -239,7 +239,7 @@ PcieSiliconHidePorts ( Silicon->Address.AddressValue | D0F0x60_ADDRESS, D0F0x64_x0C_ADDRESS | IOC_WRITE_ENABLE, AccessS3SaveWidth32, - ~(BIT2 | BIT3 | BIT4 | BIT5 | BIT6 | BIT7), + ~(UINT32)(BIT2 | BIT3 | BIT4 | BIT5 | BIT6 | BIT7), D0F0x64_x0C.Value, GnbLibGetHeader (Pcie) ); @@ -247,7 +247,7 @@ PcieSiliconHidePorts ( Silicon->Address.AddressValue | D0F0x60_ADDRESS, D0F0x64_x00_ADDRESS | IOC_WRITE_ENABLE, AccessS3SaveWidth32, - ~BIT6, + ~(UINT32)BIT6, 0x0, GnbLibGetHeader (Pcie) ); diff --git a/src/vendorcode/amd/agesa/f14/Proc/GNB/Modules/GnbPcieInitLibV1/PcieSmuLib.esl b/src/vendorcode/amd/agesa/f14/Proc/GNB/Modules/GnbPcieInitLibV1/PcieSmuLib.esl index 5ca83524a4..43b1d62de0 100644 --- a/src/vendorcode/amd/agesa/f14/Proc/GNB/Modules/GnbPcieInitLibV1/PcieSmuLib.esl +++ b/src/vendorcode/amd/agesa/f14/Proc/GNB/Modules/GnbPcieInitLibV1/PcieSmuLib.esl @@ -130,7 +130,7 @@ } } // Clear IRQ register - procNbSmuIndirectRegisterWrite (0x3, 0, 0) + procNbSmuIndirectRegisterWrite (0x3, 0, 1) Store ("NbSmuServiceRequest Exit", Debug) } diff --git a/src/vendorcode/amd/agesa/f14/Proc/GNB/Modules/GnbPcieInitLibV1/PcieTopologyServices.c b/src/vendorcode/amd/agesa/f14/Proc/GNB/Modules/GnbPcieInitLibV1/PcieTopologyServices.c index 2bddde40f1..ae9fd5c629 100644 --- a/src/vendorcode/amd/agesa/f14/Proc/GNB/Modules/GnbPcieInitLibV1/PcieTopologyServices.c +++ b/src/vendorcode/amd/agesa/f14/Proc/GNB/Modules/GnbPcieInitLibV1/PcieTopologyServices.c @@ -76,6 +76,11 @@ * P R O T O T Y P E S O F L O C A L F U N C T I O N S *---------------------------------------------------------------------------------------- */ +UINT8 +PcieTopologyLocateMuxIndex ( + IN OUT UINT8 *LaneMuxSelectorArrayPtr, + IN UINT8 LaneMuxValue + ); /*----------------------------------------------------------------------------------------*/ @@ -199,7 +204,7 @@ PcieTopologyApplyLaneMux ( ); while (EngineList != NULL) { if (PcieLibIsPcieEngine (EngineList) && PcieLibIsEngineAllocated (EngineList)) { - CurrentPhyLane = (UINT8) PcieUtilGetLoPhyLane (EngineList) - Wrapper->StartPhyLane; + CurrentPhyLane = (UINT8) PcieLibGetLoPhyLane (EngineList) - Wrapper->StartPhyLane; NumberOfPhyLane = (UINT8) PcieConfigGetNumberOfPhyLane (EngineList); CurrentCoreLane = (UINT8) EngineList->Type.Port.StartCoreLane; if (PcieUtilIsLinkReversed (FALSE, EngineList, Pcie)) { @@ -505,7 +510,7 @@ PcieTopologyLaneControl ( Wrapper, WRAP_SPACE (Wrapper->WrapId, D0F0xE4_WRAP_8023_ADDRESS), D0F0xE4_WRAP_8023.Value, - FALSE, + TRUE, Pcie ); } diff --git a/src/vendorcode/amd/agesa/f14/Proc/GNB/Modules/GnbPcieInitLibV1/PcieUtilityLib.c b/src/vendorcode/amd/agesa/f14/Proc/GNB/Modules/GnbPcieInitLibV1/PcieUtilityLib.c index ef868203dd..00fca78857 100644 --- a/src/vendorcode/amd/agesa/f14/Proc/GNB/Modules/GnbPcieInitLibV1/PcieUtilityLib.c +++ b/src/vendorcode/amd/agesa/f14/Proc/GNB/Modules/GnbPcieInitLibV1/PcieUtilityLib.c @@ -303,7 +303,7 @@ PcieUtilGetEngineLaneBitMap ( if ((IncludeLaneType & LANE_TYPE_DDI_LANES) && Engine->EngineData.EngineType == PcieDdiEngine) { if (PcieLibIsEngineAllocated (Engine)) { if (IncludeLaneType & (LANE_TYPE_DDI_ALLOCATED | LANE_TYPE_DDI_ALL)) { - LaneOffset = PcieUtilGetLoPhyLane (Engine) - PcieEngineGetParentWrapper (Engine)->StartPhyLane; + LaneOffset = PcieLibGetLoPhyLane (Engine) - PcieEngineGetParentWrapper (Engine)->StartPhyLane; LaneBitmap |= ((1 << PcieConfigGetNumberOfPhyLane (Engine)) - 1) << LaneOffset; } if (IncludeLaneType & LANE_TYPE_DDI_ACTIVE) { diff --git a/src/vendorcode/amd/agesa/f14/Proc/GNB/Modules/GnbPcieTrainingV1/PcieTraining.c b/src/vendorcode/amd/agesa/f14/Proc/GNB/Modules/GnbPcieTrainingV1/PcieTraining.c index ada2ccbcb9..5a5faf32bc 100644 --- a/src/vendorcode/amd/agesa/f14/Proc/GNB/Modules/GnbPcieTrainingV1/PcieTraining.c +++ b/src/vendorcode/amd/agesa/f14/Proc/GNB/Modules/GnbPcieTrainingV1/PcieTraining.c @@ -58,6 +58,7 @@ #include GNB_MODULE_DEFINITIONS (GnbPcieConfig) #include GNB_MODULE_DEFINITIONS (GnbPcieInitLibV1) #include "PcieWorkarounds.h" +#include "PcieTraining.h" #include "GnbRegistersON.h" #include "Filecode.h" #define FILECODE PROC_GNB_MODULES_GNBPCIETRAININGV1_PCIETRAINING_FILECODE @@ -77,14 +78,45 @@ * P R O T O T Y P E S O F L O C A L F U N C T I O N S *---------------------------------------------------------------------------------------- */ +VOID +PcieSetResetStateOnEngines ( + IN PCIe_ENGINE_CONFIG *Engine, + IN OUT VOID *Buffer, + IN PCIe_PLATFORM_CONFIG *Pcie + ); VOID -STATIC -PcieTrainingDebugDumpPortState ( +PcieTrainingCheckResetDuration ( + IN PCIe_ENGINE_CONFIG *CurrentEngine, + IN PCIe_PLATFORM_CONFIG *Pcie + ); + +VOID +PcieTrainingDeassertReset ( IN PCIe_ENGINE_CONFIG *CurrentEngine, IN PCIe_PLATFORM_CONFIG *Pcie ); +VOID +PcieTrainingBrokenLine ( + IN PCIe_ENGINE_CONFIG *CurrentEngine, + IN PCIe_PLATFORM_CONFIG *Pcie + ); + +VOID +PcieTrainingGen2Fail ( + IN PCIe_ENGINE_CONFIG *CurrentEngine, + IN PCIe_PLATFORM_CONFIG *Pcie + ); + +GNB_DEBUG_CODE ( + VOID + STATIC + PcieTrainingDebugDumpPortState ( + IN PCIe_ENGINE_CONFIG *CurrentEngine, + IN PCIe_PLATFORM_CONFIG *Pcie + ); +) /*----------------------------------------------------------------------------------------*/ /** @@ -114,6 +146,7 @@ PcieTrainingSetPortState ( GNB_DEBUG_CODE ( PcieTrainingDebugDumpPortState (CurrentEngine, Pcie) ); + } @@ -372,7 +405,7 @@ PcieTrainingBrokenLine ( UINT8 LinkTrainingState; CurrentLinkWidth = PcieUtilGetLinkWidth (CurrentEngine, Pcie); if (CurrentLinkWidth < PcieConfigGetNumberOfPhyLane (CurrentEngine) && CurrentLinkWidth > 0) { - CurrentEngine->InitStatus |= INIT_STATUS_PCIE_PORT_GEN2_RECOVERY; + CurrentEngine->InitStatus |= INIT_STATUS_PCIE_PORT_BROKEN_LANE_RECOVERY; PcieTopologyReduceLinkWidth (CurrentLinkWidth, CurrentEngine, Pcie); LinkTrainingState = LinkStateResetAssert; PutEventLog ( @@ -684,8 +717,10 @@ PcieTrainingPortCallback ( { BOOLEAN *TrainingComplete; TrainingComplete = (BOOLEAN *) Buffer; - if (Engine->Type.Port.State != LinkStateTrainingCompleted) { + if (Engine->Type.Port.State < Pcie->TrainingExitState) { *TrainingComplete = FALSE; + } else { + return; } switch (Engine->Type.Port.State) { case LinkStateResetAssert: @@ -793,6 +828,7 @@ PcieTraining ( * */ +GNB_DEBUG_CODE ( VOID STATIC PcieTrainingDebugDumpPortState ( @@ -826,3 +862,4 @@ PcieTrainingDebugDumpPortState ( CurrentEngine->Type.Port.TimeStamp ); } +)
\ No newline at end of file diff --git a/src/vendorcode/amd/agesa/f14/Proc/GNB/Modules/GnbPcieTrainingV1/PcieWorkarounds.c b/src/vendorcode/amd/agesa/f14/Proc/GNB/Modules/GnbPcieTrainingV1/PcieWorkarounds.c index 5191465096..c256eba2d8 100644 --- a/src/vendorcode/amd/agesa/f14/Proc/GNB/Modules/GnbPcieTrainingV1/PcieWorkarounds.c +++ b/src/vendorcode/amd/agesa/f14/Proc/GNB/Modules/GnbPcieTrainingV1/PcieWorkarounds.c @@ -56,6 +56,7 @@ #include GNB_MODULE_DEFINITIONS (GnbCommonLib) #include GNB_MODULE_DEFINITIONS (GnbPcieConfig) #include "GnbRegistersON.h" +#include "PcieWorkarounds.h" #include "Filecode.h" #define FILECODE PROC_GNB_MODULES_GNBPCIETRAININGV1_PCIEWORKAROUNDS_FILECODE /*---------------------------------------------------------------------------------------- @@ -190,7 +191,7 @@ PcieDeskewWorkaround ( return GFX_WORKAROUND_SUCCESS; } GnbLibPciWrite (Device.AddressValue | 0x18, AccessWidth32, &MmioBase, StdHeader); - GnbLibPciRMW (Device.AddressValue | 0x04, AccessWidth8 , ~BIT1, BIT1, StdHeader); + GnbLibPciRMW (Device.AddressValue | 0x04, AccessWidth8 , ~(UINT32)BIT1, BIT1, StdHeader); GnbLibMemRMW (MmioBase + 0x120, AccessWidth16, 0, 0xb700, StdHeader); GnbLibMemRead (MmioBase + 0x120, AccessWidth16, &MmioData1, StdHeader); if (MmioData1 == 0xb700) { @@ -203,7 +204,7 @@ PcieDeskewWorkaround ( } } } - GnbLibPciRMW (Device.AddressValue | 0x04, AccessWidth8, ~BIT1, 0x0, StdHeader); + GnbLibPciRMW (Device.AddressValue | 0x04, AccessWidth8, ~(UINT32)BIT1, 0x0, StdHeader); GnbLibPciRMW (Device.AddressValue | 0x18, AccessWidth32, 0x0, 0x0, StdHeader); return GFX_WORKAROUND_SUCCESS; diff --git a/src/vendorcode/amd/agesa/f14/Proc/GNB/Nb/Family/0x14/F14NbPowerGate.c b/src/vendorcode/amd/agesa/f14/Proc/GNB/Nb/Family/0x14/F14NbPowerGate.c index 8b717fb8bb..a1c2639fa1 100644 --- a/src/vendorcode/amd/agesa/f14/Proc/GNB/Nb/Family/0x14/F14NbPowerGate.c +++ b/src/vendorcode/amd/agesa/f14/Proc/GNB/Nb/Family/0x14/F14NbPowerGate.c @@ -61,6 +61,7 @@ #include "NbSmuLib.h" #include "NbConfigData.h" #include "NbFamilyServices.h" +#include "F14NbPowerGate.h" #include "GfxLib.h" #include "Filecode.h" #define FILECODE PROC_GNB_NB_FAMILY_0x14_F14NBPOWERGATE_FILECODE diff --git a/src/vendorcode/amd/agesa/f14/Proc/GNB/Nb/Family/0x14/F14NbServices.c b/src/vendorcode/amd/agesa/f14/Proc/GNB/Nb/Family/0x14/F14NbServices.c index e6c7265ea2..74e3bbc42f 100644 --- a/src/vendorcode/amd/agesa/f14/Proc/GNB/Nb/Family/0x14/F14NbServices.c +++ b/src/vendorcode/amd/agesa/f14/Proc/GNB/Nb/Family/0x14/F14NbServices.c @@ -9,7 +9,7 @@ * @xrefitem bom "File Content Label" "Release Content" * @e project: AGESA * @e sub-project: GNB - * @e \$Revision: 41363 $ @e \$Date: 2010-11-04 03:24:17 +0800 (Thu, 04 Nov 2010) $ + * @e \$Revision: 48498 $ @e \$Date: 2011-03-09 12:44:53 -0700 (Wed, 09 Mar 2011) $ * */ /* @@ -58,9 +58,11 @@ #include GNB_MODULE_DEFINITIONS (GnbCommonLib) #include GNB_MODULE_DEFINITIONS (GnbGfxInitLibV1) #include GNB_MODULE_DEFINITIONS (GnbPcieConfig) +#include "NbConfigData.h" #include "OptionGnb.h" #include "NbLclkDpm.h" #include "NbFamilyServices.h" +#include "NbPowerMgmt.h" #include "GfxLib.h" #include "GnbRegistersON.h" #include "cpuFamilyTranslation.h" @@ -85,6 +87,29 @@ FUSE_TABLE FuseTable; *---------------------------------------------------------------------------------------- */ +/*----------------------------------------------------------------------------------------*/ +/** + * NB family specific clock gating + * + * + * @param[in, out] NbClkGatingCtrl Pointer to NB_CLK_GATING_CTRL + * @param[in] StdHeader Pointer to AMD_CONFIG_PARAMS + */ +VOID +NbFmNbClockGating ( + IN OUT VOID *NbClkGatingCtrl, + IN AMD_CONFIG_PARAMS *StdHeader + ) +{ + NB_CLK_GATING_CTRL *NbClkGatingCtrlPtr; + CPU_LOGICAL_ID LogicalId; + + NbClkGatingCtrlPtr = (NB_CLK_GATING_CTRL *)NbClkGatingCtrl; + GetLogicalIdOfCurrentCore (&LogicalId, StdHeader); + if ((LogicalId.Revision & AMD_F14_ON_Cx) != 0) { + NbClkGatingCtrlPtr->Smu_Sclk_Gating = FALSE; + } +} /*----------------------------------------------------------------------------------------*/ /** @@ -184,7 +209,7 @@ NbFmFuseAdjustFuseTablePatch ( if (GfxLibIsControllerPresent (StdHeader)) { //VID index = VID index associated with highest SCLK DPM state in the Powerplay state where Label_Performance=1 // This would ignore the UVD case (where Label_Performance would be 0). for (SwSatateIndex = 0 ; SwSatateIndex < PP_FUSE_MAX_NUM_SW_STATE; SwSatateIndex++) { - if (PpFuseArray->PolicyLabel[SwSatateIndex] == 1) { + if (PpFuseArray->PolicyLabel[SwSatateIndex] == POLICY_LABEL_PERFORMANCE) { break; } } @@ -206,9 +231,13 @@ NbFmFuseAdjustFuseTablePatch ( } // - use fused values for LclkDpmDid[0,1,2] and appropriate voltage //Keep using actual fusing - IDS_HDT_CONSOLE (NB_MISC, " LCLK DPM use actaul fusing.\n"); + IDS_HDT_CONSOLE (NB_MISC, " LCLK DPM use actual fusing.\n"); } + //Patch SclkThermDid to 175Mhz if not fused + if (PpFuseArray->SclkThermDid == 0) { + PpFuseArray->SclkThermDid = GfxLibCalculateDid (175 * 100, GfxLibGetMainPllFreq (StdHeader) * 100); + } } @@ -434,7 +463,6 @@ FUSE_REGISTER_ENTRY FCRxFE00_70B9_TABLE [] = { } }; - FUSE_REGISTER_ENTRY FCRxFE00_70BC_TABLE [] = { { FCRxFE00_70BC_SclkDpmValid0_OFFSET, @@ -575,8 +603,86 @@ FUSE_REGISTER_ENTRY FCRxFE00_70C7_TABLE [] = { }, }; +FUSE_REGISTER_ENTRY FCRxFE00_70C8_TABLE [] = { + { + FCRxFE00_70C8_GpuBoostCap_OFFSET, + FCRxFE00_70C8_GpuBoostCap_WIDTH, + (UINT8) offsetof (PP_FUSE_ARRAY, GpuBoostCap) + }, + { + FCRxFE00_70C8_SclkDpmVid5_OFFSET, + FCRxFE00_70C8_SclkDpmVid5_WIDTH, + (UINT8) offsetof (PP_FUSE_ARRAY, SclkDpmVid[5]) + }, + { + FCRxFE00_70C8_SclkDpmDid5_OFFSET, + FCRxFE00_70C8_SclkDpmDid5_WIDTH, + (UINT8) offsetof (PP_FUSE_ARRAY, SclkDpmDid[5]) + }, +}; +FUSE_REGISTER_ENTRY FCRxFE00_70C9_TABLE [] = { + { + FCRxFE00_70C9_SclkDpmTdpLimit0_OFFSET, + FCRxFE00_70C9_SclkDpmTdpLimit0_WIDTH, + (UINT8) offsetof (PP_FUSE_ARRAY, SclkDpmTdpLimit[0]) + }, + { + FCRxFE00_70C9_SclkDpmTdpLimit1_OFFSET, + FCRxFE00_70C9_SclkDpmTdpLimit1_WIDTH, + (UINT8) offsetof (PP_FUSE_ARRAY, SclkDpmTdpLimit[1]) + } +}; +FUSE_REGISTER_ENTRY FCRxFE00_70CC_TABLE [] = { + { + FCRxFE00_70CC_SclkDpmTdpLimit2_OFFSET, + FCRxFE00_70CC_SclkDpmTdpLimit2_WIDTH, + (UINT8) offsetof (PP_FUSE_ARRAY, SclkDpmTdpLimit[2]) + }, + { + FCRxFE00_70CC_SclkDpmTdpLimit3_OFFSET, + FCRxFE00_70CC_SclkDpmTdpLimit3_WIDTH, + (UINT8) offsetof (PP_FUSE_ARRAY, SclkDpmTdpLimit[3]) + } +}; + +FUSE_REGISTER_ENTRY FCRxFE00_70CF_TABLE [] = { + { + FCRxFE00_70CF_SclkDpmTdpLimit4_OFFSET, + FCRxFE00_70CF_SclkDpmTdpLimit4_WIDTH, + (UINT8) offsetof (PP_FUSE_ARRAY, SclkDpmTdpLimit[4]) + }, + { + FCRxFE00_70CF_SclkDpmTdpLimit5_OFFSET, + FCRxFE00_70CF_SclkDpmTdpLimit5_WIDTH, + (UINT8) offsetof (PP_FUSE_ARRAY, SclkDpmTdpLimit[5]) + } +}; + +FUSE_REGISTER_ENTRY FCRxFE00_70D2_TABLE [] = { + { + FCRxFE00_70D2_SclkDpmTdpLimitPG_OFFSET, + FCRxFE00_70D2_SclkDpmTdpLimitPG_WIDTH, + (UINT8) offsetof (PP_FUSE_ARRAY, SclkDpmTdpLimitPG) + } +}; + +FUSE_REGISTER_ENTRY FCRxFE00_70D4_TABLE [] = { + { + FCRxFE00_70D4_SclkDpmBoostMargin_OFFSET, + FCRxFE00_70D4_SclkDpmBoostMargin_WIDTH, + (UINT8) offsetof (PP_FUSE_ARRAY, SclkDpmBoostMargin) + } +}; + +FUSE_REGISTER_ENTRY FCRxFE00_70D7_TABLE [] = { + { + FCRxFE00_70D7_SclkDpmThrottleMargin_OFFSET, + FCRxFE00_70D7_SclkDpmThrottleMargin_WIDTH, + (UINT8) offsetof (PP_FUSE_ARRAY, SclkDpmThrottleMargin) + } +}; FUSE_TABLE_ENTRY FuseRegisterTable [] = { { @@ -669,7 +775,41 @@ FUSE_TABLE_ENTRY FuseRegisterTable [] = { sizeof (FCRxFE00_70C7_TABLE) / sizeof (FUSE_REGISTER_ENTRY), FCRxFE00_70C7_TABLE }, - + { + FCRxFE00_70C8_ADDRESS, + sizeof (FCRxFE00_70C8_TABLE) / sizeof (FUSE_REGISTER_ENTRY), + FCRxFE00_70C8_TABLE + }, + { + FCRxFE00_70C9_ADDRESS, + sizeof (FCRxFE00_70C9_TABLE) / sizeof (FUSE_REGISTER_ENTRY), + FCRxFE00_70C9_TABLE + }, + { + FCRxFE00_70CC_ADDRESS, + sizeof (FCRxFE00_70CC_TABLE) / sizeof (FUSE_REGISTER_ENTRY), + FCRxFE00_70CC_TABLE + }, + { + FCRxFE00_70CF_ADDRESS, + sizeof (FCRxFE00_70CF_TABLE) / sizeof (FUSE_REGISTER_ENTRY), + FCRxFE00_70CF_TABLE + }, + { + FCRxFE00_70D2_ADDRESS, + sizeof (FCRxFE00_70D2_TABLE) / sizeof (FUSE_REGISTER_ENTRY), + FCRxFE00_70D2_TABLE + }, + { + FCRxFE00_70D4_ADDRESS, + sizeof (FCRxFE00_70D4_TABLE) / sizeof (FUSE_REGISTER_ENTRY), + FCRxFE00_70D4_TABLE + }, + { + FCRxFE00_70D7_ADDRESS, + sizeof (FCRxFE00_70D7_TABLE) / sizeof (FUSE_REGISTER_ENTRY), + FCRxFE00_70D7_TABLE + }, }; FUSE_TABLE FuseTable = { diff --git a/src/vendorcode/amd/agesa/f14/Proc/GNB/Nb/Family/0x14/F14NbSmu.c b/src/vendorcode/amd/agesa/f14/Proc/GNB/Nb/Family/0x14/F14NbSmu.c index 014e1a3ba0..a2ed861958 100644 --- a/src/vendorcode/amd/agesa/f14/Proc/GNB/Nb/Family/0x14/F14NbSmu.c +++ b/src/vendorcode/amd/agesa/f14/Proc/GNB/Nb/Family/0x14/F14NbSmu.c @@ -67,6 +67,10 @@ *---------------------------------------------------------------------------------------- */ +AGESA_STATUS +F14NbSmuInitFeature ( + IN AMD_CONFIG_PARAMS *StdHeader + ); /*----------------------------------------------------------------------------------------*/ diff --git a/src/vendorcode/amd/agesa/f14/Proc/GNB/Nb/Family/0x14/F14NbSmuFirmware.h b/src/vendorcode/amd/agesa/f14/Proc/GNB/Nb/Family/0x14/F14NbSmuFirmware.h index 80e6830799..b61f67ed5e 100644 --- a/src/vendorcode/amd/agesa/f14/Proc/GNB/Nb/Family/0x14/F14NbSmuFirmware.h +++ b/src/vendorcode/amd/agesa/f14/Proc/GNB/Nb/Family/0x14/F14NbSmuFirmware.h @@ -9,11 +9,11 @@ * @xrefitem bom "File Content Label" "Release Content" * @e project: AGESA * @e sub-project: GNB - * @e \$Revision: 37675 $ @e \$Date: 2010-09-09 22:33:48 +0800 (Thu, 09 Sep 2010) $ + * @e \$Revision: 51210 $ @e \$Date: 2011-04-20 11:41:43 -0600 (Wed, 20 Apr 2011) $ * */ /* - ***************************************************************************** + ****************************************************************************** * * Copyright (c) 2011, Advanced Micro Devices, Inc. * All rights reserved. @@ -40,8 +40,7 @@ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. * - * *************************************************************************** - * + ****************************************************************************** */ @@ -49,21 +48,22 @@ #define _F14NBSMUFIRMWARE_H_ UINT32 DataBlock0[] = { - 0x00020100, + 0x01060100, + 0x68d699d6, 0xbdff018e, - 0x00ce3d9d, + 0x00cea2a4, 0x00ce1810, 0xa6082000, 0x00a71800, 0x8c081808, 0xf3251000, 0x270000cc, - 0xda9dce0b, + 0x3fa5ce0b, 0x8308006f, 0xf8260100, - 0x9dbd248d, - 0x90fb2040, - 0xde20900a, + 0xa4bd248d, + 0x90fb20a5, + 0xde24900e, 0x02de3c00, 0x3c04de3c, 0x9f3c06de, @@ -76,115 +76,163 @@ UINT32 DataBlock0[] = { 0xfc02ed02, 0x00ed0090, 0x1caa7fce, - 0x82ce0300, - 0x3191ccda, + 0xce5f0300, + 0x00e78485, + 0xe78385ce, + 0x8585ce00, + 0x82ce00e7, + 0x6b91ccd6, + 0x82ce00ed, + 0x8491ccda, + 0x82ce00ed, + 0x039cccdc, + 0x82ce00ed, + 0xe19bccde, + 0x82ce00ed, + 0x6492cce2, + 0x82ce00ed, + 0x6295cce4, + 0x82ce00ed, + 0xc3a2cce6, 0x82ce00ed, - 0x5d91cce2, + 0x7696cce8, 0x82ce00ed, - 0x5b94cce4, + 0x6291ccea, 0x82ce00ed, - 0x699bcce6, + 0xce00edec, + 0x00edee82, + 0xedf082ce, + 0xf282ce00, 0x82ce00ed, - 0x2891cce8, + 0xa494ccf4, 0x82ce00ed, - 0xce00edea, - 0x00edec82, - 0xedee82ce, - 0xf082ce00, + 0x96a1ccf6, 0x82ce00ed, - 0xce00edf2, - 0x93ccf482, - 0xce00ed9d, - 0x9accf682, - 0xce00ed3c, - 0x91ccf882, - 0xce00edb5, - 0x91ccfa82, - 0xbd00edf8, - 0x82ce349b, - 0x6698cc9a, - 0xce0e00ed, + 0xbc92ccf8, + 0x82ce00ed, + 0xff92ccfa, + 0xa2bd00ed, + 0x9a82ce8e, + 0xed609fcc, + 0xce180e00, 0x01c6ed84, - 0x02c600e7, - 0x9dcc00e7, - 0x659dfd44, - 0xcfa09dfd, - 0x00defd20, - 0x3c02de3c, - 0xde3c04de, - 0x069f3c06, - 0x3806df38, - 0xdf3804df, - 0x00df3802, - 0x3c00de3b, - 0xde3c02de, - 0x06de3c04, - 0x38069f3c, - 0xdf3806df, - 0x02df3804, - 0x3b00df38, + 0xce00e718, + 0x00cc00bf, + 0xc600ed33, + 0x00e71802, + 0xfda9a4cc, + 0xa5fdcaa4, + 0xfd20cf05, + 0xde3c00de, + 0x04de3c02, + 0x3c06de3c, + 0xdf38069f, + 0x04df3806, + 0x3802df38, + 0xde3b00df, + 0x02de3c00, + 0x3c04de3c, 0x9f3c06de, 0x06df3806, - 0x3c06de39, - 0x7ece069f, - 0xe7dfc601, - 0x647ece00, - 0xed02ffcc, - 0x627ece00, - 0xed0086cc, - 0x017ece00, - 0x20c400e6, - 0x95bdf727, - 0x06df3801, - 0x3c06de39, - 0x85ce069f, - 0xce00e607, - 0x8c4f0000, + 0x3804df38, + 0xdf3802df, + 0x06de3b00, + 0x38069f3c, + 0xde3906df, + 0x069f3c06, + 0xe60086ce, + 0x220bc100, + 0xce408d07, + 0x00adc8cc, + 0x3906df38, + 0x9f3c06de, + 0x0086ce06, + 0x0bc100e6, + 0x278d2522, + 0xc6017ece, + 0xce00e7df, + 0xffcc647e, + 0xce00ed02, + 0x86cc627e, + 0xce00ed00, + 0x00e6017e, + 0xf72720c4, + 0x38259cbd, + 0xde3906df, + 0x069f3c06, + 0xde3c08de, + 0x86ce3c0a, + 0xdd5f4f08, + 0xdf08dd0a, + 0x1d02de02, + 0xdf183f00, + 0x02de1804, + 0x00c38f18, + 0xdc8f1807, + 0xc308de0a, + 0x01240100, + 0xdf0add08, + 0x02df1808, + 0x8c04de18, 0x06260000, - 0x0100831a, - 0x008c2d27, - 0x2b362e00, - 0x00831a34, - 0x8c0b2201, - 0x29260000, - 0x0f2700dd, - 0x008c2320, - 0x1a1e2600, - 0x27020083, - 0xcc162012, - 0x95bd0885, - 0xcc0e2029, - 0x95bd3085, - 0xcc062029, - 0x95bd5885, - 0x06df3829, - 0x3c06de39, - 0x08de069f, - 0x3c0ade3c, - 0x1daa7fce, - 0x7fce0100, - 0x10001c8f, - 0x6b8d1bc6, - 0x36377f84, - 0x92bd1bc6, - 0x8d04c6f7, - 0x8f7fce5e, - 0xce10001d, - 0x001daa7f, - 0x01001c01, - 0xdf383131, + 0x0a00831a, + 0x04dfcf23, + 0x4f0486ce, + 0xdd0add5f, + 0xde02df08, + 0xdf02de04, + 0x00de1800, + 0x04df0818, + 0x0700c38f, + 0x00ec188f, + 0x02dff084, + 0x831a04de, + 0x1426fe00, + 0x18fe00cc, + 0x001d00ed, + 0xc400e680, + 0x2620c1f0, + 0x0e001d03, + 0x08de0adc, + 0x240100c3, + 0x0add0801, + 0x062608df, + 0x0a00831a, + 0xdf38b723, 0x08df380a, 0x3906df38, 0x9f3c06de, + 0x0785ce06, + 0x00ce00e6, + 0x008c4f00, + 0x1a062600, + 0x27010083, + 0x00008c2d, + 0x342b362e, + 0x0100831a, + 0x008c0b22, + 0xdd292600, + 0x200f2700, + 0x00008c23, + 0x831a1e26, + 0x12270200, + 0x85cc1620, + 0x4d9cbd08, + 0x85cc0e20, + 0x4d9cbd30, + 0x85cc0620, + 0x4d9cbd58, + 0x3906df38, + 0x9f3c06de, 0x3c08de06, 0xce3c0ade, 0x001daa7f, 0x8f7fce01, 0xc610001c, - 0x8a288d1b, - 0xc6363780, - 0xf792bd1b, - 0x1b8d04c6, + 0x846b8d1b, + 0xc636377f, + 0xfe93bd1b, + 0x5e8d04c6, 0x1d8f7fce, 0x7fce1000, 0x01001daa, @@ -194,144 +242,168 @@ UINT32 DataBlock0[] = { 0xde3906df, 0x069f3c06, 0xde3c08de, - 0x0cde3c0a, - 0x3c0ede3c, - 0x00cc0dd7, - 0x4f36374d, + 0x7fce3c0a, + 0x01001daa, + 0x1c8f7fce, + 0x1bc61000, + 0x808a288d, + 0x1bc63637, + 0xc6fe93bd, + 0xce1b8d04, + 0x001d8f7f, + 0xaa7fce10, + 0x1c01001d, + 0x31310100, + 0x380adf38, + 0xdf3808df, + 0x06de3906, + 0xde069f3c, + 0x0ade3c08, + 0x3c0cde3c, + 0xd73c0ede, + 0x4d00cc0d, + 0x5f4f3637, + 0x00cc3637, + 0x0002ce60, + 0xcc5a9ebd, + 0x02ce6400, + 0x389ebd00, + 0x00cc08df, + 0x4f3637cd, 0xcc36375f, 0x02ce6000, - 0x3697bd00, + 0x5a9ebd00, + 0x0dd68f18, + 0xdf188f18, + 0x0e007f0e, + 0x0cdd0edc, + 0x7f0f007f, + 0x38180e00, + 0x38183818, + 0x08dc3818, + 0x08260185, + 0x8a8f0cde, + 0x0cdf8f01, + 0x36370edc, + 0x36370cdc, 0xce6400cc, - 0x97bd0002, - 0xcc08df14, - 0x3637cd00, - 0x36375f4f, - 0xce6000cc, - 0x97bd0002, - 0xd68f1836, - 0x188f180d, - 0x007f0edf, - 0xdd0edc0e, - 0x0f007f0c, - 0x180e007f, + 0x9ebd0002, + 0x4e00cc5a, + 0x5f4f3637, + 0x00cc3637, + 0x0002ce60, + 0xcc5a9ebd, + 0x02ce6400, + 0x389ebd00, + 0x38183818, + 0x38183818, + 0xdf183818, + 0x1838180e, + 0x38180cdf, + 0x180adf18, + 0x08df1838, + 0xdf183818, + 0x06de3906, + 0xde069f3c, + 0x0ade3c08, + 0x3c0cde3c, + 0xd73c0ede, + 0x4d00cc0d, + 0x5f4f3637, + 0x00cc3637, + 0x0002ce60, + 0xcc5a9ebd, + 0x02ce6400, + 0x389ebd00, + 0x00cc08df, + 0x4f3637cd, + 0xcc36375f, + 0x02ce6000, + 0x5a9ebd00, + 0x0dd68f18, + 0xdf188f18, + 0x0e007f0e, + 0x7f0d007f, + 0x5f4f0c00, + 0x8f0002ce, + 0x0fda0e9a, + 0xdf0edd8f, + 0xec06de0c, + 0xda0e9a05, + 0xdd0cde0f, + 0x1838180e, 0x18381838, - 0xdc381838, - 0x26018508, - 0x8f0cde08, + 0x8508dc38, + 0x8f062601, 0xdf8f018a, 0x370edc0c, 0x370cdc36, 0x6400cc36, 0xbd0002ce, - 0x00cc3697, - 0x4f36374e, - 0xcc36375f, - 0x02ce6000, - 0x3697bd00, - 0xce6400cc, - 0x97bd0002, - 0x18381814, - 0x18381838, - 0x18381838, - 0x38180edf, - 0x180cdf18, - 0x0adf1838, - 0xdf183818, - 0x18381808, - 0xde3906df, - 0x069f3c06, - 0xde3c08de, - 0x0cde3c0a, - 0x3c0ede3c, - 0x00cc0dd7, - 0x4f36374d, - 0xcc36375f, - 0x02ce6000, - 0x3697bd00, - 0xce6400cc, - 0x97bd0002, - 0xcc08df14, - 0x3637cd00, - 0x36375f4f, - 0xce6000cc, - 0x97bd0002, - 0xd68f1836, - 0x188f180d, - 0x007f0edf, - 0x0d007f0e, - 0x4f0c007f, - 0x0002ce5f, - 0xda0e9a8f, - 0x0edd8f0f, - 0x06de0cdf, - 0x0e9a05ec, - 0x0cde0fda, - 0x38180edd, - 0x38183818, - 0x08dc3818, - 0x06260185, - 0x8f018a8f, - 0x0edc0cdf, - 0x0cdc3637, - 0x00cc3637, - 0x0002ce64, - 0x383697bd, - 0x0edf3838, - 0x380cdf38, - 0xdf380adf, - 0x06df3808, - 0x3c06de39, - 0x08de069f, - 0x3c0ade3c, - 0xde3c0cde, - 0x85ce3c0e, - 0xdd02ec90, - 0xdd00ec0e, - 0x5f0edc0c, - 0x04caf084, - 0x0edd0e8a, - 0x1daa7fce, - 0x0cde0100, - 0xdd7196bd, - 0xce08df0a, - 0x00e69785, - 0x0adc0626, - 0x0420118a, - 0xef840adc, - 0x36370add, - 0x363708dc, - 0x0cde0edc, - 0xcebc96bd, - 0x001caa7f, - 0x38383801, - 0xdf380edf, - 0x0adf380c, - 0x3808df38, - 0xde3906df, - 0x069f3c06, - 0x80ce8f18, - 0x2600e6ff, - 0xe704c60c, - 0x207ece00, - 0x2001001c, - 0x04001c03, - 0xc6007ece, - 0xce00e7ef, - 0x00ec217e, - 0xd300df18, - 0x277ece00, - 0x7ece00ed, - 0xc400e600, - 0xcef72710, - 0x001dff80, - 0x2600e604, - 0x207ece06, - 0x3801001d, - 0xde3906df, - 0x069f3c06, - 0xe68385ce, - 0x2701c400, - 0xb885ce74, + 0x38385a9e, + 0x380edf38, + 0xdf380cdf, + 0x08df380a, + 0x3906df38, + 0x9f3c06de, + 0x3c08de06, + 0xde3c0ade, + 0x0ede3c0c, + 0x9085ce3c, + 0x0edd02ec, + 0x0cdd00ec, + 0x845f0edc, + 0x8a04caf0, + 0xce0edd0e, + 0x001daa7f, + 0xbd0cde01, + 0x0add959d, + 0x85ce08df, + 0x2600e697, + 0x8a0adc06, + 0xdc042011, + 0xddef840a, + 0xdc36370a, + 0xdc363708, + 0xbd0cde0e, + 0x7fcee09d, + 0x01001caa, + 0xdf383838, + 0x0cdf380e, + 0x380adf38, + 0xdf3808df, + 0x06de3906, + 0x18069f3c, + 0xff80ce8f, + 0x0c2600e6, + 0x00e704c6, + 0x1c207ece, + 0x03200100, + 0xce04001c, + 0xefc6007e, + 0x7ece00e7, + 0x1800ec21, + 0x00d300df, + 0xed277ece, + 0x007ece00, + 0x10c400e6, + 0x80cef727, + 0x04001dff, + 0x062600e6, + 0x1d207ece, + 0xdf380100, + 0x06de3906, + 0xde069f3c, + 0x85ce3c08, + 0xce00e683, + 0x8f188485, + 0x09d700e6, + 0x09d18f18, + 0x967e0326, + 0x8385ce65, + 0x01c400e6, + 0x967e0326, + 0xb885ce3b, 0x02ed5f4f, 0x85ce00ed, 0xed02edbc, @@ -342,33 +414,417 @@ UINT32 DataBlock0[] = { 0x02edc885, 0x85ce00ed, 0xed02edcc, - 0x8285ce00, - 0x08c400e6, - 0x97bd0326, - 0xff80ceaa, - 0xce08001c, - 0x00e68285, - 0x7ecef0c4, - 0xe701ca20, - 0x217ece00, - 0xce00ee1a, - 0x00ec8085, - 0x8f1800dd, - 0x8f1800d3, - 0x1a297ece, - 0x7ece00ef, - 0xe7dfc600, - 0x027ece00, - 0x2020001c, - 0xff80ce20, + 0x85ce1800, + 0x00e61882, + 0x032608c4, + 0xcece9ebd, + 0x02cc0883, + 0xce00ed00, + 0x5f4f1483, + 0x00ed02ed, + 0xed1083ce, + 0x1800ed02, + 0x188385ce, + 0xce5400e6, + 0x00e71283, + 0xe68585ce, + 0x5d02df00, + 0x80ce3a26, + 0x08001cff, + 0xe68285ce, + 0xcef0c400, + 0x01ca207e, + 0x7ece00e7, + 0x00ee1a21, + 0xec8085ce, + 0x1800dd00, + 0x1800d38f, + 0x297ece8f, + 0xce00ef1a, + 0xdfc6007e, + 0x7ece00e7, + 0x20001c02, + 0x02de04df, + 0xde01001c, + 0xce2a2004, + 0x001d8585, + 0x2600e601, + 0xff80ce1d, 0xe608001d, 0xce062600, 0x001d207e, 0x007ece01, 0x00e7dfc6, 0x1d027ece, - 0x99bd2000, - 0x06df38c1, + 0xa1bd2000, + 0x8385ce1b, + 0x85ce00e6, + 0x3800e784, + 0xdf3808df, + 0x06de3906, + 0x8d069f3c, + 0x8585ce1c, + 0x032600e6, + 0xce7d97bd, + 0x001c8585, + 0x9a82ce02, + 0xedcd97cc, + 0x06df3800, + 0x3c06de39, + 0x08de069f, + 0x3c0ade3c, + 0xec4485ce, + 0x10c44f00, + 0x02ec2027, + 0x00ec0add, + 0x0adc08dd, + 0x4f8f08de, + 0xbd8f0fc4, + 0xce1897a4, + 0xed18d085, + 0x00efcd02, + 0x02ec1c20, + 0x00ec0add, + 0x0adc08dd, + 0x4f8f08de, + 0xdf8f0fc4, + 0xd085ce08, + 0x08dc02ed, + 0x85ce00ed, + 0x4f00ec48, + 0x202710c4, + 0x0add02ec, + 0x08dd00ec, + 0x08de0adc, + 0x0fc44f8f, + 0x97a4bd8f, + 0xd485ce18, + 0xcd02ed18, + 0x1c2000ef, + 0x0add02ec, + 0x08dd00ec, + 0x08de0adc, + 0x0fc44f8f, + 0xce08df8f, + 0x02edd485, + 0x00ed08dc, + 0xcc5884ce, + 0x00ed0091, + 0xcc5a84ce, + 0x00ed0cc4, + 0xad0490fe, + 0x85ce1800, + 0x5e84ced8, + 0x0f8400ec, + 0x1800ed18, + 0x85ce00ec, + 0x4f00edda, + 0x1285ce5f, + 0x85ce00ed, + 0xce00ed10, + 0x00e7977f, + 0xc60b85ce, + 0x3800e701, + 0xdf380adf, + 0x06df3808, + 0x3c06de39, + 0xce069f34, + 0x001cff80, + 0x0e85ce08, + 0x06de00ec, + 0x011d01e7, + 0x217ece0f, + 0xce00ee1a, + 0x00ec0c85, + 0x8f1800dd, + 0x8f1800d3, + 0x1a297ece, + 0x7ece00ef, + 0x06de1820, + 0xca01e618, + 0xce00e701, + 0xdfc6007e, + 0x7ece00e7, + 0x20001c02, + 0x06df3831, + 0x3c06de39, + 0x069f3c3c, + 0xde3c08de, + 0x0cde3c0a, + 0x3c0ede3c, + 0xce779abd, + 0x00e6de85, + 0x997e0327, + 0x5884ce21, + 0xed0090cc, + 0x5a84ce00, + 0x50c7ce18, + 0xfe00ef1a, + 0x00ad0490, + 0xec5c84ce, + 0x10c44f00, + 0x02ec2027, + 0x00ec0add, + 0x0adc08dd, + 0x4f8f08de, + 0xbd8f0fc4, + 0xce1897a4, + 0xed18e085, + 0x00efcd02, + 0x02ec1c20, + 0x00ec0add, + 0x0adc08dd, + 0x4f8f08de, + 0xdf8f0fc4, + 0xe085ce08, + 0x08dc02ed, + 0x85ce00ed, + 0xc400e60b, + 0x18452601, + 0x18977fce, + 0x01c400e6, + 0x85ce3a26, + 0xdd02ece0, + 0xdd00ec0e, + 0xd085ce0c, + 0x0add02ec, + 0x08dd00ec, + 0x089c0cde, + 0x072e1e2d, + 0x931a0edc, + 0xc615230a, + 0x00e71801, + 0x1c1285ce, + 0x85ce0101, + 0x6f016f10, + 0x21997e00, + 0x4f06de18, + 0x03ed185f, + 0xce01ed18, + 0x00e60b85, + 0x262601c4, + 0xece085ce, + 0xec0edd02, + 0xce0cdd00, + 0x02ecd485, + 0x00ec0add, + 0xde1808dd, + 0x089c180c, + 0x142e082d, + 0x0a9c0ede, + 0xde180e24, + 0x0100cc06, + 0x4f03ed18, + 0x01ed185f, + 0x0add5f4f, + 0x7fce08dd, + 0xc100e684, + 0xcc072607, + 0x0add0100, + 0xde185f4f, + 0x03ec1806, + 0x9401eecd, + 0x8f0bd40a, + 0x09d40894, + 0x00008c8f, + 0x00dd0426, + 0x7fce0f27, + 0xe702c697, + 0x1285ce00, + 0x011d006f, + 0x847fce01, + 0x07c100e6, + 0x85ce1226, + 0x02011c12, + 0xec1085ce, + 0x0100c300, + 0x082000ed, + 0x6f1285ce, + 0x02011d00, + 0xe60b85ce, + 0x2602c400, + 0x239a7e03, + 0xe6847fce, + 0x2607c100, + 0x85ce1860, + 0x00ec1812, + 0x2604c44f, + 0x0090cc54, + 0xed5884ce, + 0x68c3ce00, + 0x5a84ce18, + 0xfe00efcd, + 0x00ad0490, + 0x5c84ce18, + 0xdd02ec18, + 0x00ec180a, + 0x0adc08dd, + 0xed1820ca, + 0x1808dc02, + 0x80ce00ed, + 0x84ce1800, + 0x00efcd58, + 0x1868c3ce, + 0xcd5a84ce, + 0x90fe00ef, + 0x1800ad06, + 0x181285ce, + 0x2004011c, + 0x847fce6a, + 0x07c100e6, + 0x85ce6127, + 0x4f00ec12, + 0x572704c4, + 0x180090ce, + 0xcd5884ce, + 0xc3ce00ef, + 0x84ce1868, + 0x00efcd5a, + 0xad0490fe, + 0x84ce1800, + 0x02ec185c, + 0xec180add, + 0xdc08dd00, + 0x18dfc40a, + 0x08dc02ed, + 0xce00ed18, + 0xce180080, + 0xefcd5884, + 0x68c3ce00, + 0x5a84ce18, + 0xfe00efcd, + 0x00ad0690, + 0x1285ce18, + 0x18006f18, + 0xce04011d, + 0x00e68385, + 0x188485ce, + 0xd700e68f, + 0xd18f1809, + 0xbd032709, + 0x85ce6295, + 0xc400e683, + 0xbd032701, + 0x7ece609f, + 0x00ee1a21, + 0xec0c85ce, + 0x1800dd00, + 0x1800d38f, + 0x297ece8f, + 0xce00ef1a, + 0x001d007e, + 0x0edf3820, + 0x380cdf38, + 0xdf380adf, + 0x38383808, + 0xde3906df, + 0x069f3c06, + 0xce3c08de, + 0x01c6687e, + 0xce1800e7, + 0xfecc647e, + 0x00ed1870, + 0xcc667ece, + 0x00ed0200, + 0xce00e618, + 0x00e6677e, + 0xf72701c4, + 0xe6637ece, + 0x5404c400, + 0xdc85ce54, + 0xce1800e7, + 0xfecc647e, + 0x00ed1880, + 0xcc667ece, + 0x00ed0200, + 0xce00e618, + 0x00e6677e, + 0xf72701c4, + 0xe6637ece, + 0x5404c400, + 0xdd85ce54, + 0xce1800e7, + 0xfecc647e, + 0x00ed1860, + 0xcc667ece, + 0x00ed0200, + 0xce00e618, + 0x00e6677e, + 0xf72701c4, + 0xe6637ece, + 0x5404c400, + 0xde85ce54, + 0xce1800e7, + 0x85cedf85, + 0xce00e6dc, + 0x04dddd85, + 0x09d700e6, + 0x09d404dc, + 0x1800e718, + 0xce1804df, + 0x85ce0088, + 0xce00ecd8, + 0x00ee4285, + 0x00d300df, + 0x1800ed18, + 0xde1802df, + 0x00e61804, + 0x052601c1, + 0x202285ce, + 0x847fce1d, + 0x07c100e6, + 0x85ce0526, + 0xe60f201e, + 0x0000ce00, + 0x598f054f, + 0x85c38f49, + 0x00ec8f14, + 0x08dd0f84, + 0x00ec02de, + 0x00ed0893, + 0xda85ce18, + 0x1804df18, + 0xcd0088ce, + 0xdf1800ee, + 0x04de1802, + 0xdd00ec18, + 0x27009c00, + 0xec02de45, + 0x00ed1800, + 0xce0091cc, + 0x00ed5884, + 0x180cc4ce, + 0xcd5a84ce, + 0x90fe00ef, + 0xce00ad04, + 0x00ec0088, + 0xed5e84ce, + 0x0081cc00, + 0xed5884ce, + 0x0cc4ce00, + 0x1804df18, + 0xcd5a84ce, + 0xde1800ef, + 0x0690fe04, + 0xdf3800ad, + 0x06df3808, + 0x3c06de39, + 0x84ce069f, + 0xc400ecf2, + 0x7e831af0, + 0xec072660, + 0x5000c300, + 0xcdce00ed, + 0x3800ad83, + 0xde3906df, + 0x069f3c06, + 0xecfc84ce, + 0x1af0c400, + 0x2600fe83, + 0xc300ec07, + 0x00ed5000, + 0xad29cece, + 0x06df3800, 0x3c08de39, 0xb65086ce, 0x19270086, @@ -510,7 +966,7 @@ UINT32 DataBlock0[] = { 0x1803a718, 0xfd8602e7, 0x7e04a718, - 0xde188b96, + 0xde18af9d, 0x9f3c1806, 0x7fce1806, 0x01a71880, @@ -520,7 +976,7 @@ UINT32 DataBlock0[] = { 0x03a718fc, 0x8602e718, 0x04a718fd, - 0xeddb967e, + 0xedff9d7e, 0x8407a602, 0x39fa2701, 0x018407a6, @@ -541,75 +997,85 @@ UINT32 DataBlock0[] = { 0xecef2e4a, 0xfecc3902, 0xfc84fd00, - 0xfdf370cc, + 0xfd4470cc, 0x00ccfe84, 0xfa84fd03, - 0x8de0d6bd, - 0xa085f775, + 0x8d29cebd, + 0xa085f75b, 0x8fa185b7, 0x86a285b7, - 0xff84b7f6, - 0x8de0d6bd, - 0xa385f761, + 0xff84b747, + 0x8d29cebd, + 0xa385f747, 0x8fa685b7, 0x86a785b7, - 0xff84b7f9, - 0x8de0d6bd, - 0xae85fd4d, + 0xff84b74a, + 0x8d29cebd, + 0xae85fd33, 0xad85b78f, - 0x84b7fc86, - 0xe0d6bdff, - 0x85fd3c8d, + 0x84b74d86, + 0x29cebdff, + 0x85fd228d, 0x85b78faa, - 0xb7ff86a9, - 0xd6bdff84, - 0xf72b8de0, + 0xb75086a9, + 0xcebdff84, + 0xf7118d29, 0x85b7a485, 0x85b78fa5, - 0x0a71cca8, - 0xbdfe84fd, - 0x85cee0d6, - 0x02ee1a00, - 0x185401e6, - 0x1856468f, - 0x8f18548f, - 0x84fd5646, - 0x08de39be, - 0x0085ce3c, - 0x03a600e6, - 0x01e608dd, - 0x007902a6, - 0x79495909, - 0x00790800, - 0x79495909, - 0x00790800, - 0x79495909, - 0x08de0800, - 0xdf183818, - 0x08de3908, - 0x0090cc3c, - 0xcc5884fd, - 0x84fde4c6, - 0xc3e4bd5a, - 0xb60000ce, - 0xc4165f84, - 0x04163a01, - 0x3a01c404, - 0xc4040416, - 0x04163a01, - 0x3a01c404, - 0x04cb508f, - 0xce4f08d7, - 0x9abdb885, - 0x4f08d60a, + 0x0000cca8, + 0x39be84fd, + 0xce3c08de, + 0x03e60085, + 0x08dd02a6, + 0x01a600e6, + 0x76090076, + 0x56460800, + 0x381808de, + 0x3908df18, + 0xde3c08de, + 0x7ece3c0a, + 0xa7038660, + 0x60fecc08, + 0x00cc04ed, + 0xa606ed02, + 0x8407a604, + 0x4ffa2701, + 0x03a60b97, + 0x0a970184, + 0xa62e274d, + 0x97048403, + 0x25274d0a, + 0xec1083ce, + 0x110f2702, + 0x97048407, + 0x04274d0b, + 0x0220036f, + 0x83f6036c, + 0x1a08d708, + 0x081806ee, + 0x2006ef1a, + 0x1083ce2d, + 0x90cc036f, + 0x5884fd00, + 0xfde4c6cc, + 0xd6bd5a84, + 0x0000ce99, + 0x165f84b6, + 0x163a01c4, + 0x01c40404, + 0xcb508f3a, + 0xf708d702, + 0xce4f0883, + 0xa1bdb885, + 0x4f08d664, 0xbdc085ce, - 0x85f60a9a, + 0x85f664a1, 0x1809d7a6, 0xbdb885ce, - 0x85f6ee99, + 0x85f648a1, 0x1809d7a7, 0xbdc085ce, - 0x8086ee99, + 0x808648a1, 0x85b60897, 0x27048482, 0x607ece5b, @@ -621,346 +1087,352 @@ UINT32 DataBlock0[] = { 0x03a6fa27, 0x44440484, 0xce5f0188, - 0x9abdc885, - 0xa585f60a, + 0xa1bdc885, + 0xa585f664, 0xce1809d7, - 0x99bdc885, - 0xcc85ceee, + 0xa1bdc885, + 0xcc85ce48, 0x0000ce18, 0x142600ec, 0x102602a6, 0x85b103a6, - 0x18092ca4, + 0x180924a4, 0xb6be84fe, 0x0897a885, 0xab7fff18, 0xad7fb74f, 0xf6ac85ce, - 0xfe18a085, - 0x2026bc85, + 0xfe18a285, + 0x1226bc85, 0x26be85b6, - 0xbf85b61b, + 0xbf85b60d, 0xa1a385f6, - 0xf6112d03, - 0x02a1a285, - 0x85f60a2d, - 0x2d01a1a1, - 0xa085f603, - 0x85ce09d7, - 0xa085f6a8, - 0xc485fe18, - 0x85b61d26, - 0xb61826c6, - 0x01a1c785, - 0x85f6112e, - 0x2e02a1a1, - 0xa285f60a, - 0x032e03a1, + 0xf6032503, + 0x09d7a285, + 0xf6a885ce, + 0xfe18a285, + 0x0f26c485, + 0x26c685b6, + 0xc785b60a, + 0x032203a1, 0xd1a385f6, - 0xd7022e09, + 0xd7022209, 0x4f08d609, 0xd68f1805, - 0xeabd4f09, - 0xcc09d740, + 0xdcbd4f09, + 0x9609d706, + 0xcc1c260a, 0x84fd0091, 0x0cc4cc58, 0xbd5a84fd, - 0x09d6c3e4, + 0x09d699d6, 0xc65d84f7, 0x5884f781, - 0xfc92e4bd, - 0x7ef38085, - 0x297efd21, - 0x7eb7df86, - 0x08df3800, - 0x0091cc39, - 0xcc5884fd, - 0x84fd0cc4, - 0xc3e4bd5a, - 0xf7a085f6, - 0x81c65d84, - 0xbd5884f7, - 0x85b692e4, - 0x27048482, - 0xfd4f5f08, - 0x7fb7ab7f, - 0xec1839ad, - 0x02eecd00, - 0x2709007d, - 0x468f040a, - 0x007a8f56, - 0x18f62609, - 0xefcd04ed, - 0x58583906, - 0x02e35858, - 0x00ec02ed, - 0x008900c9, - 0x04ec00ed, - 0x8f184353, - 0x435306ec, - 0x180100c3, - 0x8900c98f, - 0xe38f1800, - 0x1802ed02, - 0xa901e98f, - 0x3900ed00, - 0xde3c06de, - 0x069f3c08, - 0x1daa7fce, - 0x7fce0100, - 0x10001c8f, + 0xce68d6bd, + 0x04ec1083, + 0xed0100c3, + 0x0000c304, + 0x8f180a26, + 0x00ed06ec, + 0x06ed8f18, + 0x848585b6, + 0x96112602, + 0x85f35f0b, + 0x217ef380, + 0x86297efd, + 0x007eb7df, + 0x380adf38, + 0xcc3908df, + 0x84fd0091, + 0x0cc4cc58, + 0xbd5a84fd, + 0x85f699d6, + 0x5d84f7a0, + 0x84f781c6, + 0x68d6bd58, + 0x848285b6, + 0x5f082704, + 0xab7ffd4f, + 0x39ad7fb7, + 0xcd00ec18, + 0x007d02ee, + 0x040a2709, + 0x8f56468f, + 0x2609007a, + 0x04ed18f6, + 0x3906efcd, + 0x58585858, + 0x02ed02e3, + 0x00c900ec, + 0x00ed0089, + 0x435304ec, + 0x06ec8f18, + 0x00c34353, + 0xc98f1801, + 0x18008900, + 0xed02e38f, + 0xe98f1802, + 0xed00a901, + 0x06de3900, + 0x3c08de3c, + 0x7fce069f, + 0x01001daa, + 0x1c8f7fce, + 0x0ccc1000, + 0x0000ced6, + 0xd7499dbd, + 0x37c8c608, + 0xd60ccc34, + 0xbd0000ce, + 0x0cccf19c, + 0x0000ced7, + 0xca499dbd, + 0xcc343720, + 0x00ced70c, + 0xf19cbd00, + 0x3437d8c6, 0xced60ccc, - 0x96bd0000, - 0xc608d725, - 0xcc3437c8, - 0x00ced60c, - 0xcd95bd00, - 0xced70ccc, - 0x96bd0000, - 0x3720ca25, + 0x9cbd0000, + 0x371fc6f1, 0xd70ccc34, 0xbd0000ce, - 0xd8c6cd95, + 0xd9c6f19c, 0x0ccc3437, 0x0000ced6, - 0xc6cd95bd, - 0xcc34371f, + 0xccf19cbd, 0x00ced70c, - 0xcd95bd00, - 0x3437d9c6, - 0xced60ccc, - 0x95bd0000, - 0xd70ccccd, + 0x499dbd00, + 0x00c38f30, + 0xc4358f0a, + 0x8d022620, + 0x3708d644, + 0xd60ccc34, 0xbd0000ce, - 0x8f302596, - 0x8f0a00c3, - 0x2620c435, - 0xd6448d02, - 0xcc343708, - 0x00ced60c, - 0xcd95bd00, - 0x00a0cc38, - 0xbd0002ce, - 0x20ca2596, - 0x022722c1, - 0xa0cc258d, - 0x0002ce01, - 0xc12596bd, - 0x8d022710, - 0x8f7fce16, - 0xce10001d, - 0x001daa7f, - 0x01001c01, - 0x3808df38, - 0xce3906df, - 0x0386607e, - 0xffcc08a7, - 0xcc04ed30, - 0x06ede701, - 0x00ed5f4f, - 0x02ed7fc6, - 0x018407a6, - 0x01ccfa27, - 0x5f06ede9, - 0xed00ed4f, - 0x8407a602, - 0x01fa2701, - 0x39fd20cf, - 0xcc607ece, - 0x04ed30ff, - 0xed3d26cc, + 0xcc38f19c, + 0x02ce00a0, + 0x499dbd00, + 0x22c120ca, + 0x258d0227, + 0xce01a0cc, + 0x9dbd0002, + 0x2710c149, + 0xce168d02, + 0x001d8f7f, + 0xaa7fce10, + 0x1c01001d, + 0xdf380100, + 0x06df3808, + 0x607ece39, + 0x08a70386, + 0xed30ffcc, + 0xe701cc04, + 0x5f4f06ed, + 0x7fc600ed, + 0x07a602ed, + 0xfa270184, + 0xede901cc, + 0xed4f5f06, + 0xa602ed00, + 0x27018407, + 0x20cf01fa, + 0x7ece39fd, + 0x30ffcc60, + 0x26cc04ed, + 0xcc06ed3d, + 0x00edfe00, + 0x839ebd5f, + 0xede20fcc, 0xfe00cc06, 0xbd5f00ed, - 0x0fcc5f97, - 0xcc06ede2, - 0x00edfe00, - 0x5f97bd5f, - 0xed5422cc, - 0xfcffcc06, - 0xfccc00ed, - 0x5f97bd00, - 0x3c08de39, - 0xde3c0ade, - 0x0ede3c0c, - 0xb7df863c, - 0x7ece017e, - 0x02ffcc60, - 0x9dcc04ed, - 0xb602ed64, - 0x2084017e, - 0x01ccf927, - 0xcc08dd01, - 0x0add1100, - 0xdd0000cc, - 0x0f00cc0c, - 0x9cbd0edd, - 0x3001cca9, - 0x80cc08dd, - 0xcc0add62, - 0x0cddffff, - 0xddfff7cc, - 0xdb9cbd0e, - 0xdd0200cc, - 0xffffcc0a, - 0xffcc0cdd, - 0xbd0eddfb, - 0x80ccdb9c, - 0xcc0add63, - 0x0cdd0101, - 0xdd0080cc, - 0xa99cbd0e, + 0x22cc839e, + 0xcc06ed54, + 0x00edfcff, + 0xbd00fccc, + 0xde39839e, + 0x0ade3c08, + 0x3c0cde3c, + 0x863c0ede, + 0x017eb7df, + 0xcc607ece, + 0x04ed02ff, + 0xedc9a4cc, + 0x017eb602, + 0xf9272084, + 0xdd0101cc, + 0x1100cc08, + 0x00cc0add, + 0xcc0cdd00, + 0x0edd0f00, + 0xcc03a4bd, + 0x08dd3001, 0xdd6280cc, + 0xffffcc0a, + 0xf7cc0cdd, + 0xbd0eddff, + 0x00cc35a4, + 0xcc0add02, + 0x0cddffff, + 0xddfbffcc, + 0x35a4bd0e, + 0xdd6380cc, + 0x0101cc0a, + 0x80cc0cdd, + 0xbd0edd00, + 0x80cc03a4, + 0xcc0add62, + 0x0cdd0000, + 0xdd0100cc, + 0x03a4bd0e, + 0xdd6080cc, 0x0000cc0a, 0x00cc0cdd, 0xbd0edd01, - 0x80cca99c, + 0xce1803a4, + 0x7ef60200, + 0x54545420, + 0x939ebd54, + 0xcc1295bd, + 0x08dd1001, + 0xdd1000cc, + 0x0000cc0a, + 0x00cc0cdd, + 0x8d0edd01, + 0x3001cc7e, + 0x80cc08dd, 0xcc0add60, - 0x0cdd0000, - 0xdd0100cc, - 0xa99cbd0e, - 0x0200ce18, - 0x54207ef6, - 0xbd545454, - 0x94bd6f97, - 0x1001cc0b, - 0x00cc08dd, - 0xcc0add10, - 0x0cdd0000, - 0xdd0100cc, - 0xcc7e8d0e, + 0x0cdd0301, + 0xcc67a4bd, 0x08dd3001, - 0xdd6080cc, - 0x0301cc0a, - 0x9dbd0cdd, - 0x3001cc0d, - 0x80cc08dd, - 0xcc0add62, - 0x0cddffff, - 0xddfeffcc, - 0xdb9cbd0e, - 0xdd0000cc, - 0x0008cc0c, - 0x498d0edd, - 0xdd6380cc, - 0xfefecc0a, - 0x7fcc0cdd, - 0x8d0eddff, - 0x2001cc6a, - 0x44cc08dd, - 0xcc0add50, - 0x0cdd0203, - 0x860d9dbd, - 0x017eb7df, - 0xcc607ece, - 0x04ed02ff, - 0xed9f9dcc, - 0x017eb602, - 0xf9272084, - 0x380edf38, - 0xdf380cdf, - 0x08df380a, - 0x607ece39, - 0xed30ffcc, - 0x2800cc04, - 0x08dc06ed, - 0x0adc00ed, - 0xcc5f97bd, - 0x06ed2900, - 0x97bd04a6, - 0x9a00ec68, - 0xed0dda0c, - 0x9a02ec00, - 0xbd0fda0e, - 0xce395f97, + 0xdd6280cc, + 0xffffcc0a, + 0xffcc0cdd, + 0xbd0eddfe, + 0x00cc35a4, + 0xcc0cdd00, + 0x0edd0008, + 0x80cc498d, + 0xcc0add63, + 0x0cddfefe, + 0xddff7fcc, + 0xcc6a8d0e, + 0x08dd2001, + 0xdd5044cc, + 0x0203cc0a, + 0xa4bd0cdd, + 0xb7df8667, + 0x7ece017e, + 0x02ffcc60, + 0xa5cc04ed, + 0xb602ed04, + 0x2084017e, + 0xdf38f927, + 0x0cdf380e, + 0x380adf38, + 0xce3908df, 0xffcc607e, 0xcc04ed30, 0x06ed2800, 0x00ed08dc, - 0x97bd0adc, - 0x2900cc5f, + 0x9ebd0adc, + 0x2900cc83, 0x04a606ed, - 0xec6897bd, - 0xd40c9400, + 0xec8c9ebd, + 0xda0c9a00, 0xec00ed0d, - 0xd40e9402, - 0x5f97bd0f, + 0xda0e9a02, + 0x839ebd0f, 0x607ece39, - 0x607ece18, - 0x3a180dd6, 0xed30ffcc, 0x2800cc04, 0x08dc06ed, 0x0adc00ed, - 0xcc5f97bd, + 0xcc839ebd, 0x06ed2900, - 0x97bd04a6, - 0x00e61868, - 0xf4260cd4, - 0x39064f39, - 0xfc203e0e, - 0x28202001, - 0x00000000, - 0x20202001, - 0x00000000, - 0x24202001, - 0x00000000, - 0x2c202001, - 0x00000000, - 0x28000008, + 0x9ebd04a6, + 0x9400ec8c, + 0xed0dd40c, + 0x9402ec00, + 0xbd0fd40e, + 0xce39839e, + 0xce18607e, + 0x0dd6607e, + 0xffcc3a18, + 0xcc04ed30, + 0x06ed2800, + 0x00ed08dc, + 0x9ebd0adc, + 0x2900cc83, + 0x04a606ed, + 0x188c9ebd, + 0x0cd400e6, + 0x5339f426, + 0x43538f43, + 0x01268f08, + 0x064f3908, + 0x203e0e39, + 0x202001fc, + 0x00000028, + 0x20200100, + 0x00000020, + 0x20200100, + 0x00000024, + 0x20200100, + 0x0000002c, + 0x00000800, + 0xff300028, + 0x2901c004, 0x04ff3000, - 0x002901c0, + 0x002800c0, 0xc004ff30, - 0x30002800, - 0x01c004ff, - 0xff300029, - 0x2800c004, + 0x30002901, + 0x00c004ff, + 0xff300028, + 0x2901c004, 0x04ff3000, - 0x002901c0, + 0x002800c0, 0xc004ff30, - 0x30002800, - 0x01c004ff, - 0xff300029, - 0x0800c004, - 0x00280000, + 0x30002901, + 0x00c004ff, + 0x28000008, + 0x04ff3000, + 0x002909c0, 0xc004ff30, - 0x30002909, + 0x30002809, 0x09c004ff, - 0xff300028, - 0x2909c004, + 0xff300029, + 0x2809c004, 0x04ff3000, - 0x002809c0, + 0x002909c0, 0xc004ff30, - 0x30002909, + 0x30002809, 0x09c004ff, - 0xff300028, - 0x2909c004, - 0x04ff3000, - 0x000001c0 + 0xff300029, + 0x0001c004 }; UINT32 DataBlock1[] = { - 0x3b903b90, - 0x3b903b90, - 0x3b903b90, - 0x3b903b90, - 0x3b903b90, - 0x3b903b90, - 0x3b903b90, - 0x3b903b90, - 0x3b903b90, - 0x3b903b90, - 0x3b903b90, - 0x3b903b90, - 0x96d53b90, - 0x3b90aed5, - 0x04900490, - 0x04900490 + 0x3f903f90, + 0x3f903f90, + 0x3f903f90, + 0x3f903f90, + 0x3f903f90, + 0x3f903f90, + 0x3f903f90, + 0x3f903f90, + 0x3f903f90, + 0x3f903f90, + 0x3f903f90, + 0x3f903f90, + 0x96d53f90, + 0x3f90aed5, + 0x08900890, + 0x08900890 }; SMU_FIRMWARE_BLOCK FmBlockArray[] = { { 0x9000, - 0x377, + 0x550, &DataBlock0[0] }, { @@ -972,7 +1444,7 @@ SMU_FIRMWARE_BLOCK FmBlockArray[] = { SMU_FIRMWARE_HEADER Fm = { { - 0x1, 0x200 + 0x1, 0x601 }, 2, &FmBlockArray[0] diff --git a/src/vendorcode/amd/agesa/f14/Proc/GNB/Nb/Family/NbFamilyServices.h b/src/vendorcode/amd/agesa/f14/Proc/GNB/Nb/Family/NbFamilyServices.h index 808658c3cf..e9083b227e 100644 --- a/src/vendorcode/amd/agesa/f14/Proc/GNB/Nb/Family/NbFamilyServices.h +++ b/src/vendorcode/amd/agesa/f14/Proc/GNB/Nb/Family/NbFamilyServices.h @@ -9,7 +9,7 @@ * @xrefitem bom "File Content Label" "Release Content" * @e project: AGESA * @e sub-project: GNB - * @e \$Revision: 40044 $ @e \$Date: 2010-10-19 06:43:22 +0800 (Tue, 19 Oct 2010) $ + * @e \$Revision: 47490 $ @e \$Date: 2011-02-22 08:34:28 -0700 (Tue, 22 Feb 2011) $ * */ /* @@ -79,6 +79,12 @@ typedef struct { } NB_POWERGATE_CONFIG; VOID +NbFmNbClockGating ( + IN OUT VOID *NbClkGatingCtrl, + IN AMD_CONFIG_PARAMS *StdHeader + ); + +VOID NbFmClumpUnitID ( IN PCI_ADDR NbPciAddress, IN AMD_CONFIG_PARAMS *StdHeader diff --git a/src/vendorcode/amd/agesa/f14/Proc/GNB/Nb/Feature/NbFuseTable.c b/src/vendorcode/amd/agesa/f14/Proc/GNB/Nb/Feature/NbFuseTable.c index d3f3e6c496..ea9afd24e3 100644 --- a/src/vendorcode/amd/agesa/f14/Proc/GNB/Nb/Feature/NbFuseTable.c +++ b/src/vendorcode/amd/agesa/f14/Proc/GNB/Nb/Feature/NbFuseTable.c @@ -9,7 +9,7 @@ * @xrefitem bom "File Content Label" "Release Content" * @e project: AGESA * @e sub-project: GNB - * @e \$Revision: 39275 $ @e \$Date: 2010-10-09 08:22:05 +0800 (Sat, 09 Oct 2010) $ + * @e \$Revision: 48498 $ @e \$Date: 2011-03-09 12:44:53 -0700 (Wed, 09 Mar 2011) $ * */ /* @@ -220,9 +220,18 @@ NbFuseLoadFuseTableFromFcr ( ); for (FieldIndex = 0; FieldIndex < FuseRegisterTableLength; FieldIndex++) { FUSE_REGISTER_ENTRY RegisterEntry; + UINT8 *FuseArrayPtr; + UINT32 FuseArrauValue; RegisterEntry = FuseTable->FuseTable[RegisterIndex].FuseRegisterTable[FieldIndex]; - *((UINT8 *) PpFuseArray + RegisterEntry.FuseOffset) = (UINT8) ((FuseValue >> RegisterEntry.FieldOffset) & - ((1 << RegisterEntry.FieldWidth) - 1)); + FuseArrayPtr = (UINT8*) PpFuseArray + RegisterEntry.FuseOffset; + FuseArrauValue = (FuseValue >> RegisterEntry.FieldOffset) & ((1 << RegisterEntry.FieldWidth) - 1); + if (RegisterEntry.FieldWidth > 16) { + *((UINT32 *) FuseArrayPtr) = FuseArrauValue; + } else if (RegisterEntry.FieldWidth > 8) { + *((UINT16 *) FuseArrayPtr) = (UINT16) FuseArrauValue; + } else { + *((UINT8 *) FuseArrayPtr) = (UINT8) FuseArrauValue; + } } } } @@ -291,6 +300,8 @@ NbFuseAdjustFuseTableToCurrentMainPllVco ( FusedMainPllFreq10KHz = (PpFuseArray->MainPllId + 0x10) * 100 * 100; if (FusedMainPllFreq10KHz != EffectiveMainPllFreq10KHz) { IDS_HDT_CONSOLE (NB_MISC, " WARNING! Adjusting fuse table for reprogrammed VCO\n"); + IDS_HDT_CONSOLE (NB_MISC, " Actual main Freq %d \n", EffectiveMainPllFreq10KHz); + IDS_HDT_CONSOLE (NB_MISC, " Fused main Freq %d \n", FusedMainPllFreq10KHz); for (Index = 0; Index < 5; Index++) { if (PpFuseArray->SclkDpmDid[Index] != 0) { TempVco = GfxLibCalculateClk (PpFuseArray->SclkDpmDid[Index], FusedMainPllFreq10KHz); @@ -378,7 +389,7 @@ NbFuseDebugDump ( (PpFuseArray->DisplclkDid[Index] != 0) ? (GfxLibCalculateClk (PpFuseArray->DisplclkDid[Index], EffectiveMainPllFreq10KHz) / 100) : 0 ); } - for (Index = 0; Index < 5; Index++) { + for (Index = 0; Index < 6; Index++) { IDS_HDT_CONSOLE ( NB_MISC, " SCLK DID[%d] - 0x%02x (%dMHz)\n", @@ -386,6 +397,12 @@ NbFuseDebugDump ( PpFuseArray->SclkDpmDid[Index], (PpFuseArray->SclkDpmDid[Index] != 0) ? (GfxLibCalculateClk (PpFuseArray->SclkDpmDid[Index], EffectiveMainPllFreq10KHz) / 100) : 0 ); + IDS_HDT_CONSOLE ( + NB_MISC, + " SCLK TDP[%d] - 0x%x \n", + Index, + PpFuseArray->SclkDpmTdpLimit[Index] + ); IDS_HDT_CONSOLE (NB_MISC, " SCLK VID[%d] - 0x%02x\n", Index, PpFuseArray->SclkDpmVid[Index]); } for (Index = 0; Index < 6; Index++) { @@ -397,5 +414,14 @@ NbFuseDebugDump ( } IDS_HDT_CONSOLE (NB_MISC, " GEN2 VID - 0x%x\n", PpFuseArray->PcieGen2Vid); IDS_HDT_CONSOLE (NB_MISC, " Main PLL Id - 0x%x\n", PpFuseArray->MainPllId); + IDS_HDT_CONSOLE (NB_MISC, " GpuBoostCap - %x\n", PpFuseArray->GpuBoostCap); + IDS_HDT_CONSOLE (NB_MISC, " SclkDpmBoostMargin - %x\n", PpFuseArray->SclkDpmBoostMargin); + IDS_HDT_CONSOLE (NB_MISC, " SclkDpmThrottleMargin - %x\n", PpFuseArray->SclkDpmThrottleMargin); + IDS_HDT_CONSOLE (NB_MISC, " SclkDpmTdpLimitPG - %x\n", PpFuseArray->SclkDpmTdpLimitPG); + IDS_HDT_CONSOLE ( + NB_MISC, " SclkThermDid - %x(%dMHz)\n", + PpFuseArray->SclkThermDid, + (PpFuseArray->SclkThermDid != 0) ? (GfxLibCalculateClk (PpFuseArray->SclkThermDid, EffectiveMainPllFreq10KHz) / 100) : 0 + ); IDS_HDT_CONSOLE (NB_MISC, "<------------ GNB FUSE END-------------->\n"); } diff --git a/src/vendorcode/amd/agesa/f14/Proc/GNB/Nb/NbInit.c b/src/vendorcode/amd/agesa/f14/Proc/GNB/Nb/NbInit.c index 88ef6bf813..f723480815 100644 --- a/src/vendorcode/amd/agesa/f14/Proc/GNB/Nb/NbInit.c +++ b/src/vendorcode/amd/agesa/f14/Proc/GNB/Nb/NbInit.c @@ -9,7 +9,7 @@ * @xrefitem bom "File Content Label" "Release Content" * @e project: AGESA * @e sub-project: GNB - * @e \$Revision: 41506 $ @e \$Date: 2010-11-05 22:31:30 +0800 (Fri, 05 Nov 2010) $ + * @e \$Revision: 48955 $ @e \$Date: 2011-03-14 18:31:17 -0600 (Mon, 14 Mar 2011) $ * */ /* @@ -56,6 +56,7 @@ #include "GfxLib.h" #include "NbSmuLib.h" #include "NbConfigData.h" +#include "NbInit.h" #include "GnbRegistersON.h" #include "Filecode.h" #define FILECODE PROC_GNB_NB_NBINIT_FILECODE @@ -84,12 +85,12 @@ CONST NB_REGISTER_ENTRY NbPciInitTable [] = { }, { D0F0x4C_ADDRESS, - ~(0x3ull << D0F0x4C_CfgRdTime_OFFSET), + ~(UINT32)(0x3 << D0F0x4C_CfgRdTime_OFFSET), 0x2 << D0F0x4C_CfgRdTime_OFFSET }, { D0F0x84_ADDRESS, - ~(0x1ull << D0F0x84_Ev6Mode_OFFSET), + ~(UINT32)(0x1 << D0F0x84_Ev6Mode_OFFSET), 0x1 << D0F0x84_Ev6Mode_OFFSET } }; @@ -97,7 +98,7 @@ CONST NB_REGISTER_ENTRY NbPciInitTable [] = { CONST NB_REGISTER_ENTRY NbMiscInitTable [] = { { D0F0x64_x46_ADDRESS, - ~(0x3ull << D0F0x64_x46_P2PMode_OFFSET), + ~(UINT32)(0x3 << D0F0x64_x46_P2PMode_OFFSET), 1 << D0F0x64_x46_Msi64bitEn_OFFSET } }; @@ -113,12 +114,12 @@ CONST NB_REGISTER_ENTRY NbOrbInitTable [] = { }, { D0F0x98_x08_ADDRESS, - ~(0xffull << D0F0x98_x08_NpWrrLenC_OFFSET), + ~(UINT32)(0xff << D0F0x98_x08_NpWrrLenC_OFFSET), 1 << D0F0x98_x08_NpWrrLenC_OFFSET }, { D0F0x98_x09_ADDRESS, - ~(0xffull << D0F0x98_x09_PWrrLenD_OFFSET), + ~(UINT32)(0xff << D0F0x98_x09_PWrrLenD_OFFSET), 1 << D0F0x98_x09_PWrrLenD_OFFSET }, { @@ -158,6 +159,8 @@ NbInitOnPowerOn ( { UINTN Index; FCRxFF30_0398_STRUCT FCRxFF30_0398; + UINT32 Value; + // Init NBCONFIG for (Index = 0; Index < (sizeof (NbPciInitTable) / sizeof (NB_REGISTER_ENTRY)); Index++) { GnbLibPciRMW ( @@ -199,6 +202,33 @@ NbInitOnPowerOn ( NbSmuSrbmRegisterWrite (FCRxFF30_0398_ADDRESS, &FCRxFF30_0398.Value, FALSE, Gnb->StdHeader); } + Value = 0; + for (Index = 0x8400; Index <= 0x85AC; Index = Index + 4) { + NbSmuRcuRegisterWrite ( + (UINT16) Index, + &Value, + 1, + FALSE, + Gnb->StdHeader + ); + } + + NbSmuRcuRegisterWrite ( + 0x9000, + &Value, + 1, + FALSE, + Gnb->StdHeader + ); + + NbSmuRcuRegisterWrite ( + 0x9004, + &Value, + 1, + FALSE, + Gnb->StdHeader + ); + return AGESA_SUCCESS; } diff --git a/src/vendorcode/amd/agesa/f14/Proc/GNB/Nb/NbPowerMgmt.c b/src/vendorcode/amd/agesa/f14/Proc/GNB/Nb/NbPowerMgmt.c index 11a872408a..56e6a1a02c 100644 --- a/src/vendorcode/amd/agesa/f14/Proc/GNB/Nb/NbPowerMgmt.c +++ b/src/vendorcode/amd/agesa/f14/Proc/GNB/Nb/NbPowerMgmt.c @@ -9,7 +9,7 @@ * @xrefitem bom "File Content Label" "Release Content" * @e project: AGESA * @e sub-project: GNB - * @e \$Revision: 39275 $ @e \$Date: 2010-10-09 08:22:05 +0800 (Sat, 09 Oct 2010) $ + * @e \$Revision: 47490 $ @e \$Date: 2011-02-22 08:34:28 -0700 (Tue, 22 Feb 2011) $ * */ /* @@ -52,9 +52,11 @@ #include "amdlib.h" #include "Ids.h" #include "Gnb.h" +#include "GnbFuseTable.h" #include GNB_MODULE_DEFINITIONS (GnbCommonLib) #include "NbConfigData.h" #include "NbSmuLib.h" +#include "NbFamilyServices.h" #include "NbPowerMgmt.h" #include "OptionGnb.h" #include "GfxLib.h" @@ -524,7 +526,7 @@ NbInitDceDisplayClockGating ( //FCRxFF30_01F5[CgDcCgttDispclkOverride] NbSmuSrbmRegisterRead (FCRxFF30_01F5_ADDRESS, &FCRxFF30_01F5.Value, Gnb->StdHeader); - FCRxFF30_01F5.Field.CgDcCgttDispClkOverride = 0; + FCRxFF30_01F5.Field.CgDcCgttDispclkOverride = 0; NbSmuSrbmRegisterWrite (FCRxFF30_01F5_ADDRESS, &FCRxFF30_01F5.Value, TRUE, Gnb->StdHeader); } @@ -557,6 +559,8 @@ NbInitClockGating ( NbClkGatingCtrl.Dce_Sclk_Gating = TRUE; NbClkGatingCtrl.Dce_Dispclk_Gating = TRUE; + NbFmNbClockGating (&NbClkGatingCtrl, Gnb->StdHeader); + IDS_OPTION_HOOK (IDS_GNB_CLOCK_GATING, &NbClkGatingCtrl, Gnb->StdHeader); diff --git a/src/vendorcode/amd/agesa/f14/Proc/GNB/Nb/NbPowerMgmt.h b/src/vendorcode/amd/agesa/f14/Proc/GNB/Nb/NbPowerMgmt.h index bb5a54904c..b3dd12cfb6 100644 --- a/src/vendorcode/amd/agesa/f14/Proc/GNB/Nb/NbPowerMgmt.h +++ b/src/vendorcode/amd/agesa/f14/Proc/GNB/Nb/NbPowerMgmt.h @@ -48,11 +48,6 @@ #define _NBPOWERMGMT_H_ -AGESA_STATUS -NbInitPowerManagement ( - IN GNB_PLATFORM_CONFIG *Gnb - ); - ///Control structure for clock gating feature typedef struct { BOOLEAN Smu_Sclk_Gating; ///<Control Smu SClk gating 1 Enable 0 Disable @@ -67,4 +62,51 @@ typedef struct { BOOLEAN Dce_Dispclk_Gating; ///<Control DCE dispaly gating 1 Enable 0 Disable } NB_CLK_GATING_CTRL; +AGESA_STATUS +NbInitPowerManagement ( + IN GNB_PLATFORM_CONFIG *Gnb + ); + +VOID +NbInitSmuClockGating ( + IN NB_CLK_GATING_CTRL *NbClkGatingCtrl, + IN GNB_PLATFORM_CONFIG *Gnb + ); + +VOID +NbInitOrbClockGating ( + IN NB_CLK_GATING_CTRL *NbClkGatingCtrl, + IN GNB_PLATFORM_CONFIG *Gnb + ); + +VOID +NbInitIocClockGating ( + IN NB_CLK_GATING_CTRL *NbClkGatingCtrl, + IN GNB_PLATFORM_CONFIG *Gnb + ); + +VOID +NbInitBifClockGating ( + IN NB_CLK_GATING_CTRL *NbClkGatingCtrl, + IN GNB_PLATFORM_CONFIG *Gnb + ); + +VOID +NbInitGmcClockGating ( + IN NB_CLK_GATING_CTRL *NbClkGatingCtrl, + IN GNB_PLATFORM_CONFIG *Gnb + ); + +VOID +NbInitDceSclkClockGating ( + IN NB_CLK_GATING_CTRL *NbClkGatingCtrl, + IN GNB_PLATFORM_CONFIG *Gnb + ); + +VOID +NbInitDceDisplayClockGating ( + IN NB_CLK_GATING_CTRL *NbClkGatingCtrl, + IN GNB_PLATFORM_CONFIG *Gnb + ); + #endif diff --git a/src/vendorcode/amd/agesa/f14/Proc/GNB/Nb/NbSmuLib.c b/src/vendorcode/amd/agesa/f14/Proc/GNB/Nb/NbSmuLib.c index fa3ac0686c..06f3ba5b57 100644 --- a/src/vendorcode/amd/agesa/f14/Proc/GNB/Nb/NbSmuLib.c +++ b/src/vendorcode/amd/agesa/f14/Proc/GNB/Nb/NbSmuLib.c @@ -82,7 +82,6 @@ typedef struct { *---------------------------------------------------------------------------------------- */ - /*----------------------------------------------------------------------------------------*/ /** * SMU indirect register read diff --git a/src/vendorcode/amd/agesa/f14/Proc/GNB/Nb/NbSmuLib.h b/src/vendorcode/amd/agesa/f14/Proc/GNB/Nb/NbSmuLib.h index a54b7e8939..a7c7da5564 100644 --- a/src/vendorcode/amd/agesa/f14/Proc/GNB/Nb/NbSmuLib.h +++ b/src/vendorcode/amd/agesa/f14/Proc/GNB/Nb/NbSmuLib.h @@ -104,6 +104,14 @@ NbSmuIndirectPoll ( ); VOID +NbSmuIndirectWriteEx ( + IN UINT8 Address, + IN ACCESS_WIDTH Width, + IN VOID *Value, + IN AMD_CONFIG_PARAMS *StdHeader + ); + +VOID NbSmuIndirectWrite ( IN UINT8 Address, IN ACCESS_WIDTH Width, @@ -112,6 +120,13 @@ NbSmuIndirectWrite ( ); VOID +NbSmuIndirectWriteS3Script ( + IN AMD_CONFIG_PARAMS *StdHeader, + IN UINT16 ContextLength, + IN VOID* Context + ); + +VOID NbSmuRcuRegisterWrite ( IN UINT16 Address, IN UINT32 *Value, @@ -170,6 +185,14 @@ NbSmuReadEfuse ( IN AMD_CONFIG_PARAMS *StdHeader ); +UINT32 +NbSmuReadEfuseField ( + IN UINT8 Chain, + IN UINT16 Offset, + IN UINT8 Length, + IN AMD_CONFIG_PARAMS *StdHeader + ); + VOID NbSmuFirmwareDownload ( IN SMU_FIRMWARE_HEADER *Firmware, diff --git a/src/vendorcode/amd/agesa/f14/Proc/GNB/PCIe/Family/0x14/F14PcieAlib.c b/src/vendorcode/amd/agesa/f14/Proc/GNB/PCIe/Family/0x14/F14PcieAlib.c index e23cc7c543..ef6fae742d 100644 --- a/src/vendorcode/amd/agesa/f14/Proc/GNB/PCIe/Family/0x14/F14PcieAlib.c +++ b/src/vendorcode/amd/agesa/f14/Proc/GNB/PCIe/Family/0x14/F14PcieAlib.c @@ -9,7 +9,7 @@ * @xrefitem bom "File Content Label" "Release Content" * @e project: AGESA * @e sub-project: GNB - * @e \$Revision: 39275 $ @e \$Date: 2010-10-09 08:22:05 +0800 (Sat, 09 Oct 2010) $ + * @e \$Revision: 46946 $ @e \$Date: 2011-02-11 11:53:30 -0700 (Fri, 11 Feb 2011) $ * */ /* @@ -50,6 +50,13 @@ */ #include "AGESA.h" #include "Ids.h" +#include "heapManager.h" +#include "Gnb.h" +//#include "GnbPcieFamServices.h" +#include "GnbFuseTable.h" +#include "GnbRegistersON.h" +#include "cpuLateInit.h" +#include GNB_MODULE_DEFINITIONS (GnbCommonLib) #include "F14PcieAlibSsdt.h" #include "Filecode.h" #define FILECODE PROC_GNB_PCIE_FAMILY_0X14_F14PCIEALIB_FILECODE @@ -69,4 +76,63 @@ * P R O T O T Y P E S O F L O C A L F U N C T I O N S *---------------------------------------------------------------------------------------- */ +AGESA_STATUS +PcieFmAlibBuildAcpiTable ( + IN VOID *AlibSsdtPtr, + IN AMD_CONFIG_PARAMS *StdHeader + ); +/*----------------------------------------------------------------------------------------*/ +/** + * Build ALIB ACPI table + * + * + * + * @param[in,out] AlibSsdtPtr Pointer to ALIB SSDT table + * @param[in] StdHeader Standard Configuration Header + * @retval AGESA_SUCCESS + * @retval AGESA_FATAL + */ + +AGESA_STATUS +PcieFmAlibBuildAcpiTable ( + IN VOID *AlibSsdtPtr, + IN AMD_CONFIG_PARAMS *StdHeader + ) +{ + AGESA_STATUS AgesaStatus; + D18F4x15C_STRUCT D18F4x15C; + PP_FUSE_ARRAY *PpFuseArray; + UINT32 AmlObjName; + VOID *AmlObjPtr; + + IDS_HDT_CONSOLE (GNB_TRACE, "PcieFmAlibBuildAcpiTable Enter\n"); + AgesaStatus = AGESA_SUCCESS; + // Set voltage configuration + PpFuseArray = GnbLocateHeapBuffer (AMD_PP_FUSE_TABLE_HANDLE, StdHeader); + ASSERT (PpFuseArray != NULL); + if (PpFuseArray != NULL) { + GnbLibPciRead ( + MAKE_SBDFO (0, 0, 0x18, 0x4, D18F4x15C_ADDRESS), + AccessWidth32, + &D18F4x15C.Value, + StdHeader + ); + if (D18F4x15C.Field.BoostSrc != 0 || PpFuseArray->GpuBoostCap != 0) { +// AmlObjName = 'B0DA'; + AmlObjName = Int32FromChar ('B', '0', 'D', 'A'); + AmlObjPtr = GnbLibFind (AlibSsdtPtr, ((ACPI_TABLE_HEADER*) &AlibSsdt[0])->TableLength, (UINT8*) &AmlObjName, sizeof (AmlObjName)); + ASSERT (AmlObjPtr != NULL); + if (AmlObjPtr != NULL) { + *(UINT8*)((UINT8*) AmlObjPtr + 5) = 1; + } else { + AgesaStatus = AGESA_FATAL; + } + } + } else { + AgesaStatus = AGESA_FATAL; + } + + IDS_HDT_CONSOLE (GNB_TRACE, "PcieFmAlibBuildAcpiTable Exit[0x%x]\n", AgesaStatus); + return AgesaStatus; +} diff --git a/src/vendorcode/amd/agesa/f14/Proc/GNB/PCIe/Family/0x14/F14PcieAlib.esl b/src/vendorcode/amd/agesa/f14/Proc/GNB/PCIe/Family/0x14/F14PcieAlib.esl index d33c341048..fbfea63d62 100644 --- a/src/vendorcode/amd/agesa/f14/Proc/GNB/PCIe/Family/0x14/F14PcieAlib.esl +++ b/src/vendorcode/amd/agesa/f14/Proc/GNB/PCIe/Family/0x14/F14PcieAlib.esl @@ -97,6 +97,7 @@ DefinitionBlock ( } } +#ifdef PCIE_PHY_LANE_POWER_GATE_SUPPORT /*----------------------------------------------------------------------------------------*/ /** * Power gate PCIe phy lanes (hotplug support) @@ -108,10 +109,10 @@ DefinitionBlock ( Method (procPcieLanePowerControl, 3, NotSerialized) { // stub function } - +#endif /*----------------------------------------------------------------------------------------*/ /** - * Read RCU register + * Adjust PLL settings stub * * Arg0 - 1 - GEN1 2 - GEN2 * @@ -119,7 +120,26 @@ DefinitionBlock ( Method (procPcieAdjustPll, 1, NotSerialized) { //stub function } - + Name (AD0B, 0) + /*----------------------------------------------------------------------------------------*/ + /** + * APM/PDM stub + * + * Arg0 - 0 (AC) 1 (DC) + * + */ + Method (procApmPdmActivate, 1, NotSerialized) { + if (LEqual (AD0B, 1)) { + Store (Or(ShiftLeft (0x18, 3), 4), Local1) + Store (procPciDwordRead (Local1, 0x15C), Local2) + if (LEqual (Arg0, DEF_PSPP_STATE_AC)) { + Or (Local2, 0x01, Local2) + } else { + And (Local2, 0xfffffffc, Local2) + } + procPciDwordWrite (Local1, 0x15C, Local2) + } + } } //End of Scope(\_SB) } //End of DefinitionBlock diff --git a/src/vendorcode/amd/agesa/f14/Proc/GNB/PCIe/Family/0x14/F14PcieAlibSsdt.h b/src/vendorcode/amd/agesa/f14/Proc/GNB/PCIe/Family/0x14/F14PcieAlibSsdt.h index 533521b4a3..0fb3b9155c 100644 --- a/src/vendorcode/amd/agesa/f14/Proc/GNB/PCIe/Family/0x14/F14PcieAlibSsdt.h +++ b/src/vendorcode/amd/agesa/f14/Proc/GNB/PCIe/Family/0x14/F14PcieAlibSsdt.h @@ -12,51 +12,51 @@ * */ /* - ***************************************************************************** - * - * Copyright (c) 2011, Advanced Micro Devices, Inc. - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * * Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * * Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * * Neither the name of Advanced Micro Devices, Inc. nor the names of - * its contributors may be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY - * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND - * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - * *************************************************************************** - * - */ +***************************************************************************** +* +* Copyright (c) 2011, Advanced Micro Devices, Inc. +* All rights reserved. +* +* Redistribution and use in source and binary forms, with or without +* modification, are permitted provided that the following conditions are met: +* * Redistributions of source code must retain the above copyright +* notice, this list of conditions and the following disclaimer. +* * Redistributions in binary form must reproduce the above copyright +* notice, this list of conditions and the following disclaimer in the +* documentation and/or other materials provided with the distribution. +* * Neither the name of Advanced Micro Devices, Inc. nor the names of +* its contributors may be used to endorse or promote products derived +* from this software without specific prior written permission. +* +* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND +* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +* DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY +* DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES +* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; +* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND +* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS +* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +* +**************************************************************************** +* +*/ #ifndef _F14PCIEALIBSSDT_H_ #define _F14PCIEALIBSSDT_H_ UINT8 AlibSsdt[] = { - 0x53, 0x53, 0x44, 0x54, 0xFA, 0x12, 0x00, 0x00, - 0x02, 0xC9, 0x41, 0x4D, 0x44, 0x00, 0x00, 0x00, + 0x53, 0x53, 0x44, 0x54, 0x8E, 0x16, 0x00, 0x00, + 0x02, 0x11, 0x41, 0x4D, 0x44, 0x00, 0x00, 0x00, 0x41, 0x4C, 0x49, 0x42, 0x00, 0x00, 0x00, 0x00, 0x01, 0x00, 0x00, 0x00, 0x4D, 0x53, 0x46, 0x54, - 0x00, 0x00, 0x00, 0x04, 0x10, 0x85, 0x2D, 0x01, + 0x00, 0x00, 0x00, 0x04, 0x10, 0x89, 0x66, 0x01, 0x5C, 0x5F, 0x53, 0x42, 0x5F, 0x08, 0x41, 0x30, 0x30, 0x31, 0x0A, 0x06, 0x08, 0x41, 0x44, 0x30, 0x31, 0x0C, 0x00, 0x00, 0x00, 0xE0, 0x06, 0x41, - 0x44, 0x30, 0x31, 0x41, 0x30, 0x39, 0x31, 0x08, - 0x41, 0x44, 0x30, 0x37, 0x12, 0x45, 0x06, 0x07, + 0x44, 0x30, 0x31, 0x41, 0x30, 0x38, 0x36, 0x08, + 0x41, 0x44, 0x30, 0x37, 0x12, 0x43, 0x07, 0x08, 0x11, 0x0D, 0x0A, 0x0A, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x11, 0x0D, 0x0A, 0x0A, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, @@ -69,81 +69,84 @@ UINT8 AlibSsdt[] = { 0x0A, 0x0A, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x11, 0x0D, 0x0A, 0x0A, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x06, 0x41, 0x44, 0x30, 0x37, 0x41, - 0x30, 0x39, 0x32, 0x14, 0x41, 0x05, 0x41, 0x4C, + 0x00, 0x00, 0x11, 0x0D, 0x0A, 0x0A, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x06, 0x41, 0x44, 0x30, 0x37, 0x41, 0x30, 0x38, + 0x37, 0x08, 0x41, 0x30, 0x38, 0x38, 0x11, 0x04, + 0x0B, 0x00, 0x01, 0x14, 0x41, 0x05, 0x41, 0x4C, 0x49, 0x42, 0x02, 0xA0, 0x0B, 0x93, 0x68, 0x0A, - 0x01, 0xA4, 0x41, 0x30, 0x31, 0x38, 0x69, 0xA0, + 0x01, 0xA4, 0x41, 0x30, 0x32, 0x36, 0x69, 0xA0, 0x0B, 0x93, 0x68, 0x0A, 0x02, 0xA4, 0x41, 0x30, - 0x32, 0x31, 0x69, 0xA0, 0x0B, 0x93, 0x68, 0x0A, - 0x03, 0xA4, 0x41, 0x30, 0x33, 0x32, 0x69, 0xA0, + 0x33, 0x30, 0x69, 0xA0, 0x0B, 0x93, 0x68, 0x0A, + 0x03, 0xA4, 0x41, 0x30, 0x34, 0x31, 0x69, 0xA0, 0x0B, 0x93, 0x68, 0x0A, 0x04, 0xA4, 0x41, 0x30, - 0x36, 0x33, 0x69, 0xA0, 0x0A, 0x93, 0x68, 0x0A, - 0x05, 0xA4, 0x41, 0x30, 0x39, 0x33, 0xA0, 0x0B, + 0x36, 0x36, 0x69, 0xA0, 0x0A, 0x93, 0x68, 0x0A, + 0x05, 0xA4, 0x41, 0x30, 0x38, 0x39, 0xA0, 0x0B, 0x93, 0x68, 0x0A, 0x06, 0xA4, 0x41, 0x30, 0x36, - 0x36, 0x69, 0xA4, 0x0A, 0x00, 0x14, 0x09, 0x41, - 0x30, 0x39, 0x33, 0x08, 0xA4, 0x0A, 0x00, 0x14, - 0x31, 0x41, 0x30, 0x33, 0x31, 0x02, 0x72, 0x41, - 0x30, 0x39, 0x31, 0x79, 0x68, 0x0A, 0x0C, 0x00, + 0x39, 0x69, 0xA4, 0x0A, 0x00, 0x14, 0x09, 0x41, + 0x30, 0x38, 0x39, 0x08, 0xA4, 0x0A, 0x00, 0x14, + 0x31, 0x41, 0x30, 0x30, 0x37, 0x0A, 0x72, 0x41, + 0x30, 0x38, 0x36, 0x79, 0x68, 0x0A, 0x0C, 0x00, 0x60, 0x72, 0x69, 0x60, 0x60, 0x5B, 0x80, 0x41, - 0x30, 0x39, 0x34, 0x00, 0x60, 0x0A, 0x04, 0x5B, - 0x81, 0x0B, 0x41, 0x30, 0x39, 0x34, 0x03, 0x41, - 0x30, 0x39, 0x35, 0x20, 0xA4, 0x41, 0x30, 0x39, - 0x35, 0x14, 0x32, 0x41, 0x30, 0x35, 0x39, 0x03, - 0x72, 0x41, 0x30, 0x39, 0x31, 0x79, 0x68, 0x0A, + 0x30, 0x39, 0x30, 0x00, 0x60, 0x0A, 0x04, 0x5B, + 0x81, 0x0B, 0x41, 0x30, 0x39, 0x30, 0x03, 0x41, + 0x30, 0x39, 0x31, 0x20, 0xA4, 0x41, 0x30, 0x39, + 0x31, 0x14, 0x32, 0x41, 0x30, 0x30, 0x38, 0x0B, + 0x72, 0x41, 0x30, 0x38, 0x36, 0x79, 0x68, 0x0A, 0x0C, 0x00, 0x60, 0x72, 0x69, 0x60, 0x60, 0x5B, - 0x80, 0x41, 0x30, 0x39, 0x34, 0x00, 0x60, 0x0A, - 0x04, 0x5B, 0x81, 0x0B, 0x41, 0x30, 0x39, 0x34, - 0x03, 0x41, 0x30, 0x39, 0x35, 0x20, 0x70, 0x6A, - 0x41, 0x30, 0x39, 0x35, 0x14, 0x1C, 0x41, 0x30, - 0x35, 0x35, 0x04, 0x70, 0x41, 0x30, 0x33, 0x31, + 0x80, 0x41, 0x30, 0x39, 0x30, 0x00, 0x60, 0x0A, + 0x04, 0x5B, 0x81, 0x0B, 0x41, 0x30, 0x39, 0x30, + 0x03, 0x41, 0x30, 0x39, 0x31, 0x20, 0x70, 0x6A, + 0x41, 0x30, 0x39, 0x31, 0x14, 0x1C, 0x41, 0x30, + 0x35, 0x32, 0x0C, 0x70, 0x41, 0x30, 0x30, 0x37, 0x68, 0x69, 0x60, 0x7D, 0x7B, 0x60, 0x6A, 0x00, - 0x6B, 0x60, 0x41, 0x30, 0x35, 0x39, 0x68, 0x69, - 0x60, 0x5B, 0x01, 0x41, 0x30, 0x39, 0x36, 0x00, - 0x14, 0x32, 0x41, 0x30, 0x35, 0x38, 0x02, 0x5B, - 0x23, 0x41, 0x30, 0x39, 0x36, 0xFF, 0xFF, 0x70, + 0x6B, 0x60, 0x41, 0x30, 0x30, 0x38, 0x68, 0x69, + 0x60, 0x5B, 0x01, 0x41, 0x30, 0x39, 0x32, 0x00, + 0x14, 0x32, 0x41, 0x30, 0x35, 0x33, 0x02, 0x5B, + 0x23, 0x41, 0x30, 0x39, 0x32, 0xFF, 0xFF, 0x70, 0x79, 0x72, 0x68, 0x0A, 0x02, 0x00, 0x0A, 0x03, - 0x00, 0x60, 0x41, 0x30, 0x35, 0x39, 0x60, 0x0A, - 0xE0, 0x69, 0x70, 0x41, 0x30, 0x33, 0x31, 0x60, + 0x00, 0x60, 0x41, 0x30, 0x30, 0x38, 0x60, 0x0A, + 0xE0, 0x69, 0x70, 0x41, 0x30, 0x30, 0x37, 0x60, 0x0A, 0xE4, 0x60, 0x5B, 0x27, 0x41, 0x30, 0x39, - 0x36, 0xA4, 0x60, 0x14, 0x2F, 0x41, 0x30, 0x39, - 0x37, 0x03, 0x5B, 0x23, 0x41, 0x30, 0x39, 0x36, + 0x32, 0xA4, 0x60, 0x14, 0x2F, 0x41, 0x30, 0x39, + 0x33, 0x03, 0x5B, 0x23, 0x41, 0x30, 0x39, 0x32, 0xFF, 0xFF, 0x70, 0x79, 0x72, 0x68, 0x0A, 0x02, - 0x00, 0x0A, 0x03, 0x00, 0x60, 0x41, 0x30, 0x35, - 0x39, 0x60, 0x0A, 0xE0, 0x69, 0x41, 0x30, 0x35, - 0x39, 0x60, 0x0A, 0xE4, 0x6A, 0x5B, 0x27, 0x41, - 0x30, 0x39, 0x36, 0x14, 0x1C, 0x41, 0x30, 0x35, - 0x34, 0x04, 0x70, 0x41, 0x30, 0x35, 0x38, 0x68, + 0x00, 0x0A, 0x03, 0x00, 0x60, 0x41, 0x30, 0x30, + 0x38, 0x60, 0x0A, 0xE0, 0x69, 0x41, 0x30, 0x30, + 0x38, 0x60, 0x0A, 0xE4, 0x6A, 0x5B, 0x27, 0x41, + 0x30, 0x39, 0x32, 0x14, 0x1C, 0x41, 0x30, 0x35, + 0x30, 0x04, 0x70, 0x41, 0x30, 0x35, 0x33, 0x68, 0x69, 0x60, 0x7D, 0x7B, 0x60, 0x6A, 0x00, 0x6B, - 0x60, 0x41, 0x30, 0x39, 0x37, 0x68, 0x69, 0x60, - 0x5B, 0x01, 0x41, 0x30, 0x39, 0x38, 0x00, 0x14, - 0x29, 0x41, 0x30, 0x36, 0x31, 0x03, 0x5B, 0x23, - 0x41, 0x30, 0x39, 0x38, 0xFF, 0xFF, 0x41, 0x30, - 0x35, 0x39, 0x68, 0x69, 0x6A, 0x70, 0x41, 0x30, - 0x33, 0x31, 0x68, 0x72, 0x69, 0x0A, 0x04, 0x00, - 0x60, 0x5B, 0x27, 0x41, 0x30, 0x39, 0x38, 0xA4, - 0x60, 0x14, 0x26, 0x41, 0x30, 0x36, 0x32, 0x04, - 0x5B, 0x23, 0x41, 0x30, 0x39, 0x38, 0xFF, 0xFF, - 0x41, 0x30, 0x35, 0x39, 0x68, 0x69, 0x6A, 0x41, - 0x30, 0x35, 0x39, 0x68, 0x72, 0x69, 0x0A, 0x04, - 0x00, 0x6B, 0x5B, 0x27, 0x41, 0x30, 0x39, 0x38, - 0x14, 0x1E, 0x41, 0x30, 0x35, 0x33, 0x05, 0x70, - 0x41, 0x30, 0x36, 0x31, 0x68, 0x69, 0x6A, 0x60, + 0x60, 0x41, 0x30, 0x39, 0x33, 0x68, 0x69, 0x60, + 0x5B, 0x01, 0x41, 0x30, 0x39, 0x34, 0x00, 0x14, + 0x29, 0x41, 0x30, 0x34, 0x32, 0x03, 0x5B, 0x23, + 0x41, 0x30, 0x39, 0x34, 0xFF, 0xFF, 0x41, 0x30, + 0x30, 0x38, 0x68, 0x69, 0x6A, 0x70, 0x41, 0x30, + 0x30, 0x37, 0x68, 0x72, 0x69, 0x0A, 0x04, 0x00, + 0x60, 0x5B, 0x27, 0x41, 0x30, 0x39, 0x34, 0xA4, + 0x60, 0x14, 0x26, 0x41, 0x30, 0x34, 0x33, 0x04, + 0x5B, 0x23, 0x41, 0x30, 0x39, 0x34, 0xFF, 0xFF, + 0x41, 0x30, 0x30, 0x38, 0x68, 0x69, 0x6A, 0x41, + 0x30, 0x30, 0x38, 0x68, 0x72, 0x69, 0x0A, 0x04, + 0x00, 0x6B, 0x5B, 0x27, 0x41, 0x30, 0x39, 0x34, + 0x14, 0x1E, 0x41, 0x30, 0x32, 0x38, 0x05, 0x70, + 0x41, 0x30, 0x34, 0x32, 0x68, 0x69, 0x6A, 0x60, 0x7D, 0x7B, 0x60, 0x6B, 0x00, 0x6C, 0x60, 0x41, - 0x30, 0x36, 0x32, 0x68, 0x69, 0x6A, 0x60, 0x14, + 0x30, 0x34, 0x33, 0x68, 0x69, 0x6A, 0x60, 0x14, 0x0F, 0x41, 0x30, 0x37, 0x33, 0x01, 0xA4, 0x83, - 0x88, 0x41, 0x30, 0x39, 0x32, 0x68, 0x00, 0x14, - 0x42, 0x05, 0x41, 0x30, 0x35, 0x36, 0x02, 0x70, + 0x88, 0x41, 0x30, 0x38, 0x37, 0x68, 0x00, 0x14, + 0x42, 0x05, 0x41, 0x30, 0x35, 0x39, 0x02, 0x70, 0x0A, 0x34, 0x61, 0xA0, 0x11, 0x93, 0x41, 0x30, - 0x33, 0x31, 0x68, 0x0A, 0x00, 0x0C, 0xFF, 0xFF, + 0x30, 0x37, 0x68, 0x0A, 0x00, 0x0C, 0xFF, 0xFF, 0xFF, 0xFF, 0xA4, 0x0A, 0x00, 0x70, 0x0A, 0x01, 0x60, 0xA2, 0x2E, 0x93, 0x60, 0x0A, 0x01, 0x70, - 0x7B, 0x41, 0x30, 0x33, 0x31, 0x68, 0x61, 0x0A, - 0xFF, 0x00, 0x61, 0xA0, 0x1C, 0x92, 0x93, 0x61, - 0x0A, 0x00, 0xA0, 0x11, 0x93, 0x7B, 0x41, 0x30, - 0x33, 0x31, 0x68, 0x61, 0x0A, 0xFF, 0x00, 0x69, + 0x7B, 0x41, 0x30, 0x30, 0x37, 0x68, 0x61, 0x0A, + 0xFF, 0x00, 0x61, 0xA0, 0x06, 0x93, 0x61, 0x0A, + 0x00, 0xA5, 0xA0, 0x11, 0x93, 0x7B, 0x41, 0x30, + 0x30, 0x37, 0x68, 0x61, 0x0A, 0xFF, 0x00, 0x69, 0x70, 0x0A, 0x00, 0x60, 0xA1, 0x03, 0x75, 0x61, 0xA4, 0x61, 0x14, 0x47, 0x09, 0x41, 0x30, 0x35, - 0x37, 0x02, 0x5B, 0x80, 0x50, 0x4D, 0x49, 0x4F, + 0x38, 0x0A, 0x5B, 0x80, 0x50, 0x4D, 0x49, 0x4F, 0x01, 0x0B, 0xD6, 0x0C, 0x0A, 0x02, 0x5B, 0x81, 0x10, 0x50, 0x4D, 0x49, 0x4F, 0x01, 0x50, 0x4D, 0x52, 0x49, 0x08, 0x50, 0x4D, 0x52, 0x44, 0x08, @@ -162,18 +165,18 @@ UINT8 AlibSsdt[] = { 0x60, 0x7D, 0x7B, 0x60, 0x0C, 0xFC, 0xFF, 0xFF, 0xFF, 0x00, 0x68, 0x60, 0x70, 0x60, 0x41, 0x42, 0x44, 0x41, 0x14, 0x48, 0x05, 0x41, 0x30, 0x38, - 0x36, 0x01, 0x70, 0x41, 0x30, 0x36, 0x31, 0x0A, + 0x31, 0x01, 0x70, 0x41, 0x30, 0x34, 0x32, 0x0A, 0x00, 0x0A, 0x60, 0x0A, 0xCD, 0x60, 0x75, 0x68, 0x7D, 0x7B, 0x60, 0x0C, 0xFF, 0xFF, 0xFF, 0xFE, 0x00, 0x7B, 0x80, 0x7B, 0x60, 0x0C, 0x00, 0x00, 0x00, 0x01, 0x00, 0x00, 0x0C, 0x00, 0x00, 0x00, 0x01, 0x00, 0x60, 0x7D, 0x7B, 0x60, 0x0C, 0xFF, 0xFF, 0x00, 0xFD, 0x00, 0x79, 0x68, 0x0A, 0x10, - 0x00, 0x60, 0x41, 0x30, 0x36, 0x32, 0x0A, 0x00, + 0x00, 0x60, 0x41, 0x30, 0x34, 0x33, 0x0A, 0x00, 0x0A, 0x60, 0x0A, 0xCD, 0x60, 0x70, 0x41, 0x30, - 0x36, 0x31, 0x0A, 0x00, 0x0A, 0x60, 0x0A, 0xCE, + 0x34, 0x32, 0x0A, 0x00, 0x0A, 0x60, 0x0A, 0xCE, 0x60, 0xA4, 0x60, 0x14, 0x47, 0x0A, 0x41, 0x30, - 0x38, 0x37, 0x03, 0x70, 0x41, 0x30, 0x36, 0x31, + 0x38, 0x32, 0x03, 0x70, 0x41, 0x30, 0x34, 0x32, 0x0A, 0x00, 0x0A, 0x60, 0x0A, 0xCD, 0x60, 0x70, 0x7B, 0x69, 0x0B, 0xFF, 0xFF, 0x00, 0x61, 0x7D, 0x7B, 0x60, 0x0C, 0xFF, 0xFF, 0xFF, 0xFE, 0x00, @@ -182,8 +185,8 @@ UINT8 AlibSsdt[] = { 0x00, 0x60, 0x7D, 0x7B, 0x60, 0x0C, 0x00, 0x00, 0x00, 0xFD, 0x00, 0x79, 0x68, 0x0A, 0x10, 0x00, 0x60, 0x7D, 0x60, 0x0C, 0x00, 0x00, 0x00, 0x02, - 0x60, 0x7D, 0x60, 0x61, 0x60, 0x41, 0x30, 0x36, - 0x32, 0x0A, 0x00, 0x0A, 0x60, 0x0A, 0xCD, 0x60, + 0x60, 0x7D, 0x60, 0x61, 0x60, 0x41, 0x30, 0x34, + 0x33, 0x0A, 0x00, 0x0A, 0x60, 0x0A, 0xCD, 0x60, 0xA0, 0x4A, 0x04, 0x93, 0x6A, 0x0A, 0x01, 0x70, 0x7A, 0x69, 0x0A, 0x10, 0x00, 0x61, 0x7D, 0x7B, 0x60, 0x0C, 0xFF, 0xFF, 0xFF, 0xFE, 0x00, 0x7B, @@ -192,25 +195,25 @@ UINT8 AlibSsdt[] = { 0x60, 0x7D, 0x7B, 0x60, 0x0C, 0x00, 0x00, 0x00, 0xFF, 0x00, 0x79, 0x72, 0x68, 0x0A, 0x01, 0x00, 0x0A, 0x10, 0x00, 0x60, 0x7D, 0x60, 0x61, 0x60, - 0x41, 0x30, 0x36, 0x32, 0x0A, 0x00, 0x0A, 0x60, + 0x41, 0x30, 0x34, 0x33, 0x0A, 0x00, 0x0A, 0x60, 0x0A, 0xCD, 0x60, 0x14, 0x4F, 0x04, 0x41, 0x30, - 0x38, 0x38, 0x02, 0x7D, 0x79, 0x68, 0x0A, 0x03, - 0x00, 0x0A, 0x01, 0x60, 0x41, 0x30, 0x38, 0x37, + 0x38, 0x33, 0x02, 0x7D, 0x79, 0x68, 0x0A, 0x03, + 0x00, 0x0A, 0x01, 0x60, 0x41, 0x30, 0x38, 0x32, 0x0A, 0x03, 0x60, 0x0A, 0x01, 0xA0, 0x15, 0x90, 0x69, 0x0A, 0x01, 0xA2, 0x0F, 0x92, 0x93, 0x7B, - 0x41, 0x30, 0x38, 0x36, 0x0A, 0x03, 0x0A, 0x02, + 0x41, 0x30, 0x38, 0x31, 0x0A, 0x03, 0x0A, 0x02, 0x00, 0x0A, 0x02, 0xA0, 0x15, 0x90, 0x69, 0x0A, 0x02, 0xA2, 0x0F, 0x92, 0x93, 0x7B, 0x41, 0x30, - 0x38, 0x36, 0x0A, 0x03, 0x0A, 0x04, 0x00, 0x0A, - 0x04, 0x41, 0x30, 0x38, 0x37, 0x0A, 0x03, 0x0A, - 0x00, 0x0A, 0x00, 0x14, 0x18, 0x41, 0x30, 0x30, - 0x34, 0x02, 0x41, 0x30, 0x38, 0x37, 0x0A, 0x0B, - 0x68, 0x0A, 0x00, 0x41, 0x30, 0x38, 0x37, 0x0A, + 0x38, 0x31, 0x0A, 0x03, 0x0A, 0x04, 0x00, 0x0A, + 0x04, 0x41, 0x30, 0x38, 0x32, 0x0A, 0x03, 0x0A, + 0x00, 0x0A, 0x01, 0x14, 0x18, 0x41, 0x30, 0x30, + 0x34, 0x02, 0x41, 0x30, 0x38, 0x32, 0x0A, 0x0B, + 0x68, 0x0A, 0x00, 0x41, 0x30, 0x38, 0x32, 0x0A, 0x05, 0x69, 0x0A, 0x01, 0x14, 0x19, 0x41, 0x30, - 0x30, 0x33, 0x01, 0x41, 0x30, 0x38, 0x37, 0x0A, + 0x30, 0x33, 0x01, 0x41, 0x30, 0x38, 0x32, 0x0A, 0x0B, 0x68, 0x0A, 0x00, 0x70, 0x41, 0x30, 0x38, - 0x36, 0x0A, 0x05, 0x60, 0xA4, 0x60, 0x14, 0x49, - 0x07, 0x41, 0x30, 0x38, 0x39, 0x01, 0x70, 0x7D, + 0x31, 0x0A, 0x05, 0x60, 0xA4, 0x60, 0x14, 0x49, + 0x07, 0x41, 0x30, 0x38, 0x34, 0x01, 0x70, 0x7D, 0x7B, 0x68, 0x0A, 0xFF, 0x00, 0x0C, 0x00, 0x50, 0x86, 0x01, 0x00, 0x60, 0x70, 0x7D, 0x7B, 0x68, 0x0C, 0x00, 0xFF, 0xFF, 0xFF, 0x00, 0x0A, 0x04, @@ -221,11 +224,11 @@ UINT8 AlibSsdt[] = { 0x86, 0x61, 0x41, 0x30, 0x30, 0x34, 0x0B, 0x08, 0x86, 0x62, 0xA0, 0x12, 0x93, 0x7A, 0x68, 0x0A, 0x10, 0x00, 0x0B, 0x00, 0xFE, 0x41, 0x30, 0x38, - 0x38, 0x0A, 0x0D, 0x0A, 0x03, 0xA0, 0x12, 0x93, + 0x33, 0x0A, 0x0D, 0x0A, 0x03, 0xA0, 0x12, 0x93, 0x7A, 0x68, 0x0A, 0x10, 0x00, 0x0B, 0x30, 0xFE, - 0x41, 0x30, 0x38, 0x38, 0x0A, 0x0B, 0x0A, 0x03, + 0x41, 0x30, 0x38, 0x33, 0x0A, 0x0B, 0x0A, 0x03, 0xA4, 0x41, 0x30, 0x30, 0x33, 0x0B, 0x50, 0x86, - 0x14, 0x44, 0x06, 0x41, 0x30, 0x39, 0x30, 0x02, + 0x14, 0x44, 0x06, 0x41, 0x30, 0x38, 0x35, 0x02, 0x70, 0x7D, 0x7B, 0x68, 0x0A, 0xFF, 0x00, 0x0C, 0x00, 0x50, 0x86, 0x01, 0x00, 0x60, 0x70, 0x7D, 0x7B, 0x68, 0x0C, 0x00, 0xFF, 0xFF, 0xFF, 0x00, @@ -237,424 +240,535 @@ UINT8 AlibSsdt[] = { 0x34, 0x0B, 0x04, 0x86, 0x61, 0x41, 0x30, 0x30, 0x34, 0x0B, 0x08, 0x86, 0x62, 0x41, 0x30, 0x30, 0x34, 0x0B, 0x50, 0x86, 0x69, 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0x67, 0x0A, 0x01, + 0x00, 0x41, 0x30, 0x36, 0x31, 0x70, 0x0A, 0x00, + 0x60, 0xA0, 0x0E, 0x94, 0x41, 0x30, 0x36, 0x30, + 0x41, 0x30, 0x36, 0x31, 0x70, 0x0A, 0x01, 0x60, + 0x7B, 0x41, 0x30, 0x35, 0x33, 0x68, 0x0A, 0x50, + 0x0A, 0x01, 0x61, 0xA4, 0x7B, 0x7F, 0x60, 0x61, + 0x00, 0x0A, 0x01, 0x00, 0x14, 0x49, 0x05, 0x41, + 0x30, 0x37, 0x35, 0x02, 0x70, 0x41, 0x30, 0x37, + 0x33, 0x68, 0x67, 0x70, 0x83, 0x88, 0x67, 0x0A, + 0x04, 0x00, 0x41, 0x30, 0x36, 0x35, 0x70, 0x7D, + 0x79, 0x83, 0x88, 0x67, 0x72, 0x0A, 0x05, 0x0A, + 0x01, 0x00, 0x00, 0x0A, 0x08, 0x00, 0x83, 0x88, + 0x67, 0x0A, 0x05, 0x00, 0x00, 0x41, 0x30, 0x36, + 0x34, 0x41, 0x30, 0x32, 0x38, 0x0A, 0x00, 0x0A, + 0xE0, 0x7D, 0x79, 0x41, 0x30, 0x36, 0x34, 0x0A, + 0x10, 0x00, 0x72, 0x0B, 0x00, 0x08, 0x77, 0x0B, + 0x00, 0x01, 0x41, 0x30, 0x36, 0x35, 0x00, 0x00, + 0x00, 0x80, 0x0A, 0x01, 0x00, 0x69, 0x08, 0x41, + 0x30, 0x38, 0x30, 0x11, 0x0A, 0x0A, 0x07, 0x00, + 0x01, 0x02, 0x04, 0x08, 0x0C, 0x10, 0x14, 0x4B, + 0x06, 0x41, 0x30, 0x37, 0x38, 0x02, 0xA0, 0x1E, + 0x93, 0x69, 0x0A, 0x00, 0x7B, 0x7A, 0x41, 0x30, + 0x35, 0x33, 0x68, 0x0A, 0xA2, 0x0A, 0x04, 0x00, + 0x0A, 0x07, 0x60, 0x70, 0x83, 0x88, 0x41, 0x30, + 0x38, 0x30, 0x60, 0x00, 0x61, 0xA1, 0x42, 0x04, + 0x70, 0x41, 0x30, 0x37, 0x33, 0x68, 0x67, 0x70, + 0x83, 0x88, 0x67, 0x0A, 0x00, 0x00, 0x41, 0x30, + 0x36, 0x30, 0x70, 0x83, 0x88, 0x67, 0x0A, 0x01, + 0x00, 0x41, 0x30, 0x36, 0x31, 0xA0, 0x14, 0x94, + 0x41, 0x30, 0x36, 0x30, 0x41, 0x30, 0x36, 0x31, + 0x74, 0x41, 0x30, 0x36, 0x30, 0x41, 0x30, 0x36, + 0x31, 0x61, 0xA1, 0x0B, 0x74, 0x41, 0x30, 0x36, + 0x31, 0x41, 0x30, 0x36, 0x30, 0x61, 0x75, 0x61, + 0xA4, 0x61, 0x14, 0x4C, 0x09, 0x41, 0x30, 0x37, + 0x37, 0x0C, 0x70, 0x41, 0x30, 0x37, 0x33, 0x68, + 0x67, 0x70, 0x69, 0x41, 0x30, 0x36, 0x32, 0x70, + 0x6A, 0x41, 0x30, 0x36, 0x33, 0x70, 0x7D, 0x79, + 0x83, 0x88, 0x67, 0x72, 0x0A, 0x05, 0x0A, 0x01, + 0x00, 0x00, 0x0A, 0x08, 0x00, 0x83, 0x88, 0x67, + 0x0A, 0x05, 0x00, 0x00, 0x41, 0x30, 0x36, 0x34, + 0xA0, 0x1A, 0x94, 0x41, 0x30, 0x36, 0x32, 0x41, + 0x30, 0x36, 0x33, 0x74, 0x41, 0x30, 0x36, 0x32, + 0x41, 0x30, 0x36, 0x33, 0x61, 0x70, 0x41, 0x30, + 0x36, 0x33, 0x62, 0xA1, 0x11, 0x74, 0x41, 0x30, + 0x36, 0x33, 0x41, 0x30, 0x36, 0x32, 0x61, 0x70, + 0x41, 0x30, 0x36, 0x32, 0x62, 0x79, 0x74, 0x79, + 0x0A, 0x01, 0x72, 0x61, 0x0A, 0x01, 0x00, 0x00, + 0x0A, 0x01, 0x00, 0x62, 0x63, 0x70, 0x80, 0x63, + 0x00, 0x64, 0xA0, 0x09, 0x93, 0x6B, 0x0A, 0x01, + 0x70, 0x0A, 0x00, 0x63, 0x41, 0x30, 0x32, 0x38, + 0x0A, 0x00, 0x0A, 0xE0, 0x7D, 0x79, 0x41, 0x30, + 0x36, 0x34, 0x0A, 0x10, 0x00, 0x0B, 0x23, 0x80, + 0x00, 0x64, 0x63, 0x5B, 0x21, 0x0A, 0x0A, 0x14, + 0x4B, 0x05, 0x41, 0x30, 0x30, 0x32, 0x02, 0x70, + 0x41, 0x30, 0x30, 0x33, 0x0B, 0x90, 0x84, 0x60, + 0xA0, 0x4A, 0x04, 0x92, 0x93, 0x7B, 0x60, 0x0A, + 0xF0, 0x00, 0x0A, 0x00, 0xA0, 0x12, 0x93, 0x68, + 0x0A, 0x02, 0x7B, 0x60, 0x0C, 0xA0, 0xFF, 0xFF, + 0xFF, 0x60, 0x7D, 0x60, 0x0A, 0xA0, 0x60, 0xA1, + 0x23, 0xA0, 0x12, 0x93, 0x69, 0x0A, 0x00, 0x7B, + 0x60, 0x0C, 0x60, 0xFF, 0xFF, 0xFF, 0x60, 0x7D, + 0x60, 0x0A, 0x60, 0x60, 0xA1, 0x0E, 0x7B, 0x60, + 0x0C, 0x20, 0xFF, 0xFF, 0xFF, 0x60, 0x7D, 0x60, + 0x0A, 0x20, 0x60, 0x41, 0x30, 0x30, 0x34, 0x0B, + 0x90, 0x84, 0x60, 0x14, 0x06, 0x41, 0x30, 0x30, + 0x35, 0x01, 0x08, 0x41, 0x44, 0x30, 0x42, 0x0A, + 0x00, 0x14, 0x44, 0x04, 0x41, 0x30, 0x30, 0x36, + 0x01, 0xA0, 0x3C, 0x93, 0x41, 0x44, 0x30, 0x42, + 0x0A, 0x01, 0x70, 0x7D, 0x79, 0x0A, 0x18, 0x0A, + 0x03, 0x00, 0x0A, 0x04, 0x00, 0x61, 0x70, 0x41, + 0x30, 0x30, 0x37, 0x61, 0x0B, 0x5C, 0x01, 0x62, + 0xA0, 0x0A, 0x93, 0x68, 0x0A, 0x00, 0x7D, 0x62, + 0x0A, 0x01, 0x62, 0xA1, 0x09, 0x7B, 0x62, 0x0C, + 0xFC, 0xFF, 0xFF, 0xFF, 0x62, 0x41, 0x30, 0x30, + 0x38, 0x61, 0x0B, 0x5C, 0x01, 0x62 }; #endif diff --git a/src/vendorcode/amd/agesa/f14/Proc/GNB/PCIe/Family/0x14/F14PcieComplexConfig.c b/src/vendorcode/amd/agesa/f14/Proc/GNB/PCIe/Family/0x14/F14PcieComplexConfig.c index c64fc4bd72..5d9153bdce 100644 --- a/src/vendorcode/amd/agesa/f14/Proc/GNB/PCIe/Family/0x14/F14PcieComplexConfig.c +++ b/src/vendorcode/amd/agesa/f14/Proc/GNB/PCIe/Family/0x14/F14PcieComplexConfig.c @@ -53,6 +53,7 @@ #include "amdlib.h" #include "Gnb.h" #include "GnbPcie.h" +#include "GnbPcieFamServices.h" #include GNB_MODULE_DEFINITIONS (GnbPcieConfig) #include "OntarioDefinitions.h" #include "OntarioComplexData.h" diff --git a/src/vendorcode/amd/agesa/f14/Proc/GNB/PCIe/Family/0x14/F14PcieComplexServices.c b/src/vendorcode/amd/agesa/f14/Proc/GNB/PCIe/Family/0x14/F14PcieComplexServices.c index 2e789aa4c9..0895c52d22 100644 --- a/src/vendorcode/amd/agesa/f14/Proc/GNB/PCIe/Family/0x14/F14PcieComplexServices.c +++ b/src/vendorcode/amd/agesa/f14/Proc/GNB/PCIe/Family/0x14/F14PcieComplexServices.c @@ -55,6 +55,8 @@ #include GNB_MODULE_DEFINITIONS (GnbPcieInitLibV1) #include GNB_MODULE_DEFINITIONS (GnbPcieConfig) #include "OntarioDefinitions.h" +#include "GnbPcieFamServices.h" +#include "PcieFamilyServices.h" #include "GnbRegistersON.h" #include "NbSmuLib.h" #include "Filecode.h" diff --git a/src/vendorcode/amd/agesa/f14/Proc/GNB/PCIe/Family/0x14/F14PciePhyServices.c b/src/vendorcode/amd/agesa/f14/Proc/GNB/PCIe/Family/0x14/F14PciePhyServices.c index cb35a59133..fc7d4609c7 100644 --- a/src/vendorcode/amd/agesa/f14/Proc/GNB/PCIe/Family/0x14/F14PciePhyServices.c +++ b/src/vendorcode/amd/agesa/f14/Proc/GNB/PCIe/Family/0x14/F14PciePhyServices.c @@ -73,6 +73,35 @@ *---------------------------------------------------------------------------------------- */ +AGESA_STATUS +PcieFmPhyLetPllPersonalityInit ( + IN PCIe_WRAPPER_CONFIG *Wrapper, + IN PCIe_PLATFORM_CONFIG *Pcie + ); + +VOID +PcieFmPhyChannelCharacteristic ( + IN PCIe_ENGINE_CONFIG *Engine, + IN PCIe_PLATFORM_CONFIG *Pcie + ); + +VOID +PcieFmAvertClockPickers ( + IN PCIe_WRAPPER_CONFIG *Wrapper, + IN PCIe_PLATFORM_CONFIG *Pcie + ); + +VOID +PcieFmPhyApplyGanging ( + IN PCIe_WRAPPER_CONFIG *Wrapper, + IN PCIe_PLATFORM_CONFIG *Pcie + ); + +VOID +PcieFmPifSetRxDetectPowerMode ( + IN PCIe_WRAPPER_CONFIG *Wrapper, + IN PCIe_PLATFORM_CONFIG *Pcie + ); /*----------------------------------------------------------------------------------------*/ /** diff --git a/src/vendorcode/amd/agesa/f14/Proc/GNB/PCIe/Family/0x14/F14PciePifServices.c b/src/vendorcode/amd/agesa/f14/Proc/GNB/PCIe/Family/0x14/F14PciePifServices.c index 31ef7c8980..fa1e62c5f3 100644 --- a/src/vendorcode/amd/agesa/f14/Proc/GNB/PCIe/Family/0x14/F14PciePifServices.c +++ b/src/vendorcode/amd/agesa/f14/Proc/GNB/PCIe/Family/0x14/F14PciePifServices.c @@ -54,6 +54,7 @@ #include "GnbPcie.h" #include GNB_MODULE_DEFINITIONS (GnbCommonLib) #include GNB_MODULE_DEFINITIONS (GnbPcieInitLibV1) +#include "PcieFamilyServices.h" #include "GnbRegistersON.h" #include "Filecode.h" #define FILECODE PROC_GNB_PCIE_FAMILY_0X14_F14PCIEPIFSERVICES_FILECODE diff --git a/src/vendorcode/amd/agesa/f14/Proc/GNB/PCIe/Family/0x14/F14PcieWrapperServices.c b/src/vendorcode/amd/agesa/f14/Proc/GNB/PCIe/Family/0x14/F14PcieWrapperServices.c index 88290b19cc..330a02e3d0 100644 --- a/src/vendorcode/amd/agesa/f14/Proc/GNB/PCIe/Family/0x14/F14PcieWrapperServices.c +++ b/src/vendorcode/amd/agesa/f14/Proc/GNB/PCIe/Family/0x14/F14PcieWrapperServices.c @@ -9,7 +9,7 @@ * @xrefitem bom "File Content Label" "Release Content" * @e project: AGESA * @e sub-project: GNB - * @e \$Revision: 39275 $ @e \$Date: 2010-10-09 08:22:05 +0800 (Sat, 09 Oct 2010) $ + * @e \$Revision: 44325 $ @e \$Date: 2010-12-22 03:29:53 -0700 (Wed, 22 Dec 2010) $ * */ /* @@ -56,6 +56,7 @@ #include GNB_MODULE_DEFINITIONS (GnbCommonLib) #include GNB_MODULE_DEFINITIONS (GnbPcieInitLibV1) #include "PcieMiscLib.h" +#include "GnbPcieFamServices.h" #include "OntarioDefinitions.h" #include "GnbRegistersON.h" #include "NbSmuLib.h" @@ -97,12 +98,58 @@ PcieFmExecuteNativeGen1Reconfig ( IN PCIe_PLATFORM_CONFIG *Pcie ); +AGESA_STATUS +PcieOnGetGppConfigurationValue ( + IN UINT64 ConfigurationSignature, + OUT UINT8 *ConfigurationValue + ); + /*---------------------------------------------------------------------------------------- * T A B L E S *---------------------------------------------------------------------------------------- */ PCIE_HOST_REGISTER_ENTRY PcieInitTable [] = { { + PHY_SPACE (0, 0, D0F0xE4_PHY_6440_ADDRESS), + D0F0xE4_PHY_6440_RxInCalForce_MASK, + 0x1 << D0F0xE4_PHY_6440_RxInCalForce_OFFSET + }, + { + PHY_SPACE (0, 0, D0F0xE4_PHY_6480_ADDRESS), + D0F0xE4_PHY_6480_RxInCalForce_MASK, + 0x1 << D0F0xE4_PHY_6480_RxInCalForce_OFFSET + }, + { + PHY_SPACE (0, 0, D0F0xE4_PHY_6500_ADDRESS), + D0F0xE4_PHY_6500_RxInCalForce_MASK, + 0x1 << D0F0xE4_PHY_6500_RxInCalForce_OFFSET + }, + { + PHY_SPACE (0, 0, D0F0xE4_PHY_6600_ADDRESS), + D0F0xE4_PHY_6600_RxInCalForce_MASK, + 0x1 << D0F0xE4_PHY_6600_RxInCalForce_OFFSET + }, + { + PHY_SPACE (0, 0, D0F0xE4_PHY_6840_ADDRESS), + D0F0xE4_PHY_6840_RxInCalForce_MASK, + 0x1 << D0F0xE4_PHY_6840_RxInCalForce_OFFSET + }, + { + PHY_SPACE (0, 0, D0F0xE4_PHY_6880_ADDRESS), + D0F0xE4_PHY_6880_RxInCalForce_MASK, + 0x1 << D0F0xE4_PHY_6880_RxInCalForce_OFFSET + }, + { + PHY_SPACE (0, 0, D0F0xE4_PHY_6900_ADDRESS), + D0F0xE4_PHY_6900_RxInCalForce_MASK, + 0x1 << D0F0xE4_PHY_6900_RxInCalForce_OFFSET + }, + { + PHY_SPACE (0, 0, D0F0xE4_PHY_6A00_ADDRESS), + D0F0xE4_PHY_6A00_RxInCalForce_MASK, + 0x1 << D0F0xE4_PHY_6A00_RxInCalForce_OFFSET + }, + { WRAP_SPACE (0, D0F0xE4_WRAP_8016_ADDRESS), D0F0xE4_WRAP_8016_CalibAckLatency_MASK, 0 @@ -168,22 +215,22 @@ PcieFmConfigureEnginesLaneAllocation ( CONST UINT8 GppLaneConfigurationTable [][NUMBER_OF_GPP_PORTS * 2] = { //4 5 6 7 8 (SB) - 4, 7, UNUSED_LANE_ID, UNUSED_LANE_ID, UNUSED_LANE_ID, UNUSED_LANE_ID, UNUSED_LANE_ID, UNUSED_LANE_ID, 0, 3, - 4, 5, 6, 7, UNUSED_LANE_ID, UNUSED_LANE_ID, UNUSED_LANE_ID, UNUSED_LANE_ID, 0, 3, - 4, 5, UNUSED_LANE_ID, UNUSED_LANE_ID, 6, 7, UNUSED_LANE_ID, UNUSED_LANE_ID, 0, 3, - 4, 5, 6, 6, 7, 7, UNUSED_LANE_ID, UNUSED_LANE_ID, 0, 3, - 4, 5, UNUSED_LANE_ID, UNUSED_LANE_ID, 6, 6, 7, 7, 0, 3, - 4, 4, 5, 5, 6, 6, 7, 7, 0, 3 + {4, 7, UNUSED_LANE_ID, UNUSED_LANE_ID, UNUSED_LANE_ID, UNUSED_LANE_ID, UNUSED_LANE_ID, UNUSED_LANE_ID, 0, 3}, + {4, 5, 6, 7, UNUSED_LANE_ID, UNUSED_LANE_ID, UNUSED_LANE_ID, UNUSED_LANE_ID, 0, 3}, + {4, 5, UNUSED_LANE_ID, UNUSED_LANE_ID, 6, 7, UNUSED_LANE_ID, UNUSED_LANE_ID, 0, 3}, + {4, 5, 6, 6, 7, 7, UNUSED_LANE_ID, UNUSED_LANE_ID, 0, 3}, + {4, 5, UNUSED_LANE_ID, UNUSED_LANE_ID, 6, 6, 7, 7, 0, 3}, + {4, 4, 5, 5, 6, 6, 7, 7, 0, 3} }; CONST UINT8 GppPortIdConfigurationTable [][NUMBER_OF_GPP_PORTS] = { //4 5 6 7 8 (SB) - 1, 2, 3, 4, 0, - 1, 2, 3, 4, 0, - 1, 3, 2, 4, 0, - 1, 2, 3, 4, 0, - 1, 4, 2, 3, 0, - 1, 2, 3, 4, 0 + {1, 2, 3, 4, 0}, + {1, 2, 3, 4, 0}, + {1, 3, 2, 4, 0}, + {1, 2, 3, 4, 0}, + {1, 4, 2, 3, 0}, + {1, 2, 3, 4, 0} }; /*----------------------------------------------------------------------------------------*/ @@ -227,7 +274,7 @@ PcieOnConfigureGppEnginesLaneAllocation ( CONST UINT8 DdiLaneConfigurationTable [][NUMBER_OF_DDIS * 2] = { - 0, 3, 4, 7, 8, 11 + {0, 3, 4, 7, 8, 11} }; /*----------------------------------------------------------------------------------------*/ @@ -391,7 +438,7 @@ PcieFmGetLinkSpeedCap ( LinkSpeedCapability = Engine->Type.Port.PortData.LinkSpeedCapability; } if ((Flags & PCIE_PORT_GEN_CAP_BOOT) != 0) { - if (Pcie->PsppPolicy == PsppBalanceLow) { + if (Pcie->PsppPolicy == PsppBalanceLow || Engine->Type.Port.PortData.MiscControls.LinkSafeMode == PcieGen1) { LinkSpeedCapability = PcieGen1; } } @@ -491,17 +538,17 @@ PcieFmDebugGetCoreConfigurationString ( { switch (ConfigurationValue) { case 4: - return "1x4, 4x1"; + return (CONST CHAR8*)"1x4, 4x1"; case 3: - return "1x4, 1x2, 2x1"; + return (CONST CHAR8*)"1x4, 1x2, 2x1"; case 2: - return "1x4, 2x2"; + return (CONST CHAR8*)"1x4, 2x2"; case 1: - return "1x4, 1x4"; + return (CONST CHAR8*)"1x4, 1x4"; default: break; } - return " !!! Something Wrong !!!"; + return (CONST CHAR8*)" !!! Something Wrong !!!"; } /*----------------------------------------------------------------------------------------*/ @@ -521,13 +568,13 @@ PcieFmDebugGetWrapperNameString ( { switch (Wrapper->WrapId) { case GPP_WRAP_ID: - return "GPPSB"; + return (CONST CHAR8*)"GPPSB"; case DDI_WRAP_ID: - return "Virtual DDI"; + return (CONST CHAR8*)"Virtual DDI"; default: break; } - return " !!! Something Wrong !!!"; + return (CONST CHAR8*)" !!! Something Wrong !!!"; } /*----------------------------------------------------------------------------------------*/ @@ -546,17 +593,17 @@ PcieFmDebugGetHostRegAddressSpaceString ( { switch (AddressFrame) { case 0x130: - return "GPP WRAP"; + return (CONST CHAR8*)"GPP WRAP"; case 0x110: - return "GPP PIF0"; + return (CONST CHAR8*)"GPP PIF0"; case 0x120: - return "GPP PHY0"; + return (CONST CHAR8*)"GPP PHY0"; case 0x101: - return "GPP CORE"; + return (CONST CHAR8*)"GPP CORE"; default: break; } - return " !!! Something Wrong !!!"; + return (CONST CHAR8*)" !!! Something Wrong !!!"; } diff --git a/src/vendorcode/amd/agesa/f14/Proc/GNB/PCIe/Family/0x14/OntarioComplexData.h b/src/vendorcode/amd/agesa/f14/Proc/GNB/PCIe/Family/0x14/OntarioComplexData.h index b9f9a04d0f..4aee593547 100644 --- a/src/vendorcode/amd/agesa/f14/Proc/GNB/PCIe/Family/0x14/OntarioComplexData.h +++ b/src/vendorcode/amd/agesa/f14/Proc/GNB/PCIe/Family/0x14/OntarioComplexData.h @@ -52,7 +52,7 @@ F14_COMPLEX_CONFIG ComplexData = { { DESCRIPTOR_TERMINATE_LIST, {0}, - offsetof (F14_COMPLEX_CONFIG, GppWrapper), + (VOID *)(offsetof (F14_COMPLEX_CONFIG, GppWrapper)), NULL }, //Gpp Wrapper @@ -72,9 +72,9 @@ F14_COMPLEX_CONFIG ComplexData = { 1, //TxclkGatingPllPowerDown 1 //PllOffInL1 }, - offsetof (F14_COMPLEX_CONFIG, Port4), - offsetof (F14_COMPLEX_CONFIG, Silicon), - offsetof (F14_COMPLEX_CONFIG, FmGppWrapper) + (VOID *)(offsetof (F14_COMPLEX_CONFIG, Port4)), + (VOID *)(offsetof (F14_COMPLEX_CONFIG, Silicon)), + (VOID *)(offsetof (F14_COMPLEX_CONFIG, FmGppWrapper)) }, //Virtual DDI Wrapper { @@ -93,14 +93,14 @@ F14_COMPLEX_CONFIG ComplexData = { 1, //TxclkGatingPllPowerDown 0 //PllOffInL1 }, - offsetof (F14_COMPLEX_CONFIG, Dpa), - offsetof (F14_COMPLEX_CONFIG, Silicon), + (VOID *)(offsetof (F14_COMPLEX_CONFIG, Dpa)), + (VOID *)(offsetof (F14_COMPLEX_CONFIG, Silicon)), NULL }, //Port 4 { DESCRIPTOR_PCIE_ENGINE, - offsetof (F14_COMPLEX_CONFIG, GppWrapper), + (VOID *)(offsetof (F14_COMPLEX_CONFIG, GppWrapper)), { PciePortEngine, 4, 4}, 0, //Initialization Status 0xFF, //Scratch @@ -113,7 +113,7 @@ F14_COMPLEX_CONFIG ComplexData = { 0, GPP_CORE_ID, 1, - 0, + {0}, FALSE, LinkStateResetExit }, @@ -122,7 +122,7 @@ F14_COMPLEX_CONFIG ComplexData = { //Port 5 { DESCRIPTOR_PCIE_ENGINE, - offsetof (F14_COMPLEX_CONFIG, GppWrapper), + (VOID *)(offsetof (F14_COMPLEX_CONFIG, GppWrapper)), { PciePortEngine, 5, 5}, 0, //Initialization Status 0xFF, //Scratch @@ -135,7 +135,7 @@ F14_COMPLEX_CONFIG ComplexData = { 0, GPP_CORE_ID, 2, - 0, + {0}, FALSE, LinkStateResetExit }, @@ -144,7 +144,7 @@ F14_COMPLEX_CONFIG ComplexData = { //Port 6 { DESCRIPTOR_PCIE_ENGINE, - offsetof (F14_COMPLEX_CONFIG, GppWrapper), + (VOID *)(offsetof (F14_COMPLEX_CONFIG, GppWrapper)), { PciePortEngine, 6, 6 }, 0, //Initialization Status 0xFF, //Scratch @@ -157,7 +157,7 @@ F14_COMPLEX_CONFIG ComplexData = { 0, GPP_CORE_ID, 3, - 0, + {0}, FALSE, LinkStateResetExit }, @@ -166,7 +166,7 @@ F14_COMPLEX_CONFIG ComplexData = { //Port 7 { DESCRIPTOR_PCIE_ENGINE, - offsetof (F14_COMPLEX_CONFIG, GppWrapper), + (VOID *)(offsetof (F14_COMPLEX_CONFIG, GppWrapper)), { PciePortEngine, 7, 7 }, 0, //Initialization Status 0xFF, //Scratch @@ -179,7 +179,7 @@ F14_COMPLEX_CONFIG ComplexData = { 0, GPP_CORE_ID, 4, - 0, + {0}, FALSE, LinkStateResetExit }, @@ -188,7 +188,7 @@ F14_COMPLEX_CONFIG ComplexData = { //Port 8 { DESCRIPTOR_PCIE_ENGINE | DESCRIPTOR_TERMINATE_LIST, - offsetof (F14_COMPLEX_CONFIG, GppWrapper), + (VOID *)(offsetof (F14_COMPLEX_CONFIG, GppWrapper)), { PciePortEngine, 0, 3 }, 0, //Initialization Status 0xFF, //Scratch @@ -201,7 +201,7 @@ F14_COMPLEX_CONFIG ComplexData = { 0, GPP_CORE_ID, 0, - MAKE_SBDFO (0, 0, 8, 0, 0), + {MAKE_SBDFO (0, 0, 8, 0, 0)}, TRUE, LinkStateTrainingSuccess }, @@ -210,7 +210,7 @@ F14_COMPLEX_CONFIG ComplexData = { //Virtual DpA { DESCRIPTOR_DDI_ENGINE | DESCRIPTOR_VIRTUAL, - offsetof (F14_COMPLEX_CONFIG, DdiWrapper), + (VOID *)(offsetof (F14_COMPLEX_CONFIG, DdiWrapper)), {PcieDdiEngine}, 0, //Initialization Status 0xFF, //Scratch @@ -218,7 +218,7 @@ F14_COMPLEX_CONFIG ComplexData = { //Virtual DpB { DESCRIPTOR_DDI_ENGINE | DESCRIPTOR_VIRTUAL, - offsetof (F14_COMPLEX_CONFIG, DdiWrapper), + (VOID *)(offsetof (F14_COMPLEX_CONFIG, DdiWrapper)), {PcieDdiEngine}, 0, //Initialization Status 0xFF, //Scratch @@ -226,7 +226,7 @@ F14_COMPLEX_CONFIG ComplexData = { //Virtual VGA { DESCRIPTOR_DDI_ENGINE | DESCRIPTOR_VIRTUAL | DESCRIPTOR_TERMINATE_LIST, - offsetof (F14_COMPLEX_CONFIG, DdiWrapper), + (VOID *)(offsetof (F14_COMPLEX_CONFIG, DdiWrapper)), {PcieDdiEngine}, 0, //Initialization Status 0xFF, //Scratch diff --git a/src/vendorcode/amd/agesa/f14/Proc/GNB/PCIe/PcieInit.c b/src/vendorcode/amd/agesa/f14/Proc/GNB/PCIe/PcieInit.c index 8b49ad8973..3c2712612a 100644 --- a/src/vendorcode/amd/agesa/f14/Proc/GNB/PCIe/PcieInit.c +++ b/src/vendorcode/amd/agesa/f14/Proc/GNB/PCIe/PcieInit.c @@ -80,6 +80,32 @@ *---------------------------------------------------------------------------------------- */ +VOID +PcieCommonCoreInit ( + IN PCIe_WRAPPER_CONFIG *Wrapper, + IN PCIe_PLATFORM_CONFIG *Pcie + ); + +AGESA_STATUS +PcieInitSrbmCallback ( + IN PCIe_WRAPPER_CONFIG *Wrapper, + IN OUT VOID *Buffer, + IN PCIe_PLATFORM_CONFIG *Pcie + ); + +AGESA_STATUS +PcieInitCallback ( + IN PCIe_WRAPPER_CONFIG *Wrapper, + IN OUT VOID *Buffer, + IN PCIe_PLATFORM_CONFIG *Pcie + ); + +AGESA_STATUS +PciePostInitCallback ( + IN PCIe_WRAPPER_CONFIG *Wrapper, + IN OUT VOID *Buffer, + IN PCIe_PLATFORM_CONFIG *Pcie + ); /*----------------------------------------------------------------------------------------*/ /** diff --git a/src/vendorcode/amd/agesa/f14/Proc/GNB/PCIe/PcieInitAtEnv.h b/src/vendorcode/amd/agesa/f14/Proc/GNB/PCIe/PcieInitAtEnv.h index 1e1765f1e4..75157dcd13 100644 --- a/src/vendorcode/amd/agesa/f14/Proc/GNB/PCIe/PcieInitAtEnv.h +++ b/src/vendorcode/amd/agesa/f14/Proc/GNB/PCIe/PcieInitAtEnv.h @@ -44,8 +44,8 @@ * */ -#ifndef _PCIEINITATPOST_H_ -#define _PCIEINITATPOST_H_ +#ifndef _PCIEINITATENV_H_ +#define _PCIEINITATENV_H_ AGESA_STATUS PcieInitAtEnv ( diff --git a/src/vendorcode/amd/agesa/f14/Proc/GNB/PCIe/PcieInitAtPost.c b/src/vendorcode/amd/agesa/f14/Proc/GNB/PCIe/PcieInitAtPost.c index 0ee02f4614..4d6e4f0a91 100644 --- a/src/vendorcode/amd/agesa/f14/Proc/GNB/PCIe/PcieInitAtPost.c +++ b/src/vendorcode/amd/agesa/f14/Proc/GNB/PCIe/PcieInitAtPost.c @@ -9,7 +9,7 @@ * @xrefitem bom "File Content Label" "Release Content" * @e project: AGESA * @e sub-project: GNB - * @e \$Revision: 39275 $ @e \$Date: 2010-10-09 08:22:05 +0800 (Sat, 09 Oct 2010) $ + * @e \$Revision: 44325 $ @e \$Date: 2010-12-22 03:29:53 -0700 (Wed, 22 Dec 2010) $ * */ /* @@ -74,6 +74,65 @@ * P R O T O T Y P E S O F L O C A L F U N C T I O N S *---------------------------------------------------------------------------------------- */ +AGESA_STATUS +PcieInitAtPostEarly ( + IN AMD_CONFIG_PARAMS *StdHeader + ); + +AGESA_STATUS +PcieInitAtPost ( + IN AMD_CONFIG_PARAMS *StdHeader + ); + +AGESA_STATUS +PcieInitAtPostS3 ( + IN AMD_CONFIG_PARAMS *StdHeader + ); + +VOID +PcieLateRestoreS3Script ( + IN AMD_CONFIG_PARAMS *StdHeader, + IN UINT16 ContextLength, + IN VOID* Context + ); + +/*----------------------------------------------------------------------------------------*/ +/** + * PCIe Post Init prior DRAM init + * + * + * + * @param[in] StdHeader Standard configuration header + * @retval AGESA_STATUS + */ +AGESA_STATUS +PcieInitAtPostEarly ( + IN AMD_CONFIG_PARAMS *StdHeader + ) +{ + AGESA_STATUS AgesaStatus; + AGESA_STATUS Status; + PCIe_PLATFORM_CONFIG *Pcie; + IDS_HDT_CONSOLE (GNB_TRACE, "PcieInitAtPostEarly Enter\n"); + AgesaStatus = AGESA_SUCCESS; + Status = PcieLocateConfigurationData (StdHeader, &Pcie); + AGESA_STATUS_UPDATE (Status, AgesaStatus); + if (Status == AGESA_SUCCESS) { + PciePortsVisibilityControl (UnhidePorts, Pcie); + + Status = PciePortPostEarlyInit (Pcie); + AGESA_STATUS_UPDATE (Status, AgesaStatus); + ASSERT (Status == AGESA_SUCCESS); + + Status = PcieTraining (Pcie); + AGESA_STATUS_UPDATE (Status, AgesaStatus); + ASSERT (Status == AGESA_SUCCESS); + + PciePortsVisibilityControl (HidePorts, Pcie); + } + IDS_HDT_CONSOLE (GNB_TRACE, "PcieInitAtPostEarly Exit [0x%x]\n", AgesaStatus); + return AgesaStatus; +} /*----------------------------------------------------------------------------------------*/ /** @@ -120,6 +179,52 @@ PcieInitAtPost ( /*----------------------------------------------------------------------------------------*/ /** + * PCIe Post Init + * + * + * + * @param[in] StdHeader Standard configuration header + * @retval AGESA_STATUS + */ +AGESA_STATUS +PcieInitAtPostS3 ( + IN AMD_CONFIG_PARAMS *StdHeader + ) +{ + AGESA_STATUS AgesaStatus; + AGESA_STATUS Status; + PCIe_PLATFORM_CONFIG *Pcie; + IDS_HDT_CONSOLE (GNB_TRACE, "PcieInitAtPostS3 Enter\n"); + AgesaStatus = AGESA_SUCCESS; + Status = PcieLocateConfigurationData (StdHeader, &Pcie); + AGESA_STATUS_UPDATE (Status, AgesaStatus); + if (Status == AGESA_SUCCESS) { + PciePortsVisibilityControl (UnhidePorts, Pcie); + + Status = PciePostInit (Pcie); + AGESA_STATUS_UPDATE (Status, AgesaStatus); + ASSERT (Status == AGESA_SUCCESS); + + if (Pcie->TrainingAlgorithm == PcieTrainingDistributed) { + Status = PciePortPostS3Init (Pcie); + } else { + Status = PciePortPostInit (Pcie); + } + AGESA_STATUS_UPDATE (Status, AgesaStatus); + ASSERT (Status == AGESA_SUCCESS); + + Status = PcieTraining (Pcie); + AGESA_STATUS_UPDATE (Status, AgesaStatus); + ASSERT (Status == AGESA_SUCCESS); + + PciePortsVisibilityControl (HidePorts, Pcie); + } + IDS_HDT_CONSOLE (GNB_TRACE, "PcieInitAtPostS3 Exit [0x%x]\n", AgesaStatus); + return AgesaStatus; +} + +/*----------------------------------------------------------------------------------------*/ +/** * PCIe S3 restore * * @@ -135,5 +240,5 @@ PcieLateRestoreS3Script ( IN VOID* Context ) { - PcieInitAtPost (StdHeader); + PcieInitAtPostS3 (StdHeader); } diff --git a/src/vendorcode/amd/agesa/f14/Proc/GNB/PCIe/PcieLateInit.c b/src/vendorcode/amd/agesa/f14/Proc/GNB/PCIe/PcieLateInit.c index a979511279..d5e91895de 100644 --- a/src/vendorcode/amd/agesa/f14/Proc/GNB/PCIe/PcieLateInit.c +++ b/src/vendorcode/amd/agesa/f14/Proc/GNB/PCIe/PcieLateInit.c @@ -78,6 +78,18 @@ *---------------------------------------------------------------------------------------- */ +VOID +PciePwrPowerDownPllInL1 ( + IN PCIe_WRAPPER_CONFIG *Wrapper, + IN PCIe_PLATFORM_CONFIG *Pcie + ); + +AGESA_STATUS +PcieLateInitCallback ( + IN PCIe_WRAPPER_CONFIG *Wrapper, + IN OUT VOID *Buffer, + IN PCIe_PLATFORM_CONFIG *Pcie + ); /*----------------------------------------------------------------------------------------*/ /** diff --git a/src/vendorcode/amd/agesa/f14/Proc/GNB/PCIe/PcieMiscLib.c b/src/vendorcode/amd/agesa/f14/Proc/GNB/PCIe/PcieMiscLib.c index 97eb370759..e5ae7a683c 100644 --- a/src/vendorcode/amd/agesa/f14/Proc/GNB/PCIe/PcieMiscLib.c +++ b/src/vendorcode/amd/agesa/f14/Proc/GNB/PCIe/PcieMiscLib.c @@ -56,6 +56,7 @@ #include GNB_MODULE_DEFINITIONS (GnbCommonLib) #include GNB_MODULE_DEFINITIONS (GnbPcieInitLibV1) #include GNB_MODULE_DEFINITIONS (GnbPcieConfig) +#include "PcieMiscLib.h" #include "GnbRegistersON.h" #include "Filecode.h" #define FILECODE PROC_GNB_PCIE_PCIEMISCLIB_FILECODE diff --git a/src/vendorcode/amd/agesa/f14/Proc/GNB/PCIe/PciePortInit.c b/src/vendorcode/amd/agesa/f14/Proc/GNB/PCIe/PciePortInit.c index 2802ba21f7..567c2fad1a 100644 --- a/src/vendorcode/amd/agesa/f14/Proc/GNB/PCIe/PciePortInit.c +++ b/src/vendorcode/amd/agesa/f14/Proc/GNB/PCIe/PciePortInit.c @@ -9,7 +9,7 @@ * @xrefitem bom "File Content Label" "Release Content" * @e project: AGESA * @e sub-project: GNB - * @e \$Revision: 39275 $ @e \$Date: 2010-10-09 08:22:05 +0800 (Sat, 09 Oct 2010) $ + * @e \$Revision: 44325 $ @e \$Date: 2010-12-22 03:29:53 -0700 (Wed, 22 Dec 2010) $ * */ /* @@ -58,6 +58,7 @@ #include GNB_MODULE_DEFINITIONS (GnbPcieInitLibV1) #include GNB_MODULE_DEFINITIONS (GnbPcieConfig) #include GNB_MODULE_DEFINITIONS (GnbPcieTrainingV1) +#include "PciePortInit.h" #include "GnbRegistersON.h" #include "Filecode.h" #define FILECODE PROC_GNB_PCIE_PCIEPORTINIT_FILECODE @@ -156,6 +157,7 @@ PciePortInitCallback ( ASSERT (Engine->Type.Port.IsSB == FALSE); PcieTrainingSetPortState (Engine, LinkStateDeviceNotPresent, FALSE, Pcie); } + // Train port that forced to compliance in last stage of training if (Engine->Type.Port.PortData.MiscControls.LinkComplianceMode == 0x1) { PcieTrainingSetPortState (Engine, LinkStateTrainingCompleted, FALSE, Pcie); } @@ -180,6 +182,10 @@ PciePortInit ( { AGESA_STATUS Status; Status = AGESA_SUCCESS; + // Leave all device in Presence Detect Presence state for distributed training will be completed at PciePortPostEarlyInit + if (Pcie->TrainingAlgorithm == PcieTrainingDistributed) { + Pcie->TrainingExitState = LinkStateResetExit; + } PcieConfigRunProcForAllEngines ( DESCRIPTOR_ALLOCATED | DESCRIPTOR_PCIE_ENGINE, PciePortInitCallback, @@ -217,10 +223,12 @@ PciePortPostInitCallback ( } LinkSpeedCapability = PcieFmGetLinkSpeedCap (PCIE_PORT_GEN_CAP_BOOT, Engine, Pcie); PcieSetLinkSpeedCap (LinkSpeedCapability, Engine, Pcie); + // Retrain only present port to Gen2 if (PcieConfigCheckPortStatus (Engine, INIT_STATUS_PCIE_TRAINING_SUCCESS) && (LinkSpeedCapability > PcieGen1) && !Engine->Type.Port.IsSB) { PcieTrainingSetPortState (Engine, LinkStateRetrain, FALSE, Pcie); PcieConfigUpdatePortStatus (Engine, 0, INIT_STATUS_PCIE_TRAINING_SUCCESS); } + // Train ports forced to compliance if (Engine->Type.Port.PortData.MiscControls.LinkComplianceMode == 0x1) { PcieForceCompliance (Engine, Pcie); PcieTrainingSetPortState (Engine, LinkStateResetExit, FALSE, Pcie); @@ -254,3 +262,101 @@ PciePortPostInit ( ); return Status; } + +/*----------------------------------------------------------------------------------------*/ +/** + * Callback to init various features on all ports on S3 resume path + * + * + * + * + * @param[in] Engine Pointer to engine config descriptor + * @param[in, out] Buffer Not used + * @param[in] Pcie Pointer to global PCIe configuration + * + */ + +VOID +STATIC +PciePortPostS3InitCallback ( + IN PCIe_ENGINE_CONFIG *Engine, + IN OUT VOID *Buffer, + IN PCIe_PLATFORM_CONFIG *Pcie + ) +{ + PCIE_LINK_SPEED_CAP LinkSpeedCapability; + ASSERT (Engine->EngineData.EngineType == PciePortEngine); + LinkSpeedCapability = PcieFmGetLinkSpeedCap (PCIE_PORT_GEN_CAP_BOOT, Engine, Pcie); + PcieSetLinkSpeedCap (LinkSpeedCapability, Engine, Pcie); + if (Engine->Type.Port.PortData.MiscControls.LinkSafeMode == PcieGen1) { + PcieLinkSafeMode (Engine, Pcie); + } + if (Engine->Type.Port.PortData.MiscControls.LinkComplianceMode == 0x1) { + PcieForceCompliance (Engine, Pcie); + } + if (!Engine->Type.Port.IsSB) { + if ((PcieConfigCheckPortStatus (Engine, INIT_STATUS_PCIE_TRAINING_SUCCESS) || + ((Engine->Type.Port.PortData.LinkHotplug != HotplugDisabled) && (Engine->Type.Port.PortData.LinkHotplug != HotplugInboard)) || + (Engine->Type.Port.PortData.MiscControls.LinkComplianceMode == 0x1))) { + PcieTrainingSetPortState (Engine, LinkStateResetExit, FALSE, Pcie); + } else { + PcieTrainingSetPortState (Engine, LinkStateDeviceNotPresent, FALSE, Pcie); + } + PcieConfigUpdatePortStatus (Engine, 0, INIT_STATUS_PCIE_TRAINING_SUCCESS); + } else { + PcieTrainingSetPortState (Engine, LinkStateTrainingSuccess, FALSE, Pcie); + } +} +/*----------------------------------------------------------------------------------------*/ +/** + * Init port on S3 resume during destributed training + * + * + * + * + * @param[in] Pcie Pointer to global PCIe configuration + * @retval AGESA_STATUS + * + */ + +AGESA_STATUS +PciePortPostS3Init ( + IN PCIe_PLATFORM_CONFIG *Pcie + ) +{ + AGESA_STATUS Status; + Status = AGESA_SUCCESS; + PcieConfigRunProcForAllEngines ( + DESCRIPTOR_ALLOCATED | DESCRIPTOR_PCIE_ENGINE, + PciePortPostS3InitCallback, + NULL, + Pcie + ); + return Status; +} + +/*----------------------------------------------------------------------------------------*/ +/** + * Master procedure to init various features on all active ports + * + * + * + * + * @param[in] Pcie Pointer to global PCIe configuration + * @retval AGESA_STATUS + * + */ + +AGESA_STATUS +PciePortPostEarlyInit ( + IN PCIe_PLATFORM_CONFIG *Pcie + ) +{ + AGESA_STATUS Status; + Status = AGESA_SUCCESS; + // Distributed Training started at PciePortInit complete it now to get access to PCIe devices + if (Pcie->TrainingAlgorithm == PcieTrainingDistributed) { + Pcie->TrainingExitState = LinkStateTrainingCompleted; + } + return Status; +} diff --git a/src/vendorcode/amd/agesa/f14/Proc/GNB/PCIe/PciePortInit.h b/src/vendorcode/amd/agesa/f14/Proc/GNB/PCIe/PciePortInit.h index 6e65c8d1c9..6d26a4a7a7 100644 --- a/src/vendorcode/amd/agesa/f14/Proc/GNB/PCIe/PciePortInit.h +++ b/src/vendorcode/amd/agesa/f14/Proc/GNB/PCIe/PciePortInit.h @@ -9,7 +9,7 @@ * @xrefitem bom "File Content Label" "Release Content" * @e project: AGESA * @e sub-project: GNB - * @e \$Revision: 39275 $ @e \$Date: 2010-10-09 08:22:05 +0800 (Sat, 09 Oct 2010) $ + * @e \$Revision: 44325 $ @e \$Date: 2010-12-22 03:29:53 -0700 (Wed, 22 Dec 2010) $ * */ /* @@ -57,6 +57,15 @@ PciePortPostInit ( IN PCIe_PLATFORM_CONFIG *Pcie ); +AGESA_STATUS +PciePortPostEarlyInit ( + IN PCIe_PLATFORM_CONFIG *Pcie + ); + +AGESA_STATUS +PciePortPostS3Init ( + IN PCIe_PLATFORM_CONFIG *Pcie + ); #endif diff --git a/src/vendorcode/amd/agesa/f14/Proc/GNB/PCIe/PciePortLateInit.c b/src/vendorcode/amd/agesa/f14/Proc/GNB/PCIe/PciePortLateInit.c index e3a2b5ab21..27bf2934e1 100644 --- a/src/vendorcode/amd/agesa/f14/Proc/GNB/PCIe/PciePortLateInit.c +++ b/src/vendorcode/amd/agesa/f14/Proc/GNB/PCIe/PciePortLateInit.c @@ -77,6 +77,18 @@ *---------------------------------------------------------------------------------------- */ +VOID +PcieSlotPowerLimit ( + IN PCIe_ENGINE_CONFIG *Engine, + IN PCIe_PLATFORM_CONFIG *Pcie + ); + +AGESA_STATUS +PciePortLateInit ( + IN PCIe_PLATFORM_CONFIG *Pcie + ); + + PCIE_PORT_REGISTER_ENTRY PortLateInitTable [] = { { DxF0xE4_xA2_ADDRESS, diff --git a/src/vendorcode/amd/agesa/f14/Proc/HT/Fam14/htNbFam14.c b/src/vendorcode/amd/agesa/f14/Proc/HT/Fam14/htNbFam14.c index 97f4e0d4a0..baf39bd9e1 100644 --- a/src/vendorcode/amd/agesa/f14/Proc/HT/Fam14/htNbFam14.c +++ b/src/vendorcode/amd/agesa/f14/Proc/HT/Fam14/htNbFam14.c @@ -7,7 +7,7 @@ * @xrefitem bom "File Content Label" "Release Content" * @e project: AGESA * @e sub-project: HyperTransport - * @e \$Revision: 34897 $ @e \$Date: 2010-07-14 10:07:10 +0800 (Wed, 14 Jul 2010) $ + * @e \$Revision: 44325 $ @e \$Date: 2010-12-22 03:29:53 -0700 (Wed, 22 Dec 2010) $ * */ /* @@ -128,8 +128,7 @@ CONST NORTHBRIDGE ROMDATA HtFam14Nb = (PF_MAKE_LINK_BASE)CommonReturnZero32, (PF_GET_MODULE_INFO)CommonVoid, (PF_POST_MAILBOX)CommonVoid, - //(PF_RETRIEVE_MAILBOX)CommonReturnZero32, - Fam14RetrieveMailbox, + (PF_RETRIEVE_MAILBOX)CommonReturnZero32, (PF_GET_SOCKET)CommonReturnZero8, (PF_GET_ENABLED_COMPUTE_UNITS)CommonReturnZero8, (PF_GET_DUALCORE_COMPUTE_UNITS)CommonReturnZero8, diff --git a/src/vendorcode/amd/agesa/f14/Proc/HT/Fam14/htNbUtilitiesFam14.c b/src/vendorcode/amd/agesa/f14/Proc/HT/Fam14/htNbUtilitiesFam14.c index b780b0b75f..f6475c4fbc 100644 --- a/src/vendorcode/amd/agesa/f14/Proc/HT/Fam14/htNbUtilitiesFam14.c +++ b/src/vendorcode/amd/agesa/f14/Proc/HT/Fam14/htNbUtilitiesFam14.c @@ -10,7 +10,7 @@ * @xrefitem bom "File Content Label" "Release Content" * @e project: AGESA * @e sub-project: HyperTransport - * @e \$Revision: 34897 $ @e \$Date: 2010-07-14 10:07:10 +0800 (Wed, 14 Jul 2010) $ + * @e \$Revision: 44325 $ @e \$Date: 2010-12-22 03:29:53 -0700 (Wed, 22 Dec 2010) $ * */ /* @@ -126,14 +126,3 @@ Fam14GetNodeCount ( return (1); } -AP_MAIL_INFO -Fam14RetrieveMailbox ( - IN UINT8 Node, - IN NORTHBRIDGE *Nb - ) -{ - AP_MAIL_INFO NodeApMailBox; - ASSERT (Nb != NULL); - NodeApMailBox.Info = 0; - return NodeApMailBox; -} diff --git a/src/vendorcode/amd/agesa/f14/Proc/HT/Fam14/htNbUtilitiesFam14.h b/src/vendorcode/amd/agesa/f14/Proc/HT/Fam14/htNbUtilitiesFam14.h index 533a79c6db..eeb84ec3ef 100644 --- a/src/vendorcode/amd/agesa/f14/Proc/HT/Fam14/htNbUtilitiesFam14.h +++ b/src/vendorcode/amd/agesa/f14/Proc/HT/Fam14/htNbUtilitiesFam14.h @@ -7,7 +7,7 @@ * @xrefitem bom "File Content Label" "Release Content" * @e project: AGESA * @e sub-project: HyperTransport - * @e \$Revision: 34897 $ @e \$Date: 2010-07-14 10:07:10 +0800 (Wed, 14 Jul 2010) $ + * @e \$Revision: 44325 $ @e \$Date: 2010-12-22 03:29:53 -0700 (Wed, 22 Dec 2010) $ * */ /* @@ -60,9 +60,4 @@ Fam14GetNodeCount ( IN NORTHBRIDGE *Nb ); -AP_MAIL_INFO -Fam14RetrieveMailbox ( - IN UINT8 Node, - IN NORTHBRIDGE *Nb - ); #endif // _HT_NB_UTILITIES_FAM14_H_ diff --git a/src/vendorcode/amd/agesa/f14/Proc/IDS/IdsLib.h b/src/vendorcode/amd/agesa/f14/Proc/IDS/IdsLib.h index fe90b67e99..fe909be4d8 100644 --- a/src/vendorcode/amd/agesa/f14/Proc/IDS/IdsLib.h +++ b/src/vendorcode/amd/agesa/f14/Proc/IDS/IdsLib.h @@ -9,7 +9,7 @@ * @xrefitem bom "File Content Label" "Release Content" * @e project: AGESA * @e sub-project: IDS - * @e \$Revision: 35777 $ @e \$Date: 2010-07-30 17:41:05 +0800 (Fri, 30 Jul 2010) $ + * @e \$Revision: 44324 $ @e \$Date: 2010-12-22 02:16:51 -0700 (Wed, 22 Dec 2010) $ */ /* ***************************************************************************** diff --git a/src/vendorcode/amd/agesa/f14/Proc/Mem/Feat/CSINTLV/mfcsi.c b/src/vendorcode/amd/agesa/f14/Proc/Mem/Feat/CSINTLV/mfcsi.c index 812aa963e4..0f22e1b71e 100644 --- a/src/vendorcode/amd/agesa/f14/Proc/Mem/Feat/CSINTLV/mfcsi.c +++ b/src/vendorcode/amd/agesa/f14/Proc/Mem/Feat/CSINTLV/mfcsi.c @@ -86,6 +86,11 @@ MemFDctInterleaveBanks ( IN OUT MEM_NB_BLOCK *NBPtr ); +BOOLEAN +MemFUndoInterleaveBanks ( + IN OUT MEM_NB_BLOCK *NBPtr + ); + VOID STATIC CsIntSwap ( diff --git a/src/vendorcode/amd/agesa/f14/Proc/Mem/Feat/DMI/mfDMI.c b/src/vendorcode/amd/agesa/f14/Proc/Mem/Feat/DMI/mfDMI.c index b4d17194ea..bcbee65444 100644 --- a/src/vendorcode/amd/agesa/f14/Proc/Mem/Feat/DMI/mfDMI.c +++ b/src/vendorcode/amd/agesa/f14/Proc/Mem/Feat/DMI/mfDMI.c @@ -9,7 +9,7 @@ * @xrefitem bom "File Content Label" "Release Content" * @e project: AGESA * @e sub-project: (Mem/Main) - * @e \$Revision: 39742 $ @e \$Date: 2010-10-15 02:11:58 +0800 (Fri, 15 Oct 2010) $ + * @e \$Revision: 46495 $ @e \$Date: 2011-02-03 14:10:56 -0700 (Thu, 03 Feb 2011) $ * **/ /* @@ -84,6 +84,16 @@ RDATA_GROUP (G2_PEI) *---------------------------------------------------------------------------- */ +BOOLEAN +MemFDMISupport3 ( + IN OUT MEM_MAIN_DATA_BLOCK *MemMainPtr + ); + +BOOLEAN +MemFDMISupport2 ( + IN OUT MEM_MAIN_DATA_BLOCK *MemMainPtr + ); + /*---------------------------------------------------------------------------- * EXPORTED FUNCTIONS * @@ -505,7 +515,7 @@ MemFDMISupport2 ( // Form Factor (offset 0Eh) FormFactor = (UINT8) SpdDataStructure[DimmIndex].Data[20]; - if ((FormFactor & 0x20) == 4) { + if ((FormFactor & 0x04) == 4) { DmiTable[DimmIndex].FormFactor = 0x0D; // SO-DIMM } else { DmiTable[DimmIndex].FormFactor = 0x09; // RDIMM or UDIMM diff --git a/src/vendorcode/amd/agesa/f14/Proc/Mem/Feat/ECC/mfecc.c b/src/vendorcode/amd/agesa/f14/Proc/Mem/Feat/ECC/mfecc.c index 4ea95e98cd..4344e25663 100644 --- a/src/vendorcode/amd/agesa/f14/Proc/Mem/Feat/ECC/mfecc.c +++ b/src/vendorcode/amd/agesa/f14/Proc/Mem/Feat/ECC/mfecc.c @@ -75,11 +75,18 @@ RDATA_GROUP (G2_PEI) *---------------------------------------------------------------------------- */ +BOOLEAN +MemFCheckECC ( + IN OUT MEM_NB_BLOCK *NBPtr + ); + +/* UINT32 STATIC MemFGetScrubAddr ( IN OUT MEM_NB_BLOCK *NBPtr ); +*/ VOID STATIC @@ -296,6 +303,7 @@ InitECCOverriedeStruct ( * @return Scrubber Address */ +/* UINT32 STATIC MemFGetScrubAddr ( @@ -318,4 +326,4 @@ MemFGetScrubAddr ( } return ((ScrubAddrHi << 16) | (ScrubAddrLo >> 16)); } - +*/ diff --git a/src/vendorcode/amd/agesa/f14/Proc/Mem/Feat/ECC/mfemp.c b/src/vendorcode/amd/agesa/f14/Proc/Mem/Feat/ECC/mfemp.c index cdf3568259..75590ede75 100644 --- a/src/vendorcode/amd/agesa/f14/Proc/Mem/Feat/ECC/mfemp.c +++ b/src/vendorcode/amd/agesa/f14/Proc/Mem/Feat/ECC/mfemp.c @@ -75,6 +75,11 @@ RDATA_GROUP (G2_PEI) *---------------------------------------------------------------------------- */ BOOLEAN +MemFInitEMP ( + IN OUT MEM_NB_BLOCK *NBPtr + ); + +BOOLEAN STATIC IsPowerOfTwo ( IN UINT32 TestNumber diff --git a/src/vendorcode/amd/agesa/f14/Proc/Mem/Feat/EXCLUDIMM/mfdimmexclud.c b/src/vendorcode/amd/agesa/f14/Proc/Mem/Feat/EXCLUDIMM/mfdimmexclud.c index c6e85ec3f0..bcd069b7ca 100644 --- a/src/vendorcode/amd/agesa/f14/Proc/Mem/Feat/EXCLUDIMM/mfdimmexclud.c +++ b/src/vendorcode/amd/agesa/f14/Proc/Mem/Feat/EXCLUDIMM/mfdimmexclud.c @@ -9,7 +9,7 @@ * @xrefitem bom "File Content Label" "Release Content" * @e project: AGESA * @e sub-project: (Mem/Feat/EXCLUDIMM) - * @e \$Revision: 35136 $ @e \$Date: 2010-07-16 11:29:48 +0800 (Fri, 16 Jul 2010) $ + * @e \$Revision: 48496 $ @e \$Date: 2011-03-09 12:26:48 -0700 (Wed, 09 Mar 2011) $ * **/ /* @@ -82,6 +82,11 @@ RDATA_GROUP (G2_PEI) *---------------------------------------------------------------------------- */ +BOOLEAN +MemFRASExcludeDIMM ( + IN OUT MEM_NB_BLOCK *NBPtr + ); + /*---------------------------------------------------------------------------- * EXPORTED FUNCTIONS * @@ -163,6 +168,8 @@ MemFRASExcludeDIMM ( IsCSIntlvEnabled = TRUE; } + Flag = TRUE; + NBPtr->FamilySpecificHook[BfAfExcludeDimm] (NBPtr, &Flag); for (Dct = 0; Dct < NBPtr->DctCount; Dct++) { NBPtr->SwitchDCT (NBPtr, Dct); if (!MCTPtr->GangedMode || (MCTPtr->Dct == 0)) { @@ -179,6 +186,8 @@ MemFRASExcludeDIMM ( } } } + Flag = FALSE; + NBPtr->FamilySpecificHook[BfAfExcludeDimm] (NBPtr, &Flag); // Re-enable chip select interleaving when remapping is done. if (IsCSIntlvEnabled) { diff --git a/src/vendorcode/amd/agesa/f14/Proc/Mem/Feat/IDENDIMM/mfidendimm.c b/src/vendorcode/amd/agesa/f14/Proc/Mem/Feat/IDENDIMM/mfidendimm.c index 9576f8014b..f96841b051 100644 --- a/src/vendorcode/amd/agesa/f14/Proc/Mem/Feat/IDENDIMM/mfidendimm.c +++ b/src/vendorcode/amd/agesa/f14/Proc/Mem/Feat/IDENDIMM/mfidendimm.c @@ -9,7 +9,7 @@ * @xrefitem bom "File Content Label" "Release Content" * @e project: AGESA * @e sub-project: (Mem/Feat) - * @e \$Revision: 35136 $ @e \$Date: 2010-07-16 11:29:48 +0800 (Fri, 16 Jul 2010) $ + * @e \$Revision: 46495 $ @e \$Date: 2011-02-03 14:10:56 -0700 (Thu, 03 Feb 2011) $ * **/ /* @@ -160,6 +160,7 @@ AmdIdentifyDimm ( // NB block has already been constructed by main block. // No need to construct it here. NBPtr = (MEM_NB_BLOCK *)LocHeap.BufferPtr; + mmData.NBPtr = NBPtr; } else { AllocHeapParams.RequestedBufferSize = (DieCount * (sizeof (MEM_NB_BLOCK))); AllocHeapParams.BufferHandle = AMD_MEM_AUTO_HANDLE; diff --git a/src/vendorcode/amd/agesa/f14/Proc/Mem/Feat/S3/mfs3.c b/src/vendorcode/amd/agesa/f14/Proc/Mem/Feat/S3/mfs3.c index b51db06a5b..df2071f5bc 100644 --- a/src/vendorcode/amd/agesa/f14/Proc/Mem/Feat/S3/mfs3.c +++ b/src/vendorcode/amd/agesa/f14/Proc/Mem/Feat/S3/mfs3.c @@ -703,7 +703,7 @@ MemFS3Wait10ns ( CPU_SPECIFIC_SERVICES *FamilySpecificServices; ASSERT (Count <= 1000000); - GetCpuServicesOfCurrentCore (&FamilySpecificServices, &MemPtr->StdHeader); + GetCpuServicesOfCurrentCore ((const CPU_SPECIFIC_SERVICES **)&FamilySpecificServices, &MemPtr->StdHeader); FamilySpecificServices->GetTscRate (FamilySpecificServices, &TscRate, &MemPtr->StdHeader); LibAmdMsrRead (TSC, &CurrentTsc, &MemPtr->StdHeader); diff --git a/src/vendorcode/amd/agesa/f14/Proc/Mem/Main/ON/mmflowon.c b/src/vendorcode/amd/agesa/f14/Proc/Mem/Main/ON/mmflowon.c index 378ca7a254..2c0cb25141 100644 --- a/src/vendorcode/amd/agesa/f14/Proc/Mem/Main/ON/mmflowon.c +++ b/src/vendorcode/amd/agesa/f14/Proc/Mem/Main/ON/mmflowon.c @@ -88,6 +88,11 @@ extern MEM_FEAT_BLOCK_MAIN MemFeatMain; *---------------------------------------------------------------------------- */ +AGESA_STATUS +MemMFlowON ( + IN OUT MEM_MAIN_DATA_BLOCK *MemMainPtr + ); + /*---------------------------------------------------------------------------- * EXPORTED FUNCTIONS * diff --git a/src/vendorcode/amd/agesa/f14/Proc/Mem/Main/mdef.c b/src/vendorcode/amd/agesa/f14/Proc/Mem/Main/mdef.c index 0d80a4ec4d..a280d40656 100644 --- a/src/vendorcode/amd/agesa/f14/Proc/Mem/Main/mdef.c +++ b/src/vendorcode/amd/agesa/f14/Proc/Mem/Main/mdef.c @@ -53,6 +53,7 @@ */ #include "AGESA.h" +#include "AdvancedApi.h" #include "Filecode.h" #include "mm.h" CODE_GROUP (G1_PEICC) @@ -77,6 +78,11 @@ RDATA_GROUP (G1_PEICC) *---------------------------------------------------------------------------- */ +AGESA_STATUS +MemMFlowDef ( + IN OUT MEM_MAIN_DATA_BLOCK *MemMainPtr + ); + /*---------------------------------------------------------------------------- * EXPORTED FUNCTIONS * diff --git a/src/vendorcode/amd/agesa/f14/Proc/Mem/Main/minit.c b/src/vendorcode/amd/agesa/f14/Proc/Mem/Main/minit.c index ba3346bce6..7b6edc4691 100644 --- a/src/vendorcode/amd/agesa/f14/Proc/Mem/Main/minit.c +++ b/src/vendorcode/amd/agesa/f14/Proc/Mem/Main/minit.c @@ -54,6 +54,7 @@ #include "AGESA.h" #include "amdlib.h" +#include "AdvancedApi.h" #include "mu.h" #include "OptionMemory.h" #include "Ids.h" diff --git a/src/vendorcode/amd/agesa/f14/Proc/Mem/Main/mmEcc.c b/src/vendorcode/amd/agesa/f14/Proc/Mem/Main/mmEcc.c index 9105b3a57d..1e3067395d 100644 --- a/src/vendorcode/amd/agesa/f14/Proc/Mem/Main/mmEcc.c +++ b/src/vendorcode/amd/agesa/f14/Proc/Mem/Main/mmEcc.c @@ -74,6 +74,11 @@ RDATA_GROUP (G1_PEICC) *----------------------------------------------------------------------------- */ +BOOLEAN +MemMEcc ( + IN OUT MEM_MAIN_DATA_BLOCK *mmPtr + ); + /* -----------------------------------------------------------------------------*/ /** * diff --git a/src/vendorcode/amd/agesa/f14/Proc/Mem/Main/mmExcludeDimm.c b/src/vendorcode/amd/agesa/f14/Proc/Mem/Main/mmExcludeDimm.c index 9eb20bba72..0b62c00991 100644 --- a/src/vendorcode/amd/agesa/f14/Proc/Mem/Main/mmExcludeDimm.c +++ b/src/vendorcode/amd/agesa/f14/Proc/Mem/Main/mmExcludeDimm.c @@ -73,6 +73,11 @@ extern MEM_FEAT_BLOCK_MAIN MemFeatMain; *----------------------------------------------------------------------------- */ +BOOLEAN +MemMRASExcludeDIMM ( + IN OUT MEM_MAIN_DATA_BLOCK *MemMainPtr + ); + /* -----------------------------------------------------------------------------*/ /** * @@ -184,7 +189,7 @@ MemMRASExcludeDIMM ( LibAmdMsrRead (TOP_MEM, (UINT64 *)&SMsr, &NBPtr->MemPtr->StdHeader); // Only when TOM is set can CpuMemTyping be re-run - if (SMsr.hi == SMsr.lo == 0) { + if ((SMsr.hi == 0) && (SMsr.lo == 0)) { if (RefPtr->SysLimit != 0) { NBPtr[BSP_DIE].CpuMemTyping (&NBPtr[BSP_DIE]); } diff --git a/src/vendorcode/amd/agesa/f14/Proc/Mem/Main/mmLvDdr3.c b/src/vendorcode/amd/agesa/f14/Proc/Mem/Main/mmLvDdr3.c index 1fe217118a..d00f92fe3f 100644 --- a/src/vendorcode/amd/agesa/f14/Proc/Mem/Main/mmLvDdr3.c +++ b/src/vendorcode/amd/agesa/f14/Proc/Mem/Main/mmLvDdr3.c @@ -58,6 +58,7 @@ #include "OptionMemory.h" #include "mm.h" #include "mn.h" +#include "mmlvddr3.h" #include "Filecode.h" CODE_GROUP (G1_PEICC) RDATA_GROUP (G1_PEICC) @@ -71,6 +72,11 @@ extern MEM_FEAT_BLOCK_MAIN MemFeatMain; *----------------------------------------------------------------------------- */ +BOOLEAN +MemMLvDdr3 ( + IN OUT MEM_MAIN_DATA_BLOCK *MemMainPtr + ); + /* -----------------------------------------------------------------------------*/ /** * diff --git a/src/vendorcode/amd/agesa/f14/Proc/Mem/Main/mmMemClr.c b/src/vendorcode/amd/agesa/f14/Proc/Mem/Main/mmMemClr.c index 55eb5a6d80..a8f504b25d 100644 --- a/src/vendorcode/amd/agesa/f14/Proc/Mem/Main/mmMemClr.c +++ b/src/vendorcode/amd/agesa/f14/Proc/Mem/Main/mmMemClr.c @@ -69,6 +69,10 @@ RDATA_GROUP (G2_PEI) *----------------------------------------------------------------------------- */ +BOOLEAN +MemMMctMemClr ( + IN OUT MEM_MAIN_DATA_BLOCK *MemMainPtr + ); /* -----------------------------------------------------------------------------*/ /** diff --git a/src/vendorcode/amd/agesa/f14/Proc/Mem/Main/mmMemRestore.c b/src/vendorcode/amd/agesa/f14/Proc/Mem/Main/mmMemRestore.c index 3038436e41..4a1ad29da6 100644 --- a/src/vendorcode/amd/agesa/f14/Proc/Mem/Main/mmMemRestore.c +++ b/src/vendorcode/amd/agesa/f14/Proc/Mem/Main/mmMemRestore.c @@ -75,6 +75,11 @@ RDATA_GROUP (G1_PEICC) * *---------------------------------------------------------------------------- */ +VOID +MemMContextSave ( + IN OUT MEM_MAIN_DATA_BLOCK *MemMainPtr + ); + BOOLEAN STATIC MemMRestoreDqsTimings ( @@ -97,6 +102,12 @@ MemMCreateS3NbBlock ( IN OUT MEM_MAIN_DATA_BLOCK *MemMainPtr, OUT S3_MEM_NB_BLOCK **S3NBPtr ); + +BOOLEAN +MemMContextRestore ( + IN OUT MEM_MAIN_DATA_BLOCK *MemMainPtr + ); + /*----------------------------------------------------------------------------- * EXPORTED FUNCTIONS * @@ -125,7 +136,7 @@ MemMContextSave ( DEVICE_BLOCK_HEADER *DeviceList; AMD_CONFIG_PARAMS *StdHeader; UINT32 BufferSize; - UINT64 BufferOffset; + VOID *BufferOffset; MEM_NB_BLOCK *NBArray; S3_MEM_NB_BLOCK *S3NBPtr; DESCRIPTOR_GROUP DeviceDescript[MAX_NODES_SUPPORTED]; @@ -160,30 +171,31 @@ MemMContextSave ( DeviceList->RelativeOrMaskOffset = (UINT16) AllocHeapParams.RequestedBufferSize; // Copy device list on the stack to the heap. - BufferOffset = sizeof (DEVICE_BLOCK_HEADER) + (UINT64) AllocHeapParams.BufferPtr; +// BufferOffset = sizeof (DEVICE_BLOCK_HEADER) + (UINT64) AllocHeapParams.BufferPtr; + BufferOffset = AllocHeapParams.BufferPtr + sizeof (DEVICE_BLOCK_HEADER); for (Node = 0; Node < MemMainPtr->DieCount; Node ++) { for (i = PRESELFREF; i <= POSTSELFREF; i ++) { // Copy PCI device descriptor to the heap if it exists. if (DeviceDescript[Node].PCIDevice[i].RegisterListID != 0xFFFFFFFF) { - LibAmdMemCopy ((VOID *) BufferOffset, &(DeviceDescript[Node].PCIDevice[i]), sizeof (PCI_DEVICE_DESCRIPTOR), StdHeader); + LibAmdMemCopy (BufferOffset, &(DeviceDescript[Node].PCIDevice[i]), sizeof (PCI_DEVICE_DESCRIPTOR), StdHeader); DeviceList->NumDevices ++; BufferOffset += sizeof (PCI_DEVICE_DESCRIPTOR); } // Copy conditional PCI device descriptor to the heap if it exists. if (DeviceDescript[Node].CPCIDevice[i].RegisterListID != 0xFFFFFFFF) { - LibAmdMemCopy ((VOID *) BufferOffset, &(DeviceDescript[Node].CPCIDevice[i]), sizeof (CONDITIONAL_PCI_DEVICE_DESCRIPTOR), StdHeader); + LibAmdMemCopy (BufferOffset, &(DeviceDescript[Node].CPCIDevice[i]), sizeof (CONDITIONAL_PCI_DEVICE_DESCRIPTOR), StdHeader); DeviceList->NumDevices ++; BufferOffset += sizeof (CONDITIONAL_PCI_DEVICE_DESCRIPTOR); } // Copy MSR device descriptor to the heap if it exists. if (DeviceDescript[Node].MSRDevice[i].RegisterListID != 0xFFFFFFFF) { - LibAmdMemCopy ((VOID *) BufferOffset, &(DeviceDescript[Node].MSRDevice[i]), sizeof (MSR_DEVICE_DESCRIPTOR), StdHeader); + LibAmdMemCopy ( BufferOffset, &(DeviceDescript[Node].MSRDevice[i]), sizeof (MSR_DEVICE_DESCRIPTOR), StdHeader); DeviceList->NumDevices ++; BufferOffset += sizeof (MSR_DEVICE_DESCRIPTOR); } // Copy conditional MSR device descriptor to the heap if it exists. if (DeviceDescript[Node].CMSRDevice[i].RegisterListID != 0xFFFFFFFF) { - LibAmdMemCopy ((VOID *) BufferOffset, &(DeviceDescript[Node].PCIDevice[i]), sizeof (CONDITIONAL_MSR_DEVICE_DESCRIPTOR), StdHeader); + LibAmdMemCopy ( BufferOffset, &(DeviceDescript[Node].PCIDevice[i]), sizeof (CONDITIONAL_MSR_DEVICE_DESCRIPTOR), StdHeader); DeviceList->NumDevices ++; BufferOffset += sizeof (CONDITIONAL_MSR_DEVICE_DESCRIPTOR); } diff --git a/src/vendorcode/amd/agesa/f14/Proc/Mem/Main/mmNodeInterleave.c b/src/vendorcode/amd/agesa/f14/Proc/Mem/Main/mmNodeInterleave.c index 066c38ffe3..62d2fda48a 100644 --- a/src/vendorcode/amd/agesa/f14/Proc/Mem/Main/mmNodeInterleave.c +++ b/src/vendorcode/amd/agesa/f14/Proc/Mem/Main/mmNodeInterleave.c @@ -71,6 +71,11 @@ extern MEM_FEAT_BLOCK_MAIN MemFeatMain; *----------------------------------------------------------------------------- */ +BOOLEAN +MemMInterleaveNodes ( + IN OUT MEM_MAIN_DATA_BLOCK *MemMainPtr + ); + /* -----------------------------------------------------------------------------*/ /** * diff --git a/src/vendorcode/amd/agesa/f14/Proc/Mem/Main/mmOnlineSpare.c b/src/vendorcode/amd/agesa/f14/Proc/Mem/Main/mmOnlineSpare.c index f88cc150f6..b19f60e789 100644 --- a/src/vendorcode/amd/agesa/f14/Proc/Mem/Main/mmOnlineSpare.c +++ b/src/vendorcode/amd/agesa/f14/Proc/Mem/Main/mmOnlineSpare.c @@ -69,6 +69,11 @@ RDATA_GROUP (G2_PEI) *----------------------------------------------------------------------------- */ +BOOLEAN +MemMOnlineSpare ( + IN OUT MEM_MAIN_DATA_BLOCK *MemMainPtr + ); + /* -----------------------------------------------------------------------------*/ /** * diff --git a/src/vendorcode/amd/agesa/f14/Proc/Mem/Main/mmParallelTraining.c b/src/vendorcode/amd/agesa/f14/Proc/Mem/Main/mmParallelTraining.c index f9de5c5ad8..216c0925d5 100644 --- a/src/vendorcode/amd/agesa/f14/Proc/Mem/Main/mmParallelTraining.c +++ b/src/vendorcode/amd/agesa/f14/Proc/Mem/Main/mmParallelTraining.c @@ -82,6 +82,12 @@ extern MEM_FEAT_BLOCK_MAIN MemFeatMain; * *----------------------------------------------------------------------------- */ + +BOOLEAN +MemMParallelTraining ( + IN OUT MEM_MAIN_DATA_BLOCK *mmPtr + ); + /* -----------------------------------------------------------------------------*/ /** * diff --git a/src/vendorcode/amd/agesa/f14/Proc/Mem/Main/mmStandardTraining.c b/src/vendorcode/amd/agesa/f14/Proc/Mem/Main/mmStandardTraining.c index f1a6f612cd..b0376a4819 100644 --- a/src/vendorcode/amd/agesa/f14/Proc/Mem/Main/mmStandardTraining.c +++ b/src/vendorcode/amd/agesa/f14/Proc/Mem/Main/mmStandardTraining.c @@ -72,6 +72,10 @@ RDATA_GROUP (G1_PEICC) * *----------------------------------------------------------------------------- */ +BOOLEAN +MemMStandardTraining ( + IN OUT MEM_MAIN_DATA_BLOCK *mmPtr + ); /* -----------------------------------------------------------------------------*/ /** diff --git a/src/vendorcode/amd/agesa/f14/Proc/Mem/Main/mmUmaAlloc.c b/src/vendorcode/amd/agesa/f14/Proc/Mem/Main/mmUmaAlloc.c index 0f03a05e2f..755586a08e 100644 --- a/src/vendorcode/amd/agesa/f14/Proc/Mem/Main/mmUmaAlloc.c +++ b/src/vendorcode/amd/agesa/f14/Proc/Mem/Main/mmUmaAlloc.c @@ -82,6 +82,12 @@ RDATA_GROUP (G1_PEICC) * *---------------------------------------------------------------------------- */ + +BOOLEAN +MemMUmaAlloc ( + IN OUT MEM_MAIN_DATA_BLOCK *MemMainPtr + ); + /*----------------------------------------------------------------------------- * EXPORTED FUNCTIONS * diff --git a/src/vendorcode/amd/agesa/f14/Proc/Mem/Main/mmflow.c b/src/vendorcode/amd/agesa/f14/Proc/Mem/Main/mmflow.c index d3c0541327..97fab2e1fe 100644 --- a/src/vendorcode/amd/agesa/f14/Proc/Mem/Main/mmflow.c +++ b/src/vendorcode/amd/agesa/f14/Proc/Mem/Main/mmflow.c @@ -60,6 +60,7 @@ #include "GeneralServices.h" #include "cpuFamilyTranslation.h" #include "OptionMemory.h" +#include "AdvancedApi.h" #include "mm.h" #include "mn.h" #include "mt.h" @@ -174,7 +175,7 @@ AmdMemAuto ( //---------------------------------------------------------------------------- // Get TSC rate, which will be used later in Wait10ns routine //---------------------------------------------------------------------------- - GetCpuServicesOfCurrentCore (&FamilySpecificServices, &MemPtr->StdHeader); + GetCpuServicesOfCurrentCore ((const CPU_SPECIFIC_SERVICES **)&FamilySpecificServices, &MemPtr->StdHeader); FamilySpecificServices->GetTscRate (FamilySpecificServices, &MemPtr->TscRate, &MemPtr->StdHeader); //---------------------------------------------------------------------------- @@ -375,7 +376,7 @@ MemSPDDataProcess ( } } } else { - PutEventLog (AGESA_FATAL, MEM_ERROR_HEAP_ALLOCATE_FOR_SPD, NULL, NULL, NULL, NULL, &MemPtr->StdHeader); + PutEventLog (AGESA_FATAL, MEM_ERROR_HEAP_ALLOCATE_FOR_SPD, 0, 0, 0, 0, &MemPtr->StdHeader); // // Assert here if unable to allocate heap for SPDs // diff --git a/src/vendorcode/amd/agesa/f14/Proc/Mem/Main/mu.c b/src/vendorcode/amd/agesa/f14/Proc/Mem/Main/mu.c index edd39ddb2a..3c83a066bd 100644 --- a/src/vendorcode/amd/agesa/f14/Proc/Mem/Main/mu.c +++ b/src/vendorcode/amd/agesa/f14/Proc/Mem/Main/mu.c @@ -59,6 +59,7 @@ #include "AGESA.h" #include "amdlib.h" +#include "mu.h" #include "Filecode.h" /*---------------------------------------------------------------------------------------- @@ -76,6 +77,7 @@ *---------------------------------------------------------------------------------------- */ +/* VOID MemUWriteCachelines ( IN UINT32 Address, @@ -110,7 +112,8 @@ VOID AlignPointerTo16Byte ( IN OUT UINT8 **BufferPtrPtr ); - +*/ + /*---------------------------------------------------------------------------------------- * E X P O R T E D F U N C T I O N S *---------------------------------------------------------------------------------------- diff --git a/src/vendorcode/amd/agesa/f14/Proc/Mem/Main/muc.c b/src/vendorcode/amd/agesa/f14/Proc/Mem/Main/muc.c index 2ddd305e44..961ea1df00 100644 --- a/src/vendorcode/amd/agesa/f14/Proc/Mem/Main/muc.c +++ b/src/vendorcode/amd/agesa/f14/Proc/Mem/Main/muc.c @@ -646,7 +646,7 @@ GetVarMtrrHiMsk ( CPU_SPECIFIC_SERVICES *FamilySpecificServices; CACHE_INFO *CacheInfoPtr; - GetCpuServicesFromLogicalId (LogicalIdPtr, &FamilySpecificServices, StdHeader); - FamilySpecificServices->GetCacheInfo (FamilySpecificServices, &CacheInfoPtr, &TempNotCare, StdHeader); + GetCpuServicesFromLogicalId (LogicalIdPtr, (const CPU_SPECIFIC_SERVICES **)&FamilySpecificServices, StdHeader); + FamilySpecificServices->GetCacheInfo (FamilySpecificServices, (const VOID **)&CacheInfoPtr, &TempNotCare, StdHeader); return (UINT32) (CacheInfoPtr->VariableMtrrMask >> 32); } diff --git a/src/vendorcode/amd/agesa/f14/Proc/Mem/NB/C32/mnParTrainc32.c b/src/vendorcode/amd/agesa/f14/Proc/Mem/NB/C32/mnParTrainc32.c index d683da8e5d..b3f0a8ee14 100644 --- a/src/vendorcode/amd/agesa/f14/Proc/Mem/NB/C32/mnParTrainc32.c +++ b/src/vendorcode/amd/agesa/f14/Proc/Mem/NB/C32/mnParTrainc32.c @@ -217,7 +217,7 @@ MemConstructRemoteNBBlockC32 ( //---------------------------------------------------------------------------- // Get TSC rate of the this AP //---------------------------------------------------------------------------- - GetCpuServicesOfCurrentCore (&FamilySpecificServices, &NBPtr->MemPtr->StdHeader); + GetCpuServicesOfCurrentCore ((const CPU_SPECIFIC_SERVICES **)&FamilySpecificServices, &NBPtr->MemPtr->StdHeader); FamilySpecificServices->GetTscRate (FamilySpecificServices, &NBPtr->MemPtr->TscRate, &NBPtr->MemPtr->StdHeader); return TRUE; diff --git a/src/vendorcode/amd/agesa/f14/Proc/Mem/NB/DA/mnParTrainDa.c b/src/vendorcode/amd/agesa/f14/Proc/Mem/NB/DA/mnParTrainDa.c index 143baac643..2f149a212b 100644 --- a/src/vendorcode/amd/agesa/f14/Proc/Mem/NB/DA/mnParTrainDa.c +++ b/src/vendorcode/amd/agesa/f14/Proc/Mem/NB/DA/mnParTrainDa.c @@ -219,7 +219,7 @@ MemConstructRemoteNBBlockDA ( //---------------------------------------------------------------------------- // Get TSC rate of the this AP //---------------------------------------------------------------------------- - GetCpuServicesOfCurrentCore (&FamilySpecificServices, &NBPtr->MemPtr->StdHeader); + GetCpuServicesOfCurrentCore ((const CPU_SPECIFIC_SERVICES **)&FamilySpecificServices, &NBPtr->MemPtr->StdHeader); FamilySpecificServices->GetTscRate (FamilySpecificServices, &NBPtr->MemPtr->TscRate, &NBPtr->MemPtr->StdHeader); return TRUE; diff --git a/src/vendorcode/amd/agesa/f14/Proc/Mem/NB/DA/mndctda.c b/src/vendorcode/amd/agesa/f14/Proc/Mem/NB/DA/mndctda.c index d1e241c3b5..f56d02ab3d 100644 --- a/src/vendorcode/amd/agesa/f14/Proc/Mem/NB/DA/mndctda.c +++ b/src/vendorcode/amd/agesa/f14/Proc/Mem/NB/DA/mndctda.c @@ -405,7 +405,7 @@ MemNCapSpeedBatteryLifeDA ( FamilySpecificServices = NULL; DdrFreq = DDR800_FREQUENCY; // Set Default to be 400Mhz ProcessorPackageType = LibAmdGetPackageType (&(NBPtr->MemPtr->StdHeader)); - GetCpuServicesOfSocket (NBPtr->MCTPtr->SocketId, &FamilySpecificServices, &(NBPtr->MemPtr->StdHeader)); + GetCpuServicesOfSocket (NBPtr->MCTPtr->SocketId, (const CPU_SPECIFIC_SERVICES **)&FamilySpecificServices, &(NBPtr->MemPtr->StdHeader)); if (FamilySpecificServices->IsNbPstateEnabled (FamilySpecificServices, NBPtr->MemPtr->PlatFormConfig, &(NBPtr->MemPtr->StdHeader))) { NBFreq = (MemNGetBitFieldNb (NBPtr, BFNbFid) + 4) * 100; // Calculate the Nb P1 frequency (NbFreq / 2) for (j = 0; j < GET_SIZE_OF (SupportedFreq); j++) { diff --git a/src/vendorcode/amd/agesa/f14/Proc/Mem/NB/DR/mnParTrainDr.c b/src/vendorcode/amd/agesa/f14/Proc/Mem/NB/DR/mnParTrainDr.c index 33ec0c77c1..17a8427d22 100644 --- a/src/vendorcode/amd/agesa/f14/Proc/Mem/NB/DR/mnParTrainDr.c +++ b/src/vendorcode/amd/agesa/f14/Proc/Mem/NB/DR/mnParTrainDr.c @@ -219,7 +219,7 @@ MemConstructRemoteNBBlockDR ( //---------------------------------------------------------------------------- // Get TSC rate of the this AP //---------------------------------------------------------------------------- - GetCpuServicesOfCurrentCore (&FamilySpecificServices, &NBPtr->MemPtr->StdHeader); + GetCpuServicesOfCurrentCore ((const CPU_SPECIFIC_SERVICES **)&FamilySpecificServices, &NBPtr->MemPtr->StdHeader); FamilySpecificServices->GetTscRate (FamilySpecificServices, &NBPtr->MemPtr->TscRate, &NBPtr->MemPtr->StdHeader); return TRUE; diff --git a/src/vendorcode/amd/agesa/f14/Proc/Mem/NB/HY/mnParTrainHy.c b/src/vendorcode/amd/agesa/f14/Proc/Mem/NB/HY/mnParTrainHy.c index 651ba7cf56..8a444362a8 100644 --- a/src/vendorcode/amd/agesa/f14/Proc/Mem/NB/HY/mnParTrainHy.c +++ b/src/vendorcode/amd/agesa/f14/Proc/Mem/NB/HY/mnParTrainHy.c @@ -217,7 +217,7 @@ MemConstructRemoteNBBlockHY ( //---------------------------------------------------------------------------- // Get TSC rate of the this AP //---------------------------------------------------------------------------- - GetCpuServicesOfCurrentCore (&FamilySpecificServices, &NBPtr->MemPtr->StdHeader); + GetCpuServicesOfCurrentCore ((const CPU_SPECIFIC_SERVICES **)&FamilySpecificServices, &NBPtr->MemPtr->StdHeader); FamilySpecificServices->GetTscRate (FamilySpecificServices, &NBPtr->MemPtr->TscRate, &NBPtr->MemPtr->StdHeader); return TRUE; diff --git a/src/vendorcode/amd/agesa/f14/Proc/Mem/NB/ON/mnS3on.c b/src/vendorcode/amd/agesa/f14/Proc/Mem/NB/ON/mnS3on.c index dcbbf96969..4af0dfba8c 100644 --- a/src/vendorcode/amd/agesa/f14/Proc/Mem/NB/ON/mnS3on.c +++ b/src/vendorcode/amd/agesa/f14/Proc/Mem/NB/ON/mnS3on.c @@ -9,7 +9,7 @@ * @xrefitem bom "File Content Label" "Release Content" * @e project: AGESA * @e sub-project: (Mem/NB/ON) - * @e \$Revision: 38639 $ @e \$Date: 2010-09-27 21:55:34 +0800 (Mon, 27 Sep 2010) $ + * @e \$Revision: 48511 $ @e \$Date: 2011-03-09 13:53:13 -0700 (Wed, 09 Mar 2011) $ * **/ /* @@ -120,6 +120,14 @@ MemNS3GetConPCIMaskON ( IN OUT MEM_NB_BLOCK *NBPtr, IN OUT DESCRIPTOR_GROUP *DescriptPtr ); + +BOOLEAN +MemS3ResumeConstructNBBlockON ( + IN OUT VOID *S3NBPtr, + IN OUT MEM_DATA_STRUCT *MemPtr, + IN UINT8 NodeID + ); + /*---------------------------------------------------------------------------- * DEFINITIONS AND MACROS * @@ -176,6 +184,11 @@ PCI_REG_DESCRIPTOR ROMDATA S3PciPreSelfRefDescriptorON[] = { {{1, 1, 1}, DCT0, BFAddrRxVioLvl, 0x00000018}, // 4. Frequency Change {{4, 3, 1}, DCT0, BFPllLockTime, 0}, + {{1, 2, 1}, DCT0, BFDllCSRBisaTrimDByte, 0x7000}, + {{1, 2, 1}, DCT0, BFDllCSRBisaTrimClk, 0x7000}, + {{1, 2, 1}, DCT0, BFDllCSRBisaTrimCsOdt, 0x7000}, + {{1, 2, 1}, DCT0, BFDllCSRBisaTrimAByte2, 0x7000}, + {{1, 2, 1}, DCT0, BFReduceLoop, 0x6000}, {{0, 0, 0}, FUNC_2, 0x94, 0xFFD1CC1F}, // NB Pstate Related Register for Pstate 0 {{0, 0, 0}, FUNC_2, 0x78, 0xFFF63FCF}, diff --git a/src/vendorcode/amd/agesa/f14/Proc/Mem/NB/ON/mndcton.c b/src/vendorcode/amd/agesa/f14/Proc/Mem/NB/ON/mndcton.c index c0855b8f43..a3afd55e20 100644 --- a/src/vendorcode/amd/agesa/f14/Proc/Mem/NB/ON/mndcton.c +++ b/src/vendorcode/amd/agesa/f14/Proc/Mem/NB/ON/mndcton.c @@ -9,7 +9,7 @@ * @xrefitem bom "File Content Label" "Release Content" * @e project: AGESA * @e sub-project: (Mem/NB/ON) - * @e \$Revision: 37169 $ @e \$Date: 2010-09-01 05:35:27 +0800 (Wed, 01 Sep 2010) $ + * @e \$Revision: 48511 $ @e \$Date: 2011-03-09 13:53:13 -0700 (Wed, 09 Mar 2011) $ * **/ /* @@ -149,7 +149,7 @@ MemNAutoConfigON ( MemNSetBitFieldNb (NBPtr, BFPowerDownMode, 1); } - MemNSetBitFieldNb (NBPtr, BFPchgPDModeSel, 1); + MemNSetBitFieldNb (NBPtr, BFPchgPDModeSel, (((MemNGetBitFieldNb (NBPtr, BFLowPowerDefault)) == 1) && (NBPtr->MemPtr->PlatFormConfig->PlatformProfile.PlatformPowerPolicy == BatteryLife)) ? 0 : 1); MemNSetBitFieldNb (NBPtr, BFDcqBypassMax, 0xE); @@ -459,7 +459,7 @@ MemNChangeNbFrequencyWrapON ( if (Status) { // When NB frequency change succeeds, TSC rate may have changed. // We need to update TSC rate - GetCpuServicesOfCurrentCore (&FamilySpecificServices, &NBPtr->MemPtr->StdHeader); + GetCpuServicesOfCurrentCore ((const CPU_SPECIFIC_SERVICES **)&FamilySpecificServices, &NBPtr->MemPtr->StdHeader); FamilySpecificServices->GetTscRate (FamilySpecificServices, &NBPtr->MemPtr->TscRate, &NBPtr->MemPtr->StdHeader); } return Status; @@ -487,4 +487,33 @@ MemNSetDqsODTON ( MemNSetBitFieldNb (NBPtr, BFDQOdt47, 0x20); } return TRUE; -}
\ No newline at end of file +} + +/* -----------------------------------------------------------------------------*/ +/** + * + * + * This function sets reduceloop and trim value for DDR-1333 for C0 + * + * @param[in,out] *NBPtr - Pointer to the MEM_NB_BLOCK + * @param[in,out] OptParam - Optional parameter + * + * @return TRUE + * + */ + +BOOLEAN +MemNBeforeMemClkFreqValON ( + IN OUT MEM_NB_BLOCK *NBPtr, + IN OUT VOID *OptParam + ) +{ + if ((NBPtr->DCTPtr->Timings.Speed == DDR1333_FREQUENCY) && ((NBPtr->MCTPtr->LogicalCpuid.Revision & AMD_F14_ON_Cx) != 0)) { + MemNBrdcstSetNb (NBPtr, BFDllCSRBisaTrimDByte, 0x7000); + MemNBrdcstSetNb (NBPtr, BFDllCSRBisaTrimClk, 0x7000); + MemNBrdcstSetNb (NBPtr, BFDllCSRBisaTrimCsOdt, 0x7000); + MemNBrdcstSetNb (NBPtr, BFDllCSRBisaTrimAByte2, 0x7000); + MemNBrdcstSetNb (NBPtr, BFReduceLoop, 0x6000); + } + return TRUE; +} diff --git a/src/vendorcode/amd/agesa/f14/Proc/Mem/NB/ON/mnflowon.c b/src/vendorcode/amd/agesa/f14/Proc/Mem/NB/ON/mnflowon.c index b7efd35cbb..f6f170d607 100644 --- a/src/vendorcode/amd/agesa/f14/Proc/Mem/NB/ON/mnflowon.c +++ b/src/vendorcode/amd/agesa/f14/Proc/Mem/NB/ON/mnflowon.c @@ -60,6 +60,7 @@ #include "OptionMemory.h" #include "mm.h" #include "mn.h" +#include "mnon.h" #include "mt.h" #include "Filecode.h" #include "GeneralServices.h" diff --git a/src/vendorcode/amd/agesa/f14/Proc/Mem/NB/ON/mnidendimmon.c b/src/vendorcode/amd/agesa/f14/Proc/Mem/NB/ON/mnidendimmon.c index 9e4060af3f..718e52b608 100644 --- a/src/vendorcode/amd/agesa/f14/Proc/Mem/NB/ON/mnidendimmon.c +++ b/src/vendorcode/amd/agesa/f14/Proc/Mem/NB/ON/mnidendimmon.c @@ -85,6 +85,13 @@ */ +BOOLEAN +MemNIdentifyDimmConstructorON ( + IN OUT MEM_NB_BLOCK *NBPtr, + IN OUT MEM_DATA_STRUCT *MemPtr, + IN UINT8 NodeID + ); + /*---------------------------------------------------------------------------- * EXPORTED FUNCTIONS * diff --git a/src/vendorcode/amd/agesa/f14/Proc/Mem/NB/ON/mnon.c b/src/vendorcode/amd/agesa/f14/Proc/Mem/NB/ON/mnon.c index 768d0d7106..17a20198cf 100644 --- a/src/vendorcode/amd/agesa/f14/Proc/Mem/NB/ON/mnon.c +++ b/src/vendorcode/amd/agesa/f14/Proc/Mem/NB/ON/mnon.c @@ -9,7 +9,7 @@ * @xrefitem bom "File Content Label" "Release Content" * @e project: AGESA * @e sub-project: (Mem/NB/ON) - * @e \$Revision: 40406 $ @e \$Date: 2010-10-22 00:02:12 +0800 (Fri, 22 Oct 2010) $ + * @e \$Revision: 48511 $ @e \$Date: 2011-03-09 13:53:13 -0700 (Wed, 09 Mar 2011) $ * **/ /* @@ -251,7 +251,7 @@ MemConstructNBBlockON ( NBPtr->GetSocketRelativeChannel = MemNGetSocketRelativeChannelNb; NBPtr->TechBlockSwitch = MemNTechBlockSwitchON; NBPtr->SetEccSymbolSize = (VOID (*) (MEM_NB_BLOCK *)) memDefRet; - NBPtr->TrainingFlow = memNTrainFlowControl[DDR3_TRAIN_FLOW]; + NBPtr->TrainingFlow = (VOID (*) (MEM_NB_BLOCK *)) memNTrainFlowControl[DDR3_TRAIN_FLOW]; NBPtr->MinDataEyeWidth = MemNMinDataEyeWidthNb; NBPtr->PollBitField = MemNPollBitFieldNb; NBPtr->BrdcstCheck = MemNBrdcstCheckON; @@ -301,13 +301,21 @@ MemConstructNBBlockON ( NBPtr->IsSupported[AdjustTwr] = TRUE; NBPtr->IsSupported[UnifiedNbFence] = TRUE; NBPtr->IsSupported[ChannelPDMode] = TRUE; // Erratum 435 + if ((NBPtr->MCTPtr->LogicalCpuid.Revision & AMD_F14_ON_C0) != 0) { + NBPtr->IsSupported[AdjustTrc] = TRUE; + } NBPtr->FamilySpecificHook[OverrideRcvEnSeed] = MemNOverrideRcvEnSeedON; NBPtr->FamilySpecificHook[BeforePhyFenceTraining] = MemNBeforePhyFenceTrainingClientNb; NBPtr->FamilySpecificHook[AdjustTxpdll] = MemNAdjustTxpdllClientNb; + if ((NBPtr->MCTPtr->LogicalCpuid.Revision & AMD_F14_ON_Cx) == 0) { + // Do not do phase B enforcement for Rev C NBPtr->FamilySpecificHook[ForceRdDqsPhaseB] = MemNForceRdDqsPhaseBON; + } NBPtr->FamilySpecificHook[SetDqsODT] = MemNSetDqsODTON; NBPtr->FamilySpecificHook[ResetRxFifoPtr] = MemNResetRxFifoPtrON; + NBPtr->FamilySpecificHook[BfAfExcludeDimm] = MemNBfAfExcludeDimmClientNb; + NBPtr->FamilySpecificHook[BeforeMemClkFreqVal] = MemNBeforeMemClkFreqValON; FeatPtr->InitCPG (NBPtr); FeatPtr->InitEarlySampleSupport (NBPtr); diff --git a/src/vendorcode/amd/agesa/f14/Proc/Mem/NB/ON/mnon.h b/src/vendorcode/amd/agesa/f14/Proc/Mem/NB/ON/mnon.h index e5f8683d36..1523cd6218 100644 --- a/src/vendorcode/amd/agesa/f14/Proc/Mem/NB/ON/mnon.h +++ b/src/vendorcode/amd/agesa/f14/Proc/Mem/NB/ON/mnon.h @@ -9,7 +9,7 @@ * @xrefitem bom "File Content Label" "Release Content" * @e project: AGESA * @e sub-project: (Mem) - * @e \$Revision: 37115 $ @e \$Date: 2010-08-31 07:10:42 +0800 (Tue, 31 Aug 2010) $ + * @e \$Revision: 48511 $ @e \$Date: 2011-03-09 13:53:13 -0700 (Wed, 09 Mar 2011) $ * **/ /* @@ -241,6 +241,12 @@ MemNSetDqsODTON ( ); BOOLEAN +MemNBeforeMemClkFreqValON ( + IN OUT MEM_NB_BLOCK *NBPtr, + IN OUT VOID *OptParam + ); + +BOOLEAN MemNResetRxFifoPtrON ( IN OUT MEM_NB_BLOCK *NBPtr, IN OUT VOID *OptParam diff --git a/src/vendorcode/amd/agesa/f14/Proc/Mem/NB/ON/mnprotoon.c b/src/vendorcode/amd/agesa/f14/Proc/Mem/NB/ON/mnprotoon.c index d8c9c9df59..7f60a98ef9 100644 --- a/src/vendorcode/amd/agesa/f14/Proc/Mem/NB/ON/mnprotoon.c +++ b/src/vendorcode/amd/agesa/f14/Proc/Mem/NB/ON/mnprotoon.c @@ -80,6 +80,11 @@ MemNDetectMemPllErrorON ( * *----------------------------------------------------------------------------- */ +VOID +MemNInitEarlySampleSupportON ( + IN OUT MEM_NB_BLOCK *NBPtr + ); + /* -----------------------------------------------------------------------------*/ /** * diff --git a/src/vendorcode/amd/agesa/f14/Proc/Mem/NB/ON/mnregon.c b/src/vendorcode/amd/agesa/f14/Proc/Mem/NB/ON/mnregon.c index 3f99b2c590..f85e56dc17 100644 --- a/src/vendorcode/amd/agesa/f14/Proc/Mem/NB/ON/mnregon.c +++ b/src/vendorcode/amd/agesa/f14/Proc/Mem/NB/ON/mnregon.c @@ -9,7 +9,7 @@ * @xrefitem bom "File Content Label" "Release Content" * @e project: AGESA * @e sub-project: (Mem/NB/ON) - * @e \$Revision: 39747 $ @e \$Date: 2010-10-15 02:58:08 +0800 (Fri, 15 Oct 2010) $ + * @e \$Revision: 48511 $ @e \$Date: 2011-03-09 13:53:13 -0700 (Wed, 09 Mar 2011) $ * **/ /* @@ -348,6 +348,7 @@ MemNInitNBRegTableON ( MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (1, 0xF0), 31, 24, BFDramHoleBase); MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (1, 0xF0), 15, 7, BFDramHoleOffset); MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (1, 0xF0), 0, 0, BFDramHoleValid); + MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (1, 0xF0), 31, 0, BFDramHoleAddrReg); MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x40), 31, 0, BFCSBaseAddr0Reg); MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x44), 31, 0, BFCSBaseAddr1Reg); @@ -486,6 +487,7 @@ MemNInitNBRegTableON ( MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (4, 0x1A8), 25, 25, BFMemTriStateEn); MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (4, 0x1A8), 24, 24, BFDramSrEn); MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (3, 0x84), 31, 0, BFAcpiPwrStsCtrlHi); + MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (3, 0x1FC), 2, 2, BFLowPowerDefault); MAKE_TSEFO (NBRegTable, DCT_PHY_ACCESS, 0x00, 2, 0, BFCkeDrvStren); MAKE_TSEFO (NBRegTable, DCT_PHY_ACCESS, 0x00, 6, 4, BFCsOdtDrvStren); @@ -561,10 +563,15 @@ MemNInitNBRegTableON ( MAKE_TSEFO (NBRegTable, DCT_PHY_DIRECT, 0x0D0F8F1F, 4, 3, BFCmdRxVioLvl); MAKE_TSEFO (NBRegTable, DCT_PHY_DIRECT, 0x0D0FC01F, 4, 3, BFAddrRxVioLvl); - MAKE_TSEFO (NBRegTable, DCT_PHY_DIRECT, 0x0D080F0C, 15, 0, BFPhy0x0D080F0C); MAKE_TSEFO (NBRegTable, DCT_PHY_DIRECT, 0x0D0F0F00, 6, 4, BFDQOdt03); MAKE_TSEFO (NBRegTable, DCT_PHY_DIRECT, 0x0D0F0F08, 6, 4, BFDQOdt47); + MAKE_TSEFO (NBRegTable, DCT_PHY_DIRECT, 0x0D0F0F1E, 14, 12, BFDllCSRBisaTrimDByte); + MAKE_TSEFO (NBRegTable, DCT_PHY_DIRECT, 0x0D0F2F1E, 14, 12, BFDllCSRBisaTrimClk); + MAKE_TSEFO (NBRegTable, DCT_PHY_DIRECT, 0x0D0F8F1E, 14, 12, BFDllCSRBisaTrimCsOdt); + MAKE_TSEFO (NBRegTable, DCT_PHY_DIRECT, 0x0D0FCF1E, 14, 12, BFDllCSRBisaTrimAByte2); + MAKE_TSEFO (NBRegTable, DCT_PHY_DIRECT, 0x0D0F0F38, 14, 13, BFReduceLoop); + MAKE_TSEFO (NBRegTable, DCT_EXTRA, 0x06, 11, 8, BFTwrrdSD); MAKE_TSEFO (NBRegTable, DCT_EXTRA, 0x06, 3, 0, BFTrdrdSD); MAKE_TSEFO (NBRegTable, DCT_EXTRA, 0x16, 3, 0, BFTwrwrSD); diff --git a/src/vendorcode/amd/agesa/f14/Proc/Mem/NB/mndct.c b/src/vendorcode/amd/agesa/f14/Proc/Mem/NB/mndct.c index 32d6f2ce3e..ac103497f6 100644 --- a/src/vendorcode/amd/agesa/f14/Proc/Mem/NB/mndct.c +++ b/src/vendorcode/amd/agesa/f14/Proc/Mem/NB/mndct.c @@ -9,7 +9,7 @@ * @xrefitem bom "File Content Label" "Release Content" * @e project: AGESA * @e sub-project: (Mem/NB) - * @e \$Revision: 38442 $ @e \$Date: 2010-09-24 06:39:57 +0800 (Fri, 24 Sep 2010) $ + * @e \$Revision: 48511 $ @e \$Date: 2011-03-09 13:53:13 -0700 (Wed, 09 Mar 2011) $ * **/ /* @@ -978,6 +978,10 @@ MemNProgramCycTimingsClientNb ( Value8 = (Value8 >= 10) ? (((Value8 + 1) / 2) + 4) : Value8; } + if ((BitField == BFTrc) && NBPtr->IsSupported[AdjustTrc]) { + Value8 -= 5; + } + Value8 = Value8 - TmgAdjTab[j].Bias; Value8 = (Value8 * TmgAdjTab[j].Ratio_x2) >> 1; @@ -986,7 +990,7 @@ MemNProgramCycTimingsClientNb ( (BitField == BFTrp ) ? (Value8 <= 9) : (BitField == BFTrtp) ? (Value8 <= 4) : (BitField == BFTras) ? (Value8 <= 21) : - (BitField == BFTrc ) ? ((Value8 >= 9) && (Value8 <= 38)) : + (BitField == BFTrc ) ? (NBPtr->IsSupported[AdjustTrc] ? ((Value8 >= 4) && (Value8 <= 38)) : ((Value8 >= 9) && (Value8 <= 38))) : (BitField == BFTrrd) ? (Value8 <= 4) : (BitField == BFTwtr) ? (Value8 <= 4) : (BitField == BFTwrDDR3) ? (Value8 <= 7) : @@ -1857,6 +1861,7 @@ MemNChangeFrequencyUnb ( // THEN 2 ELSE 3 ENDIF (Ontario) NBPtr->ProgramNbPsDependentRegs (NBPtr); + NBPtr->FamilySpecificHook[BeforeMemClkFreqVal] (NBPtr, NBPtr); IDS_OPTION_HOOK (IDS_BEFORE_MEM_FREQ_CHG, NBPtr, &(NBPtr->MemPtr->StdHeader)); // 7. Program D18F2x[1,0]94[MemClkFreqVal] = 1. MemNBrdcstSetNb (NBPtr, BFMemClkFreqVal, 1); diff --git a/src/vendorcode/amd/agesa/f14/Proc/Mem/NB/mnfeat.c b/src/vendorcode/amd/agesa/f14/Proc/Mem/NB/mnfeat.c index 0779531ac4..d806fa5544 100644 --- a/src/vendorcode/amd/agesa/f14/Proc/Mem/NB/mnfeat.c +++ b/src/vendorcode/amd/agesa/f14/Proc/Mem/NB/mnfeat.c @@ -87,6 +87,21 @@ RDATA_GROUP (G1_PEICC) */ VOID +MemNInitCPGNb ( + IN OUT MEM_NB_BLOCK *NBPtr + ); + +VOID +MemNInitDqsTrainRcvrEnHwNb ( + IN OUT MEM_NB_BLOCK *NBPtr + ); + +VOID +MemNDisableDqsTrainRcvrEnHwNb ( + IN OUT MEM_NB_BLOCK *NBPtr + ); + +VOID STATIC MemNContWritePatternNb ( IN OUT MEM_NB_BLOCK *NBPtr, @@ -203,6 +218,16 @@ MemNContWritePatternUnb ( IN UINT16 ClCount ); +VOID +MemNInitCPGClientNb ( + IN OUT MEM_NB_BLOCK *NBPtr + ); + +VOID +MemNInitCPGUnb ( + IN OUT MEM_NB_BLOCK *NBPtr + ); + /*---------------------------------------------------------------------------- * EXPORTED FUNCTIONS * @@ -924,7 +949,7 @@ MemNGenHwRcvEnReadsUnb ( // // Issue Stream of Reads from the Target Rank // - NBPtr->ReadPattern (NBPtr, DummyPtr, NULL, NBPtr->TechPtr->PatternLength); + NBPtr->ReadPattern (NBPtr, DummyPtr, 0, NBPtr->TechPtr->PatternLength); } /* -----------------------------------------------------------------------------*/ diff --git a/src/vendorcode/amd/agesa/f14/Proc/Mem/NB/mnmct.c b/src/vendorcode/amd/agesa/f14/Proc/Mem/NB/mnmct.c index c6fe85045d..613aadd936 100644 --- a/src/vendorcode/amd/agesa/f14/Proc/Mem/NB/mnmct.c +++ b/src/vendorcode/amd/agesa/f14/Proc/Mem/NB/mnmct.c @@ -9,7 +9,7 @@ * @xrefitem bom "File Content Label" "Release Content" * @e project: AGESA * @e sub-project: (Mem/NB) - * @e \$Revision: 39420 $ @e \$Date: 2010-10-12 00:52:49 +0800 (Tue, 12 Oct 2010) $ + * @e \$Revision: 48496 $ @e \$Date: 2011-03-09 12:26:48 -0700 (Wed, 09 Mar 2011) $ * **/ /* @@ -130,7 +130,6 @@ MemNSyncTargetSpeedNb ( { CONST UINT16 DdrMaxRateTab[] = { UNSUPPORTED_DDR_FREQUENCY, - DDR1866_FREQUENCY, DDR1600_FREQUENCY, DDR1333_FREQUENCY, DDR1066_FREQUENCY, @@ -185,8 +184,8 @@ MemNSyncTargetSpeedNb ( Mode[Dct] = ChnlTmgMod[0]; // Check if input clock value is valid or not ASSERT ((NBPtr->ChannelPtr->TechType == DDR3_TECHNOLOGY) ? - (ChnlTmgMod[1] >= DDR667_FREQUENCY) : - (ChnlTmgMod[1] <= DDR1066_FREQUENCY)); + ((MEMORY_BUS_SPEED)(ChnlTmgMod[1]) >= DDR667_FREQUENCY) : + ((MEMORY_BUS_SPEED)(ChnlTmgMod[1]) <= DDR1066_FREQUENCY)); MemClkFreq = ChnlTmgMod[1]; } } @@ -1182,3 +1181,39 @@ MemNGetMaxDdrRateUnb ( * (UINT16 * ) DdrMaxRate = MemNGetMemClkFreqUnb (NBPtr, (UINT8) MemNGetBitFieldNb (NBPtr, BFDdrMaxRate)); return TRUE; } + +/* -----------------------------------------------------------------------------*/ +/** + * + * + * This function performs the action before and after excluding dimms on CNB + * + * @param[in,out] *NBPtr - Pointer to the MEM_NB_BLOCK + * @param[in,out] *IsBefore - If the function is called before excluding dimms + * + * @return TRUE + * + */ + +BOOLEAN +MemNBfAfExcludeDimmClientNb ( + IN OUT MEM_NB_BLOCK *NBPtr, + IN OUT VOID *IsBefore + ) +{ + if (*(BOOLEAN *) IsBefore == TRUE) { + NBPtr->BrdcstSet (NBPtr, BFEnterSelfRef, 1); + NBPtr->PollBitField (NBPtr, BFEnterSelfRef, 0, PCI_ACCESS_TIMEOUT, TRUE); + } else { + NBPtr->BrdcstSet (NBPtr, BFExitSelfRef, 1); + NBPtr->PollBitField (NBPtr, BFExitSelfRef, 0, PCI_ACCESS_TIMEOUT, TRUE); + } + + return TRUE; +} + +/*---------------------------------------------------------------------------- + * LOCAL FUNCTIONS + * + *---------------------------------------------------------------------------- + */ diff --git a/src/vendorcode/amd/agesa/f14/Proc/Mem/Ps/ON/mpson3.c b/src/vendorcode/amd/agesa/f14/Proc/Mem/Ps/ON/mpson3.c index 4aa2969d83..18298b831b 100644 --- a/src/vendorcode/amd/agesa/f14/Proc/Mem/Ps/ON/mpson3.c +++ b/src/vendorcode/amd/agesa/f14/Proc/Mem/Ps/ON/mpson3.c @@ -9,7 +9,7 @@ * @xrefitem bom "File Content Label" "Release Content" * @e project: AGESA * @e sub-project: (Mem/Ps/ON) - * @e \$Revision: 38634 $ @e \$Date: 2010-09-27 21:39:01 +0800 (Mon, 27 Sep 2010) $ + * @e \$Revision: 46937 $ @e \$Date: 2011-02-11 08:50:58 -0700 (Fri, 11 Feb 2011) $ * **/ /* @@ -131,7 +131,14 @@ MemPConstructPsSON3 ( return AGESA_UNSUPPORTED; } PsPtr->MemPDoPs = MemPDoPsSON3; + + if ((ChannelPtr->MCTPtr->LogicalCpuid.Revision & AMD_F14_ON_Cx) == 0) { PsPtr->MemPGetPORFreqLimit = MemPGetPORFreqLimitSON3; + } else { + // Do not force frequency limit for Rev C + PsPtr->MemPGetPORFreqLimit = (VOID (*) (MEM_NB_BLOCK *)) memDefRet; + } + return AGESA_SUCCESS; } diff --git a/src/vendorcode/amd/agesa/f14/Proc/Mem/Ps/ON/mpuon3.c b/src/vendorcode/amd/agesa/f14/Proc/Mem/Ps/ON/mpuon3.c index 6e62cc0f08..41f0df01df 100644 --- a/src/vendorcode/amd/agesa/f14/Proc/Mem/Ps/ON/mpuon3.c +++ b/src/vendorcode/amd/agesa/f14/Proc/Mem/Ps/ON/mpuon3.c @@ -9,7 +9,7 @@ * @xrefitem bom "File Content Label" "Release Content" * @e project: AGESA * @e sub-project: (Mem/Ps/ON) - * @e \$Revision: 38634 $ @e \$Date: 2010-09-27 21:39:01 +0800 (Mon, 27 Sep 2010) $ + * @e \$Revision: 46937 $ @e \$Date: 2011-02-11 08:50:58 -0700 (Fri, 11 Feb 2011) $ * **/ /* @@ -132,7 +132,14 @@ MemPConstructPsUON3 ( return AGESA_UNSUPPORTED; } PsPtr->MemPDoPs = MemPDoPsUON3; + + if ((ChannelPtr->MCTPtr->LogicalCpuid.Revision & AMD_F14_ON_Cx) == 0) { PsPtr->MemPGetPORFreqLimit = MemPGetPORFreqLimitUON3; + } else { + // Do not force frequency limit for Rev C + PsPtr->MemPGetPORFreqLimit = (VOID (*) (MEM_NB_BLOCK *)) memDefRet; + } + return AGESA_SUCCESS; } diff --git a/src/vendorcode/amd/agesa/f14/Proc/Mem/Tech/DDR3/mtrci3.c b/src/vendorcode/amd/agesa/f14/Proc/Mem/Tech/DDR3/mtrci3.c index 106f501948..21c8ad9261 100644 --- a/src/vendorcode/amd/agesa/f14/Proc/Mem/Tech/DDR3/mtrci3.c +++ b/src/vendorcode/amd/agesa/f14/Proc/Mem/Tech/DDR3/mtrci3.c @@ -59,6 +59,7 @@ #include "mn.h" #include "mu.h" #include "mt.h" +#include "mt3.h" #include "mtrci3.h" #include "merrhdl.h" #include "Filecode.h" diff --git a/src/vendorcode/amd/agesa/f14/Proc/Mem/mm.h b/src/vendorcode/amd/agesa/f14/Proc/Mem/mm.h index 6497ea33cc..f8d853726e 100644 --- a/src/vendorcode/amd/agesa/f14/Proc/Mem/mm.h +++ b/src/vendorcode/amd/agesa/f14/Proc/Mem/mm.h @@ -9,7 +9,7 @@ * @xrefitem bom "File Content Label" "Release Content" * @e project: AGESA * @e sub-project: (Mem) - * @e \$Revision: 38634 $ @e \$Date: 2010-09-27 21:39:01 +0800 (Mon, 27 Sep 2010) $ + * @e \$Revision: 48511 $ @e \$Date: 2011-03-09 13:53:13 -0700 (Wed, 09 Mar 2011) $ * **/ /* @@ -229,6 +229,7 @@ typedef enum { BFSRT, ///< Bit field SRT BFTcwl, ///< Bit field Tcwl BFPchgPDModeSel, ///< Bit field PchgPDModeSel + BFLowPowerDefault, ///< Bit field LowPowerDefault BFTwrDDR3, ///< Bit field TwrDDR3 BFTcl, ///< Bit field Tcl @@ -665,6 +666,12 @@ typedef enum { BFFixedErrataSkipPorFreqCap, ///< Bit field FixedErrataSkipPorFreqCap + BFDllCSRBisaTrimDByte, ///< Bit field DllCSRBisaTrimDByte + BFDllCSRBisaTrimClk, ///< Bit field DllCSRBisaTrimClk + BFDllCSRBisaTrimCsOdt, ///< Bit field DllCSRBisaTrimCsOdt + BFDllCSRBisaTrimAByte2, ///< Bit field DllCSRBisaTrimAByte2 + BFReduceLoop, ///< Bit field ReduceLoop + // Reserved BFReserved01, ///< Reserved 01 BFReserved02, ///< Reserved 02 @@ -983,11 +990,11 @@ AmdMemInitDataStructDefRecovery ( IN OUT MEM_DATA_STRUCT *MemPtr ); -VOID -MemRecDefRet (VOID); +//VOID +//MemRecDefRet (VOID); -BOOLEAN -MemRecDefTrue (VOID); +//BOOLEAN +//MemRecDefTrue (VOID); VOID SetMemRecError ( diff --git a/src/vendorcode/amd/agesa/f14/Proc/Mem/mn.h b/src/vendorcode/amd/agesa/f14/Proc/Mem/mn.h index 8a06566f18..1f2f0b0497 100644 --- a/src/vendorcode/amd/agesa/f14/Proc/Mem/mn.h +++ b/src/vendorcode/amd/agesa/f14/Proc/Mem/mn.h @@ -9,7 +9,7 @@ * @xrefitem bom "File Content Label" "Release Content" * @e project: AGESA * @e sub-project: (Mem) - * @e \$Revision: 38303 $ @e \$Date: 2010-09-22 00:22:47 +0800 (Wed, 22 Sep 2010) $ + * @e \$Revision: 48803 $ @e \$Date: 2011-03-10 20:18:28 -0700 (Thu, 10 Mar 2011) $ * **/ /* @@ -394,6 +394,7 @@ typedef enum { WLNegativeDelay, ///< Check to determine if the NB can tolerate a negtive WL delay value SchedDlySlot1Extra, ///< Check to determine if DataTxSchedDly Slot1 equation in slowMode to subtract an extra MEMCLK TwoStageDramInit, ///< Check to determine if we need to seperate Draminit into 2 stages. The first one processes info on all nodes. The second one does Dram Init. + AdjustTrc, ///< Check to determine if we need to adjust Trc EnumSize ///< Size of list } NB_SUPPORTED; @@ -401,6 +402,7 @@ typedef enum { /// List for family specific functions that are supported typedef enum { BeforePhyFenceTraining, ///< Family specific tasks before Phy Fence Training + BeforeMemClkFreqVal, ///< hook before setting MemClkFreqVal bit AfterMemClkFreqVal, ///< Override PllMult and PllDiv OverridePllMult, ///< Override PllMult OverridePllDiv, ///< Override PllDiv @@ -439,6 +441,7 @@ typedef enum { ResetRxFifoPtr, ///< Reset RxFifo pointer during Read DQS training EnableParityAfterMemRst, ///< Enable DRAM Address Parity after memory reset. FinalizeVDDIO, ///< Finalize VDDIO + BfAfExcludeDimm, ///< Workaround before and after excluding dimms NumberOfHooks ///< Size of list } FAMILY_SPECIFIC_FUNC_INDEX; @@ -502,6 +505,7 @@ typedef struct _MEM_NB_BLOCK { BOOLEAN ClToNbFlag; ///< is used to restore ClLinesToNbDis bit after memory UINT8 NbFreqChgState; ///< is used as a state index in NB frequency change state machine UINT32 NbPsCtlReg; ///< is used to save/restore NB Pstate control register + CONST UINT32 *RecModeDefRegArray; ///< points to an array of default register values that are set for recovery mode ///< Determines if code should be executed on a give NB BOOLEAN IsSupported[EnumSize]; @@ -1345,6 +1349,15 @@ MemRecNReEnablePhyCompNb ( IN OUT VOID *OptParam ); +UINT32 +MemRecNcmnGetSetTrainDlyClientNb ( + IN OUT MEM_NB_BLOCK *NBPtr, + IN UINT8 IsSet, + IN TRN_DLY_TYPE TrnDly, + IN DRBN DrbnVar, + IN UINT16 Field + ); + VOID MemNSetTxpNb ( IN OUT MEM_NB_BLOCK *NBPtr @@ -1369,6 +1382,12 @@ MemNGetTrainDlyParmsUnb ( IN OUT TRN_DLY_PARMS *Parms ); +BOOLEAN +MemNBfAfExcludeDimmClientNb ( + IN OUT MEM_NB_BLOCK *NBPtr, + IN OUT VOID *IsBefore + ); + #endif /* _MN_H_ */ diff --git a/src/vendorcode/amd/agesa/f14/Proc/Recovery/Mem/NB/ON/mrndcton.c b/src/vendorcode/amd/agesa/f14/Proc/Recovery/Mem/NB/ON/mrndcton.c index e90de93b84..03ef12ed28 100644 --- a/src/vendorcode/amd/agesa/f14/Proc/Recovery/Mem/NB/ON/mrndcton.c +++ b/src/vendorcode/amd/agesa/f14/Proc/Recovery/Mem/NB/ON/mrndcton.c @@ -9,7 +9,7 @@ * @xrefitem bom "File Content Label" "Release Content" * @e project: AGESA * @e sub-project: (Proc/Recovery/Mem) - * @e \$Revision: 34897 $ @e \$Date: 2010-07-14 10:07:10 +0800 (Wed, 14 Jul 2010) $ + * @e \$Revision: 48803 $ @e \$Date: 2011-03-10 20:18:28 -0700 (Thu, 10 Mar 2011) $ * **/ /* @@ -73,18 +73,12 @@ * *---------------------------------------------------------------------------- */ -#define RECDEF_DRAM_CONTROL_REG 0x14042A03 -#define RECDEF_DRAM_MRSREG 0x000400A5 -#define RECDEF_DRAM_TIMING_LO 0x000A0092 -#define RECDEF_DRAM_TIMING_HI 0x001218FF #define RECDEF_CSMASK_REG 0x00003FE0 -#define RECDEF_DRAM_CONFIG_LO_REG 0x30000000 -#define RECDEF_DRAM_CONFIG_HI_REG 0x1E000000 #define RECDEF_DRAM_BASE_REG 0x00000003 -#define RECDEF_DRAM_TIMING_0 0x0A000101 -#define RECDEF_DRAM_TIMING_1 0 #define MAX_RD_DQS_DLY 0x1F +#define DEFAULT_WR_ODT_ON_ON 6 +#define DEFAULT_RD_ODT_ON_ON 6 /*---------------------------------------------------------------------------- * TYPEDEFS AND STRUCTURES * @@ -126,6 +120,8 @@ MemRecNPlatformSpecON ( { UINT32 AddrTmgValue; UINT32 DrvStrValue; + UINT32 RODTCSLow; + UINT32 WODTCSLow; CH_DEF_STRUCT *ChannelPtr; ChannelPtr = NBPtr->ChannelPtr; @@ -133,10 +129,10 @@ MemRecNPlatformSpecON ( // SODIMM if (ChannelPtr->Dimms == 2) { AddrTmgValue = 0x00000039; - DrvStrValue = 0x30222323; + DrvStrValue = 0x20222323; } else { AddrTmgValue = 0; - DrvStrValue = 0x00002222; + DrvStrValue = 0x00002223; } } else { // UDIMM @@ -153,6 +149,23 @@ MemRecNPlatformSpecON ( } MemRecNSetBitFieldNb (NBPtr, BFODCControl, DrvStrValue); MemRecNSetBitFieldNb (NBPtr, BFAddrTmgControl, AddrTmgValue); + RODTCSLow = 0; + if (ChannelPtr->Dimms == 2) { + RODTCSLow = 0x01010404; + WODTCSLow = 0x09050605; + } else if (NBPtr->ChannelPtr->DimmDrPresent != 0) { + WODTCSLow = 0x00000201; + if (NBPtr->DimmToBeUsed == 1) { + WODTCSLow = 0x08040000; + } + } else { + WODTCSLow = 0x00000001; + if (NBPtr->DimmToBeUsed == 1) { + WODTCSLow = 0x00040000; + } + } + MemRecNSetBitFieldNb (NBPtr, BFPhyRODTCSLow, RODTCSLow); + MemRecNSetBitFieldNb (NBPtr, BFPhyWODTCSLow, WODTCSLow); return TRUE; } @@ -239,7 +252,9 @@ MemRecNSetDramOdtON ( if (OdtMode == WRITE_LEVELING_MODE) { if (ChipSelect == TargetCS) { + if (Dimms >= 2) { DramTerm = DramTermDyn; + } MaxDimmsPerChannel = RecGetMaxDimmsPerChannel (NBPtr->RefPtr->PlatformMemoryConfiguration, 0, NBPtr->ChannelPtr->ChannelID); @@ -249,7 +264,7 @@ MemRecNSetDramOdtON ( } else { // Dimms = 1 if (TargetCS == 0) { - WrLvOdt = 0xF; + WrLvOdt = 1; } else { // TargetCS = 2 WrLvOdt = 4; @@ -286,6 +301,7 @@ MemRecNAutoConfigON ( UINT8 ChipSel; UINT32 CSBase; UINT32 NBClkFreq; + UINT8 i; DCT_STRUCT *DCTPtr; CH_DEF_STRUCT *ChannelPtr; @@ -298,7 +314,6 @@ MemRecNAutoConfigON ( 0, &NBClkFreq, &(NBPtr->MemPtr->StdHeader)); - NBPtr->NBClkFreq = NBClkFreq; MemRecNSetBitFieldNb (NBPtr, BFNbPsCtrlDis, 1); //Prepare variables for future usage. @@ -331,29 +346,74 @@ MemRecNAutoConfigON ( } MemRecNSetBitFieldNb (NBPtr, BFDramBaseReg0, RECDEF_DRAM_BASE_REG); MemRecNSetBitFieldNb (NBPtr, BFDramLimitReg0, 0x70000); - MemRecNSetBitFieldNb (NBPtr, BFDramBankAddrReg, 0x00000011); - - // Set timing registers - MemRecNSetBitFieldNb (NBPtr, BFDramTiming0, RECDEF_DRAM_TIMING_0); - MemRecNSetBitFieldNb (NBPtr, BFDramTiming1, RECDEF_DRAM_TIMING_1); - MemRecNSetBitFieldNb (NBPtr, BFDramTimingLoReg, RECDEF_DRAM_TIMING_LO); - MemRecNSetBitFieldNb (NBPtr, BFDramTimingHiReg, RECDEF_DRAM_TIMING_HI); - MemRecNSetBitFieldNb (NBPtr, BFDramMRSReg, RECDEF_DRAM_MRSREG); - MemRecNSetBitFieldNb (NBPtr, BFDramControlReg, RECDEF_DRAM_CONTROL_REG); - // Set DRAM Config Low Register - MemRecNSetBitFieldNb (NBPtr, BFDramConfigLoReg, RECDEF_DRAM_CONFIG_LO_REG); - - // Set DRAM Config High Register - MemRecNSetBitFieldNb (NBPtr, BFDramConfigHiReg, RECDEF_DRAM_CONFIG_HI_REG); - - // DctWrLimit = 0x1F + + // Use default values for common registers + i = 0; + while (NBPtr->RecModeDefRegArray[i] != NULL) { + MemRecNSetBitFieldNb (NBPtr, NBPtr->RecModeDefRegArray[i], NBPtr->RecModeDefRegArray[i + 1]); + i += 2; + } + + //====================================================================== + // Build Dram Config Misc Register Value + //====================================================================== + // + // Max out Non-SPD timings + MemRecNSetBitFieldNb (NBPtr, BFTwrrdSD, 0xA); + MemRecNSetBitFieldNb (NBPtr, BFTrdrdSD, 0x8); + MemRecNSetBitFieldNb (NBPtr, BFTwrwrSD, 0x9); + + MemRecNSetBitFieldNb (NBPtr, BFWrOdtOnDuration, DEFAULT_WR_ODT_ON_ON); + MemRecNSetBitFieldNb (NBPtr, BFRdOdtOnDuration, DEFAULT_RD_ODT_ON_ON); + MemRecNSetBitFieldNb (NBPtr, BFWrOdtTrnOnDly, 0); + + MemRecNSetBitFieldNb (NBPtr, BFRdOdtTrnOnDly, 6 - 5); + //====================================================================== + // DRAM MRS Register, set ODT + //====================================================================== + MemRecNSetBitFieldNb (NBPtr, BFBurstCtrl, 1); + + // + // Recommended registers setting BEFORE DRAM device initialization and training + // + MemRecNSetBitFieldNb (NBPtr, BFDisAutoRefresh, 1); + MemRecNSetBitFieldNb (NBPtr, BFZqcsInterval, 0); + MemRecNSetBitFieldNb (NBPtr, BFRxMaxDurDllNoLock, 0); + MemRecNSetBitFieldNb (NBPtr, BFTxMaxDurDllNoLock, 0); + MemRecNSetBitFieldNb (NBPtr, BFEnRxPadStandby, 0); + MemRecNSetBitFieldNb (NBPtr, BFPrefCpuDis, 1); MemRecNSetBitFieldNb (NBPtr, BFDctWrLimit, 0x1F); - // EnCpuSerRdBehindNpIoWr = 1 MemRecNSetBitFieldNb (NBPtr, BFEnCpuSerRdBehindNpIoWr, 1); + MemRecNSetBitFieldNb (NBPtr, BFDbeGskMemClkAlignMode, 0); + MemRecNSetBitFieldNb (NBPtr, BFMaxLatency, 0x12); + MemRecNSetBitFieldNb (NBPtr, BFTraceModeEn, 0); + + // Enable cut through mode for NB P0 + MemRecNSetBitFieldNb (NBPtr, BFDisCutThroughMode, 0); return TRUE; } +/* -----------------------------------------------------------------------------*/ +/** + * + * This function overrides the seed for hardware based RcvEn training of Ontario. + * + * @param[in,out] *NBPtr - Pointer to the MEM_NB_BLOCK + * @param[in,out] *SeedPtr - Pointer to the seed value. + * + * @return TRUE + */ + +BOOLEAN +MemRecNOverrideRcvEnSeedON ( + IN OUT MEM_NB_BLOCK *NBPtr, + IN OUT VOID *SeedPtr + ) +{ + *(UINT16*) SeedPtr = 0x5B; + return TRUE; +} /*---------------------------------------------------------------------------- * LOCAL FUNCTIONS * diff --git a/src/vendorcode/amd/agesa/f14/Proc/Recovery/Mem/NB/ON/mrnmcton.c b/src/vendorcode/amd/agesa/f14/Proc/Recovery/Mem/NB/ON/mrnmcton.c index df1d5d8e40..b181e4a27d 100644 --- a/src/vendorcode/amd/agesa/f14/Proc/Recovery/Mem/NB/ON/mrnmcton.c +++ b/src/vendorcode/amd/agesa/f14/Proc/Recovery/Mem/NB/ON/mrnmcton.c @@ -9,7 +9,7 @@ * @xrefitem bom "File Content Label" "Release Content" * @e project: AGESA * @e sub-project: (Proc/Recovery/Mem) - * @e \$Revision: 34897 $ @e \$Date: 2010-07-14 10:07:10 +0800 (Wed, 14 Jul 2010) $ + * @e \$Revision: 48803 $ @e \$Date: 2011-03-10 20:18:28 -0700 (Thu, 10 Mar 2011) $ * **/ /* @@ -80,7 +80,11 @@ * *---------------------------------------------------------------------------- */ - +VOID +STATIC +MemRecNFinalizeMctON ( + IN OUT MEM_NB_BLOCK *NBPtr + ); /*---------------------------------------------------------------------------- * EXPORTED FUNCTIONS @@ -134,6 +138,8 @@ MemRecNMemInitON ( } } + MemRecNFinalizeMctON (NBPtr); + return Status; } @@ -147,6 +153,7 @@ MemRecNMemInitON ( */ VOID +STATIC MemRecNFinalizeMctON ( IN OUT MEM_NB_BLOCK *NBPtr ) @@ -154,36 +161,16 @@ MemRecNFinalizeMctON ( // // Recommended registers setting after DRAM device initialization and training // - // PrefCpuDis = 0 + MemRecNSetBitFieldNb (NBPtr, BFAddrCmdTriEn, 1); + MemRecNSetBitFieldNb (NBPtr, BFDisAutoRefresh, 0); + MemRecNSetBitFieldNb (NBPtr, BFZqcsInterval, 2); + MemRecNSetBitFieldNb (NBPtr, BFEnRxPadStandby, 0x1000); MemRecNSetBitFieldNb (NBPtr, BFPrefCpuDis, 0); - // DctWrLimit = 0x1C MemRecNSetBitFieldNb (NBPtr, BFDctWrLimit, 0x1C); - // DramTrainPdbDis = 1 MemRecNSetBitFieldNb (NBPtr, BFDramTrainPdbDis, 1); - // EnCpuSerRdBehindNpIoWr = 0 MemRecNSetBitFieldNb (NBPtr, BFEnCpuSerRdBehindNpIoWr, 0); } -/* -----------------------------------------------------------------------------*/ -/** - * - * This function sets initial values in BUCFG2 - * - * @param[in,out] *NBPtr - Pointer to the MEM_NB_BLOCK - * - */ - -VOID -MemRecNInitializeMctON ( - IN OUT MEM_NB_BLOCK *NBPtr - ) -{ -} - -/* -----------------------------------------------------------------------------*/ -/** - * - /*---------------------------------------------------------------------------- * LOCAL FUNCTIONS * diff --git a/src/vendorcode/amd/agesa/f14/Proc/Recovery/Mem/NB/ON/mrnon.c b/src/vendorcode/amd/agesa/f14/Proc/Recovery/Mem/NB/ON/mrnon.c index e8a28ed2e9..5c3e778248 100644 --- a/src/vendorcode/amd/agesa/f14/Proc/Recovery/Mem/NB/ON/mrnon.c +++ b/src/vendorcode/amd/agesa/f14/Proc/Recovery/Mem/NB/ON/mrnon.c @@ -9,7 +9,7 @@ * @xrefitem bom "File Content Label" "Release Content" * @e project: AGESA * @e sub-project: (Proc/Recovery/Mem) - * @e \$Revision: 38303 $ @e \$Date: 2010-09-22 00:22:47 +0800 (Wed, 22 Sep 2010) $ + * @e \$Revision: 48803 $ @e \$Date: 2011-03-10 20:18:28 -0700 (Thu, 10 Mar 2011) $ * **/ /* @@ -56,6 +56,7 @@ #include "AGESA.h" #include "amdlib.h" #include "Ids.h" +#include "OptionMemory.h" #include "mrport.h" #include "cpuFamRegisters.h" #include "cpuRegisters.h" @@ -77,12 +78,15 @@ #define MAX_DELAYS 9 /* 8 data bytes + 1 ECC byte */ #define MAX_DIMMS 4 /* 4 DIMMs per channel */ +#define PHY_DIRECT_ADDRESS_MASK 0x0D000000 + +STATIC CONST UINT8 RecInstancesPerTypeON[8] = {8, 2, 1, 0, 2, 0, 1, 1}; /*---------------------------------------------------------------------------- * TYPEDEFS AND STRUCTURES * *---------------------------------------------------------------------------- */ -CONST MEM_FREQ_CHANGE_PARAM RecFreqChangeParamON = {0x1838, NULL, 3, 10, 2}; +CONST MEM_FREQ_CHANGE_PARAM RecFreqChangeParamON = {0x1838, NULL, 3, 10, 2, 9, NULL, 1000}; /*---------------------------------------------------------------------------- * PROTOTYPES OF LOCAL FUNCTIONS @@ -105,16 +109,6 @@ MemRecNCmnGetSetFieldON ( IN UINT32 Field ); -UINT32 -STATIC -MemRecNcmnGetSetTrainDlyON ( - IN OUT MEM_NB_BLOCK *NBPtr, - IN UINT8 IsSet, - IN TRN_DLY_TYPE TrnDly, - IN DRBN DrbnVar, - IN UINT16 Field - ); - BOOLEAN STATIC MemRecNIsIdSupportedON ( @@ -127,6 +121,19 @@ MemRecNIsIdSupportedON ( * *---------------------------------------------------------------------------- */ +STATIC CONST UINT32 RecModeDefRegArrayON[] = { + BFDramBankAddrReg, 0x00000011, + BFDramTimingLoReg, 0x000A0092, + BFDramTiming0, 0x0A000101, + BFDramTiming1, 0x04100415, + BFDramTimingHiReg, 0x02D218FF, + BFDramMRSReg, 0x000400A5, + BFDramControlReg, 0x04802A03, + BFDramConfigLoReg, 0x06600000, + BFDramConfigHiReg, 0x1E000000, + BFPhyFence, 0x000056B5, + NULL +}; /* -----------------------------------------------------------------------------*/ /** * @@ -170,7 +177,7 @@ MemRecConstructNBBlockON ( // // Allocate buffer for DCT_STRUCTs and CH_DEF_STRUCTs // - AllocHeapParams.RequestedBufferSize = (sizeof (DCT_STRUCT) + sizeof (CH_DEF_STRUCT) + sizeof (MEM_PS_BLOCK)); + AllocHeapParams.RequestedBufferSize = (sizeof (DCT_STRUCT) + sizeof (CH_DEF_STRUCT) + sizeof (MEM_PS_BLOCK)) + (MAX_DIMMS * MAX_DELAYS * NUMBER_OF_DELAY_TABLES); AllocHeapParams.BufferHandle = GENERATE_MEM_HANDLE (ALLOC_DCT_STRUCT_HANDLE, NodeID, 0, 0); AllocHeapParams.Persist = HEAP_LOCAL_CACHE; if (HeapAllocateBuffer (&AllocHeapParams, &MemPtr->StdHeader) != AGESA_SUCCESS) { @@ -178,6 +185,9 @@ MemRecConstructNBBlockON ( return FALSE; } + NBPtr->SPDPtr = MemPtr->SpdDataStructure; + NBPtr->AllNodeSPDPtr = MemPtr->SpdDataStructure; + MemPtr->DieCount = 1; MCTPtr->Dct = 0; MCTPtr->DctCount = 1; @@ -187,6 +197,11 @@ MemRecConstructNBBlockON ( MCTPtr->DctData->ChData = (CH_DEF_STRUCT *) AllocHeapParams.BufferPtr; AllocHeapParams.BufferPtr += sizeof (CH_DEF_STRUCT); NBPtr->PSBlock = (MEM_PS_BLOCK *) AllocHeapParams.BufferPtr; + AllocHeapParams.BufferPtr += sizeof (MEM_PS_BLOCK); + + MCTPtr->DctData->ChData->RcvEnDlys = (UINT16 *) AllocHeapParams.BufferPtr; + AllocHeapParams.BufferPtr += (MAX_DIMMS * MAX_DELAYS) * 2; + MCTPtr->DctData->ChData->WrDqsDlys = AllocHeapParams.BufferPtr; // // Initialize NB block's variables @@ -211,6 +226,8 @@ MemRecConstructNBBlockON ( NBPtr->InitRecovery = MemRecNMemInitON; + NBPtr->RecModeDefRegArray = RecModeDefRegArrayON; + NBPtr->SwitchNodeRec = (VOID (*) (MEM_NB_BLOCK *, UINT8)) MemRecDefRet; NBPtr->SwitchDCT = (VOID (*) (MEM_NB_BLOCK *, UINT8)) MemRecDefRet; NBPtr->SwitchChannel = (VOID (*) (MEM_NB_BLOCK *, UINT8)) MemRecDefRet; @@ -226,13 +243,12 @@ MemRecConstructNBBlockON ( NBPtr->SetTrainDly = MemRecNSetTrainDlyNb; NBPtr->MemRecNCmnGetSetFieldNb = MemRecNCmnGetSetFieldON; - NBPtr->MemRecNcmnGetSetTrainDlyNb = MemRecNcmnGetSetTrainDlyON; + NBPtr->MemRecNcmnGetSetTrainDlyNb = MemRecNcmnGetSetTrainDlyClientNb; NBPtr->MemRecNSwitchDctNb = (VOID (*) (MEM_NB_BLOCK *, UINT8)) MemRecDefRet; - NBPtr->MemRecNInitializeMctNb = MemRecNInitializeMctON; - NBPtr->MemRecNFinalizeMctNb = MemRecNFinalizeMctON; - NBPtr->IsSupported[DramModeAfterDimmPres] = TRUE; NBPtr->TrainingFlow = MemNRecTrainingFlowClientNb; NBPtr->ReadPattern = MemRecNContReadPatternClientNb; + NBPtr->IsSupported[DramModeAfterDimmPres] = TRUE; + NBPtr->FamilySpecificHook[OverrideRcvEnSeed] = MemRecNOverrideRcvEnSeedON; return TRUE; } @@ -242,119 +258,6 @@ MemRecConstructNBBlockON ( * *---------------------------------------------------------------------------- */ - -/* -----------------------------------------------------------------------------*/ -/** - * - * This function gets or set DQS timing during training. - * - * @param[in,out] *NBPtr - Pointer to the MEM_NB_BLOCK - * @param[in] TrnDly - type of delay to be set - * @param[in] DrbnVar - encoding of Dimm-Rank-Byte-Nibble to be accessed - * (use either DIMM_BYTE_ACCESS(dimm,byte) or CS_NBBL_ACCESS(cs,nibble) to use this encoding - * @param[in] Field - Value to be programmed - * @param[in] IsSet - Indicates if the function will set or get - * - * @return value read, if the function is used as a "get" - */ - -UINT32 -STATIC -MemRecNcmnGetSetTrainDlyON ( - IN OUT MEM_NB_BLOCK *NBPtr, - IN UINT8 IsSet, - IN TRN_DLY_TYPE TrnDly, - IN DRBN DrbnVar, - IN UINT16 Field - ) -{ - UINT16 Index; - UINT16 Offset; - UINT32 Value; - UINT32 Address; - UINT8 Dimm; - UINT8 Byte; - - Dimm = DRBN_DIMM (DrbnVar); - Byte = DRBN_BYTE (DrbnVar); - - ASSERT (Dimm < 1); - ASSERT (Byte <= 8); - - switch (TrnDly) { - case AccessRcvEnDly: - Index = 0x10; - break; - case AccessWrDqsDly: - Index = 0x30; - break; - case AccessWrDatDly: - Index = 0x01; - break; - case AccessRdDqsDly: - Index = 0x05; - break; - case AccessPhRecDly: - Index = 0x50; - break; - default: - Index = 0; - IDS_ERROR_TRAP; - } - - switch (TrnDly) { - case AccessRcvEnDly: - case AccessWrDqsDly: - if ((Byte & 0x04) != 0) { - // if byte 4,5,6,7 - Index += 0x10; - } - if ((Byte & 0x02) != 0) { - // if byte 2,3,6,7 - Index++; - } - Offset = 16 * (Byte % 2); - break; - - case AccessRdDqsDly: - Field &= ~ 0x0001; - case AccessWrDatDly: - Index += (Dimm * 0x100); - // break is not being used here because AccessRdDqsDly and AccessWrDatDly also need - // to run AccessPhRecDly sequence. - case AccessPhRecDly: - Index += (Byte / 4); - Offset = 8 * (Byte % 4); - break; - default: - Offset = 0; - IDS_ERROR_TRAP; - } - - Address = Index; - MemRecNSetBitFieldNb (NBPtr, BFDctAddlOffsetReg, Address); - Value = MemRecNGetBitFieldNb (NBPtr, BFDctAddlDataReg); - - if (IsSet != 0) { - if (TrnDly == AccessPhRecDly) { - Value = NBPtr->DctCachePtr->PhRecReg[Index & 0x03]; - } - - Value = ((UINT32)Field << Offset) | (Value & (~((UINT32)0xFF << Offset))); - MemRecNSetBitFieldNb (NBPtr, BFDctAddlDataReg, Value); - Address |= DCT_ACCESS_WRITE; - MemRecNSetBitFieldNb (NBPtr, BFDctAddlOffsetReg, Address); - - if (TrnDly == AccessPhRecDly) { - NBPtr->DctCachePtr->PhRecReg[Index & 0x03] = Value; - } - } else { - Value = (Value >> Offset) & 0xFF; - } - - return Value; -} - /* -----------------------------------------------------------------------------*/ /** * @@ -376,51 +279,90 @@ MemRecNCmnGetSetFieldON ( IN UINT32 Field ) { - SBDFO Address; + TSEFO Address; PCI_ADDR PciAddr; UINT8 Type; + UINT8 IsLinked; UINT32 Value; UINT32 Highbit; UINT32 Lowbit; UINT32 Mask; + UINT8 IsPhyDirectAccess; + UINT8 IsWholeRegAccess; + UINT8 NumOfInstances; + UINT8 Instance; Value = 0; - if ((FieldName == BFDctAccessDone) || (FieldName == BFDctExtraAccessDone)) { - Value = 1; - } else if ((FieldName < BFEndOfList) && (FieldName >= 0)) { + if ((FieldName < BFEndOfList) && (FieldName >= 0)) { Address = NBPtr->NBRegTable[FieldName]; - if (Address != 0) { + if (Address) { Lowbit = TSEFO_END (Address); Highbit = TSEFO_START (Address); - Type = TSEFO_TYPE (Address); + Type = (UINT8) TSEFO_TYPE (Address); + IsLinked = (UINT8) TSEFO_LINKED (Address); + IsPhyDirectAccess = (UINT8) TSEFO_DIRECT_EN (Address); + IsWholeRegAccess = (UINT8) TSEFO_WHOLE_REG_ACCESS (Address); + + ASSERT ((Address & ((UINT32) 1) << 29) == 0); // Old Phy direct access method is not supported - if ((Address >> 29) == ((DCT_PHY_ACCESS << 1) | 1)) { - // Special DCT Phy access - Address &= 0x0FFFFFFF; + Address = TSEFO_OFFSET (Address); + + // By default, a bit field has only one instance + NumOfInstances = 1; + + if ((Type == DCT_PHY_ACCESS) && IsPhyDirectAccess) { + Address |= PHY_DIRECT_ADDRESS_MASK; + if (IsWholeRegAccess) { + // In the case of whole regiter access (bit 0 to 15), + // HW broadcast and nibble mask will be used. + Address |= Lowbit << 16; Lowbit = 0; - Highbit = 16; + Highbit = 15; } else { - // Normal DCT Phy access - Address = TSEFO_OFFSET (Address); + // In the case only some bits on a register is accessed, + // BIOS will do read-mod-write to all chiplets manually. + // And nibble mask will be 1111b always. + Address |= 0x000F0000; + Field >>= Lowbit; + if ((Address & 0x0F00) == 0x0F00) { + // Broadcast mode + // Find out how many instances to write to + NumOfInstances = RecInstancesPerTypeON[(Address >> 13) & 0x7]; + if (!IsSet) { + // For read, only read from instance 0 in broadcast mode + NumOfInstances = 1; + } + } + } } + ASSERT (NumOfInstances > 0); + for (Instance = 0; Instance < NumOfInstances; Instance++) { if (Type == NB_ACCESS) { Address |= (((UINT32) (24 + 0)) << 15); PciAddr.AddressValue = Address; LibAmdPciRead (AccessWidth32, PciAddr, &Value, &NBPtr->MemPtr->StdHeader); + if ((FieldName != BFDctAddlDataReg) && (FieldName != BFDctAddlOffsetReg) && + (FieldName != BFDctExtraDataReg) && (FieldName != BFDctExtraOffsetReg)) { + IDS_HDT_CONSOLE (MEM_GETREG, "~Fn%d_%03x = %x\n", (Address >> 12) & 0xF, Address & 0xFFF, Value); + } } else if (Type == DCT_PHY_ACCESS) { + if (IsPhyDirectAccess && (NumOfInstances > 1)) { + Address = (Address & 0x0FFFF0FF) | (((UINT32) Instance) << 8); + } MemRecNSetBitFieldNb (NBPtr, BFDctAddlOffsetReg, Address); - Value = MemRecNGetBitFieldNb (NBPtr, BFDctAddlDataReg); + IDS_HDT_CONSOLE (MEM_GETREG, "~Fn2_%d9C_%x = %x\n", NBPtr->Dct, Address & 0x0FFFFFFF, Value); } else if (Type == DCT_EXTRA) { MemRecNSetBitFieldNb (NBPtr, BFDctExtraOffsetReg, Address); Value = MemRecNGetBitFieldNb (NBPtr, BFDctExtraDataReg); + IDS_HDT_CONSOLE (MEM_GETREG, "~Fn2_%dF4_%x = %x\n", NBPtr->Dct, Address & 0x0FFFFFFF, Value); } else { IDS_ERROR_TRAP; } - if (IsSet != 0) { + if (IsSet) { // A 1<<32 == 1<<0 due to x86 SHL instruction, so skip if that is the case if ((Highbit - Lowbit) != 31) { Mask = (((UINT32)1 << (Highbit - Lowbit + 1)) - 1); @@ -433,24 +375,40 @@ MemRecNCmnGetSetFieldON ( if (Type == NB_ACCESS) { PciAddr.AddressValue = Address; LibAmdPciWrite (AccessWidth32, PciAddr , &Value, &NBPtr->MemPtr->StdHeader); + if ((FieldName != BFDctAddlDataReg) && (FieldName != BFDctAddlOffsetReg) && + (FieldName != BFDctExtraDataReg) && (FieldName != BFDctExtraOffsetReg)) { + IDS_HDT_CONSOLE (MEM_SETREG, "~Fn%d_%03x [%d:%d] = %x\n", (Address >> 12) & 0xF, Address & 0xFFF, Highbit, Lowbit, Field); + } } else if (Type == DCT_PHY_ACCESS) { MemRecNSetBitFieldNb (NBPtr, BFDctAddlDataReg, Value); Address |= DCT_ACCESS_WRITE; - MemRecNSetBitFieldNb (NBPtr, BFDctAddlOffsetReg, Address); + IDS_HDT_CONSOLE (MEM_SETREG, "~Fn2_%d9C_%x [%d:%d] = %x\n", NBPtr->Dct, Address & 0x0FFFFFFF, Highbit, Lowbit, Field); } else if (Type == DCT_EXTRA) { MemRecNSetBitFieldNb (NBPtr, BFDctExtraDataReg, Value); Address |= DCT_ACCESS_WRITE; MemRecNSetBitFieldNb (NBPtr, BFDctExtraOffsetReg, Address); + IDS_HDT_CONSOLE (MEM_SETREG, "~Fn2_%dF4_%x [%d:%d] = %x\n", NBPtr->Dct, Address & 0x0FFFFFFF, Highbit, Lowbit, Field); } else { IDS_ERROR_TRAP; } + if (IsLinked) { + MemRecNCmnGetSetFieldON (NBPtr, 1, FieldName + 1, Field >> (Highbit - Lowbit + 1)); + } } else { Value = Value >> Lowbit; // Shift // A 1<<32 == 1<<0 due to x86 SHL instruction, so skip if that is the case if ((Highbit - Lowbit) != 31) { Value &= (((UINT32)1 << (Highbit - Lowbit + 1)) - 1); } + if (IsLinked) { + Value |= MemRecNCmnGetSetFieldON (NBPtr, 0, FieldName + 1, 0) << (Highbit - Lowbit + 1); + } + // For direct phy access, shift the bit back for compatibility reason. + if ((Type == DCT_PHY_ACCESS) && IsPhyDirectAccess) { + Value <<= Lowbit; + } + } } } } else { @@ -476,7 +434,7 @@ MemRecNInitNBRegTableON ( ) { UINT16 i; - for (i = 0; i <= BFEndOfList; i++) { + for (i = 0; i < BFEndOfList; i++) { NBRegTable[i] = 0; } @@ -507,7 +465,11 @@ MemRecNInitNBRegTableON ( MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x98), 31, 0, BFDctAddlOffsetReg); MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x9C), 31, 0, BFDctAddlDataReg); + MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x78), 3, 0, BFRdPtrInit); + MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x78), 6, 6, BFRxPtrInitReq); MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x78), 18, 18, BFDqsRcvEnTrain); + MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x78), 17, 17, BFAddrCmdTriEn); + MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x78), 21, 21, BFDisCutThroughMode); MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x78), 31, 22, BFMaxLatency); MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x7C), 15, 0, BFMrsAddress); @@ -536,8 +498,11 @@ MemRecNInitNBRegTableON ( MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x94), 9, 9, BFLegacyBiosMode); MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x94), 11, 10, BFZqcsInterval); MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x94), 14, 14, BFDisDramInterface); + MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x94), 15, 15, BFPowerDownEn); + MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x94), 22, 22, BFBankSwizzleMode); MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0xA8), 22, 21, BFDbeGskMemClkAlignMode); + MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0xC0), 0, 0, BFTraceModeEn); MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0xF0), 31, 0, BFDctExtraOffsetReg); MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0xF4), 31, 0, BFDctExtraDataReg); MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x110), 8, 8, BFDramEnabled); @@ -579,10 +544,20 @@ MemRecNInitNBRegTableON ( MAKE_TSEFO (NBRegTable, DCT_PHY_ACCESS, 0x08, 27, 24, BFPllDiv); MAKE_TSEFO (NBRegTable, DCT_PHY_ACCESS, 0x0B, 31, 0, BFDramPhyStatusReg); - MAKE_TSEFO (NBRegTable, DCT_PHY_ACCESS, 0x0C, 20, 16, BFPhyFence); + MAKE_TSEFO (NBRegTable, DCT_PHY_ACCESS, 0x0C, 31, 16, BFPhyFence); + MAKE_TSEFO (NBRegTable, DCT_PHY_ACCESS, 0x0D, 19, 16, BFRxMaxDurDllNoLock); + MAKE_TSEFO (NBRegTable, DCT_PHY_ACCESS, 0x0D, 3, 0, BFTxMaxDurDllNoLock); + + MAKE_TSEFO (NBRegTable, DCT_PHY_DIRECT, 0x0D0F0F10, 12, 12, BFEnRxPadStandby); + MAKE_TSEFO (NBRegTable, DCT_PHY_DIRECT, 0x0D0FE003, 14, 13, BFDisablePredriverCal); MAKE_TSEFO (NBRegTable, DCT_PHY_DIRECT, 0x0D0FE006, 15, 0, BFPllLockTime); - MAKE_TSEFO (NBRegTable, DCT_PHY_DIRECT, 0x0D0FE013, 15, 0, BFPllRegWaitTime); + MAKE_TSEFO (NBRegTable, DCT_PHY_DIRECT, 0x0D0F812F, 15, 0, BFAddrCmdTri); + MAKE_TSEFO (NBRegTable, DCT_PHY_DIRECT, 0x0D0F0F0F, 14, 12, BFAlwaysEnDllClks); + + MAKE_TSEFO (NBRegTable, DCT_PHY_DIRECT, 0x0D0F1C00, 15, 0, BFPNOdtCal); + MAKE_TSEFO (NBRegTable, DCT_PHY_DIRECT, 0x0D0F1D00, 15, 0, BFPNDrvCal); + MAKE_TSEFO (NBRegTable, DCT_PHY_DIRECT, 0x0D081E00, 15, 0, BFCalVal); MAKE_TSEFO (NBRegTable, DCT_PHY_DIRECT, 0x0D0F0F1F, 4, 3, BFDataRxVioLvl); MAKE_TSEFO (NBRegTable, DCT_PHY_DIRECT, 0x0D0F2F1F, 4, 3, BFClkRxVioLvl); @@ -590,29 +565,9 @@ MemRecNInitNBRegTableON ( MAKE_TSEFO (NBRegTable, DCT_PHY_DIRECT, 0x0D0F8F1F, 4, 3, BFCmdRxVioLvl); MAKE_TSEFO (NBRegTable, DCT_PHY_DIRECT, 0x0D0FC01F, 4, 3, BFAddrRxVioLvl); - MAKE_TSEFO (NBRegTable, DCT_PHY_DIRECT, 0x0D0F0F31, 14, 0, BFDataFence2); - MAKE_TSEFO (NBRegTable, DCT_PHY_DIRECT, 0x0D0F2F31, 4, 0, BFClkFence2); - MAKE_TSEFO (NBRegTable, DCT_PHY_DIRECT, 0x0D0F8F31, 4, 0, BFCmdFence2); - MAKE_TSEFO (NBRegTable, DCT_PHY_DIRECT, 0x0D0FC031, 4, 0, BFAddrFence2); - MAKE_TSEFO (NBRegTable, DCT_PHY_DIRECT, 0x0D0F0F0F, 14, 12, BFAlwaysEnDllClks); - - MAKE_TSEFO (NBRegTable, DCT_PHY_DIRECT, 0x0D0FE003, 14, 13, BFDisablePredriverCal); - MAKE_TSEFO (NBRegTable, DCT_PHY_DIRECT, 0x0D0F0F02, 15, 0, BFDataByteTxPreDriverCal); - MAKE_TSEFO (NBRegTable, DCT_PHY_DIRECT, 0x0D0F0F06, 15, 0, BFDataByteTxPreDriverCal2Pad1); - MAKE_TSEFO (NBRegTable, DCT_PHY_DIRECT, 0x0D0F0F0A, 15, 0, BFDataByteTxPreDriverCal2Pad2); - MAKE_TSEFO (NBRegTable, DCT_PHY_DIRECT, 0x0D0F8006, 15, 0, BFCmdAddr0TxPreDriverCal2Pad1); - MAKE_TSEFO (NBRegTable, DCT_PHY_DIRECT, 0x0D0F800A, 15, 0, BFCmdAddr0TxPreDriverCal2Pad2); - MAKE_TSEFO (NBRegTable, DCT_PHY_DIRECT, 0x0D0F8106, 15, 0, BFCmdAddr1TxPreDriverCal2Pad1); - MAKE_TSEFO (NBRegTable, DCT_PHY_DIRECT, 0x0D0F810A, 15, 0, BFCmdAddr1TxPreDriverCal2Pad2); - MAKE_TSEFO (NBRegTable, DCT_PHY_DIRECT, 0x0D0FC006, 15, 0, BFAddrTxPreDriverCal2Pad1); - MAKE_TSEFO (NBRegTable, DCT_PHY_DIRECT, 0x0D0FC00A, 15, 0, BFAddrTxPreDriverCal2Pad2); - MAKE_TSEFO (NBRegTable, DCT_PHY_DIRECT, 0x0D0FC00E, 15, 0, BFAddrTxPreDriverCal2Pad3); - MAKE_TSEFO (NBRegTable, DCT_PHY_DIRECT, 0x0D0FC012, 15, 0, BFAddrTxPreDriverCal2Pad4); - MAKE_TSEFO (NBRegTable, DCT_PHY_DIRECT, 0x0D0F8002, 15, 0, BFCmdAddr0TxPreDriverCalPad0); - MAKE_TSEFO (NBRegTable, DCT_PHY_DIRECT, 0x0D0F8102, 15, 0, BFCmdAddr1TxPreDriverCalPad0); - MAKE_TSEFO (NBRegTable, DCT_PHY_DIRECT, 0x0D0FC002, 15, 0, BFAddrTxPreDriverCalPad0); - MAKE_TSEFO (NBRegTable, DCT_PHY_DIRECT, 0x0D0F2002, 15, 0, BFClock0TxPreDriverCalPad0); - MAKE_TSEFO (NBRegTable, DCT_PHY_DIRECT, 0x0D0F2102, 15, 0, BFClock1TxPreDriverCalPad0); + MAKE_TSEFO (NBRegTable, DCT_EXTRA, 0x06, 11, 8, BFTwrrdSD); + MAKE_TSEFO (NBRegTable, DCT_EXTRA, 0x06, 3, 0, BFTrdrdSD); + MAKE_TSEFO (NBRegTable, DCT_EXTRA, 0x16, 3, 0, BFTwrwrSD); MAKE_TSEFO (NBRegTable, DCT_EXTRA, 0x30, 12, 0, BFDbeGskFifoNumerator); MAKE_TSEFO (NBRegTable, DCT_EXTRA, 0x31, 12, 0, BFDbeGskFifoDenominator); @@ -623,7 +578,14 @@ MemRecNInitNBRegTableON ( MAKE_TSEFO (NBRegTable, DCT_EXTRA, 0x32, 15, 15, BFDataTxFifoSchedDlyNegSlot1); MAKE_TSEFO (NBRegTable, DCT_EXTRA, 0x40, 31, 0, BFDramTiming0); - MAKE_TSEFO (NBRegTable, DCT_EXTRA, 0x41, 31, 0, BFDramTiming1); + + MAKE_TSEFO (NBRegTable, DCT_EXTRA, 0x83, 2, 0, BFRdOdtTrnOnDly); + MAKE_TSEFO (NBRegTable, DCT_EXTRA, 0x83, 6, 4, BFRdOdtOnDuration); + MAKE_TSEFO (NBRegTable, DCT_EXTRA, 0x83, 8, 8, BFWrOdtTrnOnDly); + MAKE_TSEFO (NBRegTable, DCT_EXTRA, 0x83, 14, 12, BFWrOdtOnDuration); + + MAKE_TSEFO (NBRegTable, DCT_EXTRA, 0x180, 31, 0, BFPhyRODTCSLow); + MAKE_TSEFO (NBRegTable, DCT_EXTRA, 0x182, 31, 0, BFPhyWODTCSLow); } /*-----------------------------------------------------------------------------*/ diff --git a/src/vendorcode/amd/agesa/f14/Proc/Recovery/Mem/NB/ON/mrnon.h b/src/vendorcode/amd/agesa/f14/Proc/Recovery/Mem/NB/ON/mrnon.h index aa5614813c..74591337e9 100644 --- a/src/vendorcode/amd/agesa/f14/Proc/Recovery/Mem/NB/ON/mrnon.h +++ b/src/vendorcode/amd/agesa/f14/Proc/Recovery/Mem/NB/ON/mrnon.h @@ -9,7 +9,7 @@ * @xrefitem bom "File Content Label" "Release Content" * @e project: AGESA * @e sub-project: (Proc/Recovery/Mem) - * @e \$Revision: 34897 $ @e \$Date: 2010-07-14 10:07:10 +0800 (Wed, 14 Jul 2010) $ + * @e \$Revision: 48803 $ @e \$Date: 2011-03-10 20:18:28 -0700 (Thu, 10 Mar 2011) $ * **/ /* @@ -87,16 +87,6 @@ MemRecNMemInitON ( ); VOID -MemRecNFinalizeMctON ( - IN OUT MEM_NB_BLOCK *NBPtr - ); - -VOID -MemRecNInitializeMctON ( - IN OUT MEM_NB_BLOCK *NBPtr - ); - -VOID MemRecNSetMaxLatencyON ( IN OUT MEM_NB_BLOCK *NBPtr, IN UINT16 MaxRcvEnDly @@ -120,6 +110,11 @@ MemRecNAutoConfigON ( IN OUT MEM_NB_BLOCK *NBPtr ); +BOOLEAN +MemRecNOverrideRcvEnSeedON ( + IN OUT MEM_NB_BLOCK *NBPtr, + IN OUT VOID *SeedPtr + ); #endif /* _MRNON_H_ */ diff --git a/src/vendorcode/amd/agesa/f14/Proc/Recovery/Mem/NB/mrndct.c b/src/vendorcode/amd/agesa/f14/Proc/Recovery/Mem/NB/mrndct.c index 15ccaf3e8a..2769e1cc01 100644 --- a/src/vendorcode/amd/agesa/f14/Proc/Recovery/Mem/NB/mrndct.c +++ b/src/vendorcode/amd/agesa/f14/Proc/Recovery/Mem/NB/mrndct.c @@ -9,7 +9,7 @@ * @xrefitem bom "File Content Label" "Release Content" * @e project: AGESA * @e sub-project: (Proc/Recovery/Mem/NB) - * @e \$Revision: 38303 $ @e \$Date: 2010-09-22 00:22:47 +0800 (Wed, 22 Sep 2010) $ + * @e \$Revision: 48803 $ @e \$Date: 2011-03-10 20:18:28 -0700 (Thu, 10 Mar 2011) $ * **/ /* @@ -126,12 +126,6 @@ MemRecNTrainPhyFenceNb ( IN OUT MEM_NB_BLOCK *NBPtr ); -VOID -STATIC -MemRecNInitPhyCompClientNb ( - IN OUT MEM_NB_BLOCK *NBPtr - ); - /*---------------------------------------------------------------------------- * EXPORTED FUNCTIONS * @@ -338,6 +332,8 @@ MemRecNStartupDCTClientNb ( IN OUT MEM_NB_BLOCK *NBPtr ) { + IDS_HDT_CONSOLE (MEM_STATUS, "\tDct %d\n", NBPtr->Dct); + // Program D18F2x[1,0]9C_x0000_000B = 80000000h. #109999. MemRecNSetBitFieldNb (NBPtr, BFDramPhyStatusReg, 0x80000000); @@ -354,18 +350,15 @@ MemRecNStartupDCTClientNb ( MemRecNSetBitFieldNb (NBPtr, BFMemClkFreqVal, 1); MemRecNSetBitFieldNb (NBPtr, BFPllLockTime, 0x000F); + IDS_HDT_CONSOLE (MEM_FLOW, "\tMemClkAlign=0\n"); + IDS_HDT_CONSOLE (MEM_FLOW, "\tEnDramInit = 1 for DCT%d\n", NBPtr->Dct); MemRecNSetBitFieldNb (NBPtr, BFDbeGskMemClkAlignMode, 0); MemRecNSetBitFieldNb (NBPtr, BFEnDramInit, 1); - // Phy fence programming - MemRecNPhyFenceTrainingNb (NBPtr); - - // Phy Compensation Initialization - MemRecNInitPhyCompClientNb (NBPtr); - // Run DramInit sequence AGESA_TESTPOINT (TpProcMemDramInit, &(NBPtr->MemPtr->StdHeader)); NBPtr->TechPtr->DramInit (NBPtr->TechPtr); + IDS_HDT_CONSOLE (MEM_FLOW, "\nMemClkFreq: %d MHz\n", DDR800_FREQUENCY); } /* -----------------------------------------------------------------------------*/ @@ -640,15 +633,6 @@ MemRecNTotalSyncComponentsClientNb ( AGESA_TESTPOINT (TpProcMemRcvrCalcLatency , &(NBPtr->MemPtr->StdHeader)); - // Before calculating MaxRdLatecny, program a number of registers. - MemRecNSetBitFieldNb (NBPtr, BFDisDllShutdownSR, 1); - MemRecNSetBitFieldNb (NBPtr, BFEnterSelfRef, 1); - while (MemRecNGetBitFieldNb (NBPtr, BFEnterSelfRef) != 0) {} - MemRecNSetBitFieldNb (NBPtr, BFDbeGskMemClkAlignMode, 2); - MemRecNSetBitFieldNb (NBPtr, BFExitSelfRef, 1); - while (MemRecNGetBitFieldNb (NBPtr, BFExitSelfRef) != 0) {} - MemRecNSetBitFieldNb (NBPtr, BFDisDllShutdownSR, 0); - // P = P + ((16 + RdPtrInitMin - D18F2x[1,0]78[RdPtrInit]) MOD 16) where RdPtrInitMin = RdPtrInit P = 0; @@ -862,8 +846,6 @@ MemRecNTrainPhyFenceNb ( } /* -----------------------------------------------------------------------------*/ -CONST UINT16 RecPllDivTab[10] = {1, 2, 4, 8, 16, 128, 256, 1, 3, 6}; - /** * * This function calculates and programs NB P-state dependent registers @@ -883,23 +865,38 @@ MemRecNProgNbPstateDependentRegClientNb ( UINT16 MemClkDid; UINT8 PllMult; UINT8 NclkDiv; + UINT8 RdPtrInit; UINT32 NclkPeriod; UINT32 MemClkPeriod; INT32 PartialSum2x; INT32 PartialSumSlotI2x; + INT32 RdPtrInitRmdr2x; NclkFid = (UINT8) (MemRecNGetBitFieldNb (NBPtr, BFMainPllOpFreqId) + 0x10); - MemClkDid = RecPllDivTab[MemRecNGetBitFieldNb (NBPtr, BFPllDiv)]; - PllMult = (UINT8) MemRecNGetBitFieldNb (NBPtr, BFPllMult); + MemClkDid = 2; //BKDG recommended value for DDR800 + PllMult = 16; //BKDG recommended value for DDR800 NclkDiv = (UINT8) MemRecNGetBitFieldNb (NBPtr, BFNbPs0NclkDiv); NclkPeriod = (2500 * NclkDiv) / NclkFid; MemClkPeriod = 1000000 / DDR800_FREQUENCY; + NBPtr->NBClkFreq = ((UINT32) NclkFid * 400) / NclkDiv; + + IDS_HDT_CONSOLE (MEM_FLOW, "\n\tNB P%d Freq: %dMHz\n", 0, NBPtr->NBClkFreq); + IDS_HDT_CONSOLE (MEM_FLOW, "\tMemClk Freq: %dMHz\n", DDR800_FREQUENCY); + + // D18F2x[1,0]78[RdPtrInit] = IF (D18F2x[1,0]94[MemClkFreq] >= 667 MHz) THEN 7 ELSE 8 ENDIF (Llano) + // THEN 2 ELSE 3 ENDIF (Ontario) + RdPtrInit = NBPtr->FreqChangeParam->RdPtrInitLower667; + MemRecNSetBitFieldNb (NBPtr, BFRdPtrInit, RdPtrInit); + IDS_HDT_CONSOLE (MEM_FLOW, "\t\tRdPtr: %d\n", RdPtrInit); // Program D18F2x[1,0]F4_x30[DbeGskFifoNumerator] and D18F2x[1,0]F4_x31[DbeGskFifoDenominator]. MemRecNSetBitFieldNb (NBPtr, BFDbeGskFifoNumerator, NclkFid * MemClkDid * 16); MemRecNSetBitFieldNb (NBPtr, BFDbeGskFifoDenominator, PllMult * NclkDiv); + IDS_HDT_CONSOLE (MEM_FLOW, "\t\tDbeGskFifoNumerator: %d\n", NclkFid * MemClkDid * 16); + IDS_HDT_CONSOLE (MEM_FLOW, "\t\tDbeGskFifoDenominator: %d\n", PllMult * NclkDiv); + // Program D18F2x[1,0]F4_x32[DataTxFifoSchedDlyNegSlot1, DataTxFifoSchedDlySlot1, // DataTxFifoSchedDlyNegSlot0, DataTxFifoSchedDlySlot0]. // PartialSum = ((7 * NclkPeriod) + (1.5 * MemClkPeriod) + 520ps)*MemClkFrequency - tCWL - @@ -909,6 +906,9 @@ MemRecNProgNbPstateDependentRegClientNb ( PartialSum2x = NBPtr->FreqChangeParam->NclkPeriodMul2x * NclkPeriod; PartialSum2x += NBPtr->FreqChangeParam->MemClkPeriodMul2x * MemClkPeriod; PartialSum2x += 520 * 2; + RdPtrInitRmdr2x = ((NBPtr->FreqChangeParam->SyncTimeMul4x * MemClkPeriod) / 2) - 2 * (NBPtr->FreqChangeParam->TDataPropLower800 + 520); + RdPtrInitRmdr2x %= MemClkPeriod; + PartialSum2x -= RdPtrInitRmdr2x; PartialSum2x = (PartialSum2x + MemClkPeriod - 1) / MemClkPeriod; // round-up here PartialSum2x -= 2 * 5; //Tcwl + 5 if ((MemRecNGetBitFieldNb (NBPtr, BFAddrTmgControl) & 0x0202020) == 0) { @@ -916,8 +916,6 @@ MemRecNProgNbPstateDependentRegClientNb ( } else { PartialSum2x -= 2; } - // ((16 + RdPtrInitMin - D18F2x78[RdPtrInit]) MOD 16)/2 where RdPtrInitMin = RdPtrInit - PartialSum2x -= 0; PartialSum2x -= 2; // If PartialSumSlotN is positive: @@ -928,14 +926,18 @@ MemRecNProgNbPstateDependentRegClientNb ( // DataTxFifoSchedDlyNegSlotN=1. for (i = 0; i < 2; i++) { PartialSumSlotI2x = PartialSum2x; + if (i == 0) { PartialSumSlotI2x += 2; + } if (PartialSumSlotI2x > 0) { MemRecNSetBitFieldNb (NBPtr, BFDataTxFifoSchedDlyNegSlot0 + i, 0); MemRecNSetBitFieldNb (NBPtr, BFDataTxFifoSchedDlySlot0 + i, (PartialSumSlotI2x + 1) / 2); + IDS_HDT_CONSOLE (MEM_FLOW, "\t\tDataTxFifoSchedDlySlot%d: %d\n", i, (PartialSumSlotI2x + 1) / 2); } else { MemRecNSetBitFieldNb (NBPtr, BFDataTxFifoSchedDlyNegSlot0 + i, 1); PartialSumSlotI2x = ((-PartialSumSlotI2x) * MemClkPeriod) / (2 * NclkPeriod); MemRecNSetBitFieldNb (NBPtr, BFDataTxFifoSchedDlySlot0 + i, PartialSumSlotI2x); + IDS_HDT_CONSOLE (MEM_FLOW, "\t\tDataTxFifoSchedDlySlot%d: -%d\n", i, PartialSumSlotI2x); } } // Program ProcOdtAdv @@ -1416,87 +1418,111 @@ MemRecNGetPsRankType ( return DIMMRankType; } -/* -----------------------------------------------------------------------------*/ -/** - * - * - * This function initializes the DDR phy compensation logic - * - * @param[in,out] *NBPtr - Pointer to the MEM_NB_BLOCK - * - */ - -VOID -STATIC -MemRecNInitPhyCompClientNb ( - IN OUT MEM_NB_BLOCK *NBPtr +UINT32 +MemRecNcmnGetSetTrainDlyClientNb ( + IN OUT MEM_NB_BLOCK *NBPtr, + IN UINT8 IsSet, + IN TRN_DLY_TYPE TrnDly, + IN DRBN DrbnVar, + IN UINT16 Field ) { - // Slew rate table array [x] - // array[0]: slew rate for VDDIO 1.5V - // array[1]: slew rate for VDDIO 1.35V - CONST STATIC UINT16 RecTxPrePNDataDqs[2][4] = { - //{TxPreP, TxPreN}[VDDIO][Drive Strength] - {0x924, 0x924, 0x924, 0x924}, - {0xFF6, 0xB6D, 0xB6D, 0x924} - }; + UINT16 Index; + UINT16 Offset; + UINT32 Value; + UINT32 Address; + UINT8 Dimm; + UINT8 Byte; - CONST STATIC UINT16 RecTxPrePNCmdAddr[2][4] = { - //{TxPreP, TxPreN}[VDDIO][Drive Strength] - {0x492, 0x492, 0x492, 0x492}, - {0x492, 0x492, 0x492, 0x492} - }; - CONST STATIC UINT16 RecTxPrePNClock[2][4] = { - //{TxPreP, TxPreN}[VDDIO][Drive Strength] - {0x924, 0x924, 0x924, 0x924}, - {0xDAD, 0xDAD, 0x924, 0x924} - }; + Dimm = DRBN_DIMM (DrbnVar); + Byte = DRBN_BYTE (DrbnVar); - // - // Tables to describe the relationship between drive strength bit fields, PreDriver Calibration bit fields and also - // the extra value that needs to be written to specific PreDriver bit fields - // - CONST REC_PHY_COMP_INIT_CLIENTNB RecPhyCompInitBitField[] = { - // 3. Program TxPreP/TxPreN for Data and DQS according toTable 14 if VDDIO is 1.5V or Table 15 if 1.35V. - // A. Program D18F2x[1,0]9C_x0D0F_0[F,7:0]0[A,6]={0000b, TxPreP, TxPreN}. - // B. Program D18F2x[1,0]9C_x0D0F_0[F,7:0]02={1000b, TxPreP, TxPreN}. - {BFDqsDrvStren, BFDataByteTxPreDriverCal2Pad1, BFDataByteTxPreDriverCal2Pad1, 0, RecTxPrePNDataDqs}, - {BFDataDrvStren, BFDataByteTxPreDriverCal2Pad2, BFDataByteTxPreDriverCal2Pad2, 0, RecTxPrePNDataDqs}, - {BFDataDrvStren, BFDataByteTxPreDriverCal, BFDataByteTxPreDriverCal, 8, RecTxPrePNDataDqs}, - // 4. Program TxPreP/TxPreN for Cmd/Addr according toTable 16 if VDDIO is 1.5V or Table 17 if 1.35V. - // A. Program D18F2x[1,0]9C_x0D0F_[C,8][1:0][12,0E,0A,06]={0000b, TxPreP, TxPreN}. - // B. Program D18F2x[1,0]9C_x0D0F_[C,8][1:0]02={1000b, TxPreP, TxPreN}. - {BFCsOdtDrvStren, BFCmdAddr0TxPreDriverCal2Pad1, BFCmdAddr0TxPreDriverCal2Pad2, 0, RecTxPrePNCmdAddr}, - {BFAddrCmdDrvStren, BFCmdAddr1TxPreDriverCal2Pad1, BFAddrTxPreDriverCal2Pad4, 0, RecTxPrePNCmdAddr}, - {BFCsOdtDrvStren, BFCmdAddr0TxPreDriverCalPad0, BFCmdAddr0TxPreDriverCalPad0, 8, RecTxPrePNCmdAddr}, - {BFCkeDrvStren, BFAddrTxPreDriverCalPad0, BFAddrTxPreDriverCalPad0, 8, RecTxPrePNCmdAddr}, - {BFAddrCmdDrvStren, BFCmdAddr1TxPreDriverCalPad0, BFCmdAddr1TxPreDriverCalPad0, 8, RecTxPrePNCmdAddr}, - // 5. Program TxPreP/TxPreN for Clock according toTable 18 if VDDIO is 1.5V or Table 19 if 1.35V. - // A. Program D18F2x[1,0]9C_x0D0F_2[1:0]02={1000b, TxPreP, TxPreN}. - {BFClkDrvStren, BFClock0TxPreDriverCalPad0, BFClock1TxPreDriverCalPad0, 8, RecTxPrePNClock} - }; + ASSERT (Dimm < 2); + ASSERT (Byte <= ECC_DLY); - BIT_FIELD_NAME CurrentBitField; - CONST UINT16 *TxPrePNArray; - UINT8 Voltage; - UINT8 CurDct; - UINT8 i; - UINT8 j; + if ((Byte > 7)) { + // LN and ON do not support ECC delay, so: + if (IsSet) { + // On write, ignore + return 0; + } else { + // On read, redirect to byte 0 to correct fence averaging + Byte = 0; + } + } + + switch (TrnDly) { + case AccessRcvEnDly: + Index = 0x10; + break; + case AccessWrDqsDly: + Index = 0x30; + break; + case AccessWrDatDly: + Index = 0x01; + break; + case AccessRdDqsDly: + Index = 0x05; + break; + case AccessPhRecDly: + Index = 0x50; + break; + default: + Index = 0; + IDS_ERROR_TRAP; + } + + switch (TrnDly) { + case AccessRcvEnDly: + case AccessWrDqsDly: + Index += (Dimm * 3); + if (Byte & 0x04) { + // if byte 4,5,6,7 + Index += 0x10; + } + if (Byte & 0x02) { + // if byte 2,3,6,7 + Index++; + } + Offset = 16 * (Byte % 2); + break; + + case AccessRdDqsDly: + case AccessWrDatDly: + Index += (Dimm * 0x100); + // break is not being used here because AccessRdDqsDly and AccessWrDatDly also need + // to run AccessPhRecDly sequence. + case AccessPhRecDly: + Index += (Byte / 4); + Offset = 8 * (Byte % 4); + break; + default: + Offset = 0; + IDS_ERROR_TRAP; + } - CurDct = NBPtr->Dct; - NBPtr->SwitchDCT (NBPtr, 0); - // 1. Program D18F2x[1,0]9C_x0D0F_E003[DisAutoComp, DisalbePredriverCal]={1b, 1b} - MemRecNSetBitFieldNb (NBPtr, BFDisablePredriverCal, 0x6000); + Address = Index; + MemRecNSetBitFieldNb (NBPtr, BFDctAddlOffsetReg, Address); + Value = MemRecNGetBitFieldNb (NBPtr, BFDctAddlDataReg); - NBPtr->SwitchDCT (NBPtr, CurDct); + if (IsSet) { + if (TrnDly == AccessPhRecDly) { + Value = NBPtr->DctCachePtr->PhRecReg[Index & 0x03]; + } - Voltage = (UINT8) NBPtr->RefPtr->DDR3Voltage; + Value = ((UINT32)Field << Offset) | (Value & (~((UINT32) ((TrnDly == AccessRcvEnDly) ? 0x1FF : 0xFF) << Offset))); + MemRecNSetBitFieldNb (NBPtr, BFDctAddlDataReg, Value); + Address |= DCT_ACCESS_WRITE; + MemRecNSetBitFieldNb (NBPtr, BFDctAddlOffsetReg, Address); - for (j = 0; j < GET_SIZE_OF (RecPhyCompInitBitField); j ++) { - i = (UINT8) MemRecNGetBitFieldNb (NBPtr, RecPhyCompInitBitField[j].IndexBitField); - TxPrePNArray = RecPhyCompInitBitField[j].TxPrePN[Voltage]; - for (CurrentBitField = RecPhyCompInitBitField[j].StartTargetBitField; CurrentBitField <= RecPhyCompInitBitField[j].EndTargetBitField; CurrentBitField ++) { - MemRecNSetBitFieldNb (NBPtr, CurrentBitField, ((RecPhyCompInitBitField[j].ExtraValue << 12) | TxPrePNArray[i])); + if (TrnDly == AccessPhRecDly) { + NBPtr->DctCachePtr->PhRecReg[Index & 0x03] = Value; } + // Gross WrDatDly and WrDqsDly cannot be larger than 4 + ASSERT (((TrnDly == AccessWrDatDly) || (TrnDly == AccessWrDqsDly)) ? (NBPtr->IsSupported[WLNegativeDelay] || (Field < 0xA0)) : TRUE); + } else { + Value = (Value >> Offset) & (UINT32) ((TrnDly == AccessRcvEnDly) ? 0x1FF : 0xFF); } + + return Value; } diff --git a/src/vendorcode/amd/agesa/f14/Proc/Recovery/Mem/NB/mrnmct.c b/src/vendorcode/amd/agesa/f14/Proc/Recovery/Mem/NB/mrnmct.c index 75156e7c0b..88029b6d0a 100644 --- a/src/vendorcode/amd/agesa/f14/Proc/Recovery/Mem/NB/mrnmct.c +++ b/src/vendorcode/amd/agesa/f14/Proc/Recovery/Mem/NB/mrnmct.c @@ -258,8 +258,8 @@ MemRecGetVarMtrrHiMsk ( CPU_SPECIFIC_SERVICES *FamilySpecificServices; CACHE_INFO *CacheInfoPtr; - GetCpuServicesFromLogicalId (LogicalIdPtr, &FamilySpecificServices, StdHeader); - FamilySpecificServices->GetCacheInfo (FamilySpecificServices, &CacheInfoPtr, &TempNotCare, StdHeader); + GetCpuServicesFromLogicalId (LogicalIdPtr, (const CPU_SPECIFIC_SERVICES **)&FamilySpecificServices, StdHeader); + FamilySpecificServices->GetCacheInfo (FamilySpecificServices, (const VOID **)&CacheInfoPtr, &TempNotCare, StdHeader); return (UINT32) (CacheInfoPtr->VariableMtrrMask >> 32); } diff --git a/src/vendorcode/amd/agesa/f14/Proc/Recovery/Mem/NB/mrntrain3.c b/src/vendorcode/amd/agesa/f14/Proc/Recovery/Mem/NB/mrntrain3.c index 7a35921643..393cb7cabf 100644 --- a/src/vendorcode/amd/agesa/f14/Proc/Recovery/Mem/NB/mrntrain3.c +++ b/src/vendorcode/amd/agesa/f14/Proc/Recovery/Mem/NB/mrntrain3.c @@ -9,7 +9,7 @@ * @xrefitem bom "File Content Label" "Release Content" * @e project: AGESA * @e sub-project: (Mem/NB) - * @e \$Revision: 34897 $ @e \$Date: 2010-07-14 10:07:10 +0800 (Wed, 14 Jul 2010) $ + * @e \$Revision: 48803 $ @e \$Date: 2011-03-10 20:18:28 -0700 (Thu, 10 Mar 2011) $ * **/ /* @@ -115,12 +115,24 @@ MemNRecTrainingFlowClientNb ( IN OUT MEM_NB_BLOCK *NBPtr ) { + IDS_HDT_CONSOLE (MEM_STATUS, "\nStart serial training\n"); + IDS_HDT_CONSOLE (MEM_STATUS, "Node %d\n", NBPtr->MCTPtr->DieId); MemRecTTrainDQSWriteHw3 (NBPtr->TechPtr); MemRecTTrainRcvrEnHw (NBPtr->TechPtr); // Clear DisableCal and set DisablePredriverCal NBPtr->FamilySpecificHook[ReEnablePhyComp] (NBPtr, NBPtr); + NBPtr->SetBitField (NBPtr, BFRxPtrInitReq, 1); + while (NBPtr->GetBitField (NBPtr, BFRxPtrInitReq) != 0) {} + NBPtr->SetBitField (NBPtr, BFDisDllShutdownSR, 1); + NBPtr->SetBitField (NBPtr, BFEnterSelfRef, 1); + while (NBPtr->GetBitField (NBPtr, BFEnterSelfRef) != 0) {} + IDS_HDT_CONSOLE (MEM_FLOW, "\tMemClkAlign = 2\n"); + NBPtr->SetBitField (NBPtr, BFDbeGskMemClkAlignMode, 2); + NBPtr->SetBitField (NBPtr, BFExitSelfRef, 1); + while (NBPtr->GetBitField (NBPtr, BFExitSelfRef) != 0) {} + NBPtr->SetBitField (NBPtr, BFDisDllShutdownSR, 0); MemRecTTrainDQSPosSw (NBPtr->TechPtr); } diff --git a/src/vendorcode/amd/agesa/f14/Proc/Recovery/Mem/Tech/DDR3/mrtsdi3.c b/src/vendorcode/amd/agesa/f14/Proc/Recovery/Mem/Tech/DDR3/mrtsdi3.c index 92a035fec7..9ced115b3c 100644 --- a/src/vendorcode/amd/agesa/f14/Proc/Recovery/Mem/Tech/DDR3/mrtsdi3.c +++ b/src/vendorcode/amd/agesa/f14/Proc/Recovery/Mem/Tech/DDR3/mrtsdi3.c @@ -9,7 +9,7 @@ * @xrefitem bom "File Content Label" "Release Content" * @e project: AGESA * @e sub-project: (Proc/Recovery/Mem) - * @e \$Revision: 35136 $ @e \$Date: 2010-07-16 11:29:48 +0800 (Fri, 16 Jul 2010) $ + * @e \$Revision: 48803 $ @e \$Date: 2011-03-10 20:18:28 -0700 (Thu, 10 Mar 2011) $ * **/ /* @@ -56,6 +56,7 @@ #include "AGESA.h" #include "OptionMemory.h" +#include "Ids.h" #include "mm.h" #include "mn.h" #include "mru.h" @@ -114,6 +115,8 @@ MemRecTDramInitSw3 ( NBPtr = TechPtr->NBPtr; MemPtr = NBPtr->MemPtr; + IDS_HDT_CONSOLE (MEM_STATUS, "\nStart Dram Init\n"); + IDS_HDT_CONSOLE (MEM_FLOW, "\tEnDramInit = 1 for DCT%d\n", NBPtr->Dct); // 3.Program F2x[1,0]7C[EnDramInit]=1 NBPtr->SetBitField (NBPtr, BFEnDramInit, 1); @@ -177,7 +180,7 @@ MemRecTDramInitSw3 ( // 18.Program F2x[1,0]7C[EnDramInit]=0 NBPtr->SetBitField (NBPtr, BFEnDramInit, 0); - + IDS_HDT_CONSOLE (MEM_FLOW, "End Dram Init\n\n"); } /* -----------------------------------------------------------------------------*/ diff --git a/src/vendorcode/amd/agesa/f14/Proc/Recovery/Mem/Tech/DDR3/mrttwl3.c b/src/vendorcode/amd/agesa/f14/Proc/Recovery/Mem/Tech/DDR3/mrttwl3.c index 068c926ff3..5e1ad007dd 100644 --- a/src/vendorcode/amd/agesa/f14/Proc/Recovery/Mem/Tech/DDR3/mrttwl3.c +++ b/src/vendorcode/amd/agesa/f14/Proc/Recovery/Mem/Tech/DDR3/mrttwl3.c @@ -9,7 +9,7 @@ * @xrefitem bom "File Content Label" "Release Content" * @e project: AGESA * @e sub-project: (Proc/Recovery/Mem) - * @e \$Revision: 35136 $ @e \$Date: 2010-07-16 11:29:48 +0800 (Fri, 16 Jul 2010) $ + * @e \$Revision: 48803 $ @e \$Date: 2011-03-10 20:18:28 -0700 (Thu, 10 Mar 2011) $ * **/ /* @@ -129,6 +129,7 @@ MemRecTTrainDQSWriteHw3 ( NBPtr = TechPtr->NBPtr; + IDS_HDT_CONSOLE (MEM_STATUS, "\nStart write leveling\n"); // Disable auto refresh by configuring F2x[1, 0]8C[DisAutoRefresh] = 1. NBPtr->SetBitField (NBPtr, BFDisAutoRefresh, 1); // Disable ZQ calibration short command by configuring F2x[1, 0]94[ZqcsInterval] = 00b. @@ -136,6 +137,7 @@ MemRecTTrainDQSWriteHw3 ( // 1. Specify the target Dimm that is to be trained by programming // F2x[1, 0]9C_x08[TrDimmSel]. + IDS_HDT_CONSOLE (MEM_STATUS, "\t\tCS %d\n", NBPtr->DimmToBeUsed << 1); NBPtr->SetBitField (NBPtr, BFTrDimmSel, NBPtr->DimmToBeUsed); // 2. Prepare the DIMMs for write levelization using DDR3-defined @@ -167,6 +169,7 @@ MemRecTTrainDQSWriteHw3 ( // 14.Program F2x[1, 0]94[ZqcsInterval] to the proper interval for the current memory configuration. NBPtr->SetBitField (NBPtr, BFZqcsInterval, 2); + IDS_HDT_CONSOLE (MEM_FLOW, "End write leveling\n\n"); } /*---------------------------------------------------------------------------- @@ -266,6 +269,8 @@ MemRecTProcConfig3 ( // Wait 10 MEMCLKs to allow for ODT signal settling. MemRecUWait10ns (3, NBPtr->MemPtr); + IDS_HDT_CONSOLE (MEM_FLOW, "\n\t\t\t Byte: 00 01 02 03 04 05 06 07 ECC\n"); + IDS_HDT_CONSOLE (MEM_FLOW, "\t\t\tSeeds: "); // Program an initialization Value to registers F2x[1, 0]9C_x[51:50] and F2x[1, 0]9C_x52 to set // the gross and fine delay for all the byte lane fields. If the target frequency is different than 400MHz, // BIOS must execute two training passes for each Dimm. For pass 1 at a 400MHz MEMCLK frequency, @@ -284,17 +289,21 @@ MemRecTProcConfig3 ( // Get platform override seed Seed = (UINT8 *) MemRecFindPSOverrideEntry (NBPtr->RefPtr->PlatformMemoryConfiguration, PSO_WL_SEED, NBPtr->MCTPtr->SocketId, ChannelPtr->ChannelID); + IDS_HDT_CONSOLE (MEM_FLOW, "Seeds: "); for (ByteLane = 0; ByteLane < 8; ByteLane++) { // This includes ECC as byte 8 CurrentSeed = ((Seed != NULL) ? Seed[ByteLane] : DefaultSeed); NBPtr->SetTrainDly (NBPtr, AccessPhRecDly, DIMM_BYTE_ACCESS (Dimm, ByteLane), CurrentSeed); ChannelPtr->WrDqsDlys[Dimm * MAX_BYTELANES + ByteLane] = CurrentSeed; + IDS_HDT_CONSOLE (MEM_FLOW, "%02x ", CurrentSeed); } + IDS_HDT_CONSOLE (MEM_FLOW, "\n"); // Program F2x[1, 0]9C_x08[WrtLvTrMode]=0 for phy assisted training. // Program F2x[1, 0]9C_x08[TrNibbleSel]=0 + IDS_HDT_CONSOLE (MEM_FLOW, "\n"); } /* -----------------------------------------------------------------------------*/ @@ -321,6 +330,7 @@ MemRecTBeginWLTrain3 ( NBPtr = TechPtr->NBPtr; Dimm = NBPtr->DimmToBeUsed; + IDS_HDT_CONSOLE (MEM_FLOW, "\t\t\tWrtLvTrEn = 1\n"); // Program F2x[1, 0]9C_x08[WrtLlTrEn]=1. NBPtr->SetBitField (NBPtr, BFWrtLvTrEn, 1); @@ -332,10 +342,12 @@ MemRecTBeginWLTrain3 ( // Read from registers F2x[1, 0]9C_x[51:50] and F2x[1, 0]9C_x52 to get the gross and fine Delay settings // for the target Dimm and save these values. + IDS_HDT_CONSOLE (MEM_FLOW, " PRE WrDqs\n"); for (ByteLane = 0; ByteLane < 8; ByteLane++) { // This includes ECC as byte 8 Seed = NBPtr->ChannelPtr->WrDqsDlys[(Dimm * MAX_BYTELANES) + ByteLane]; Delay = (UINT8)NBPtr->GetTrainDly (NBPtr, AccessPhRecDly, DIMM_BYTE_ACCESS (Dimm, ByteLane)); + IDS_HDT_CONSOLE (MEM_FLOW, " %02x ", Delay); if (((Seed >> 5) == 0) && ((Delay >> 5) == 3)) { // If seed has gross delay of 0 and PRE has gross delay of 3, // then round the total delay of TxDqs to 0. @@ -343,5 +355,14 @@ MemRecTBeginWLTrain3 ( } NBPtr->SetTrainDly (NBPtr, AccessWrDqsDly, DIMM_BYTE_ACCESS (Dimm, ByteLane), Delay); NBPtr->ChannelPtr->WrDqsDlys[(Dimm * MAX_BYTELANES) + ByteLane] = Delay; + IDS_HDT_CONSOLE (MEM_FLOW, " %02x\n", Delay); } + + IDS_HDT_CONSOLE_DEBUG_CODE ( + IDS_HDT_CONSOLE (MEM_FLOW, "\n\t\t\tWrDqs: "); + for (ByteLane = 0; ByteLane < 8; ByteLane++) { + IDS_HDT_CONSOLE (MEM_FLOW, "%02x ", NBPtr->ChannelPtr->WrDqsDlys[ByteLane]); + } + IDS_HDT_CONSOLE (MEM_FLOW, "\n\n"); + ); } diff --git a/src/vendorcode/amd/agesa/f14/Proc/Recovery/Mem/Tech/mrtthrc.c b/src/vendorcode/amd/agesa/f14/Proc/Recovery/Mem/Tech/mrtthrc.c index 0964a53518..3fbfc6bbe2 100644 --- a/src/vendorcode/amd/agesa/f14/Proc/Recovery/Mem/Tech/mrtthrc.c +++ b/src/vendorcode/amd/agesa/f14/Proc/Recovery/Mem/Tech/mrtthrc.c @@ -9,7 +9,7 @@ * @xrefitem bom "File Content Label" "Release Content" * @e project: AGESA * @e sub-project: (Proc/Recovery/Mem) - * @e \$Revision: 35136 $ @e \$Date: 2010-07-16 11:29:48 +0800 (Fri, 16 Jul 2010) $ + * @e \$Revision: 48803 $ @e \$Date: 2011-03-10 20:18:28 -0700 (Thu, 10 Mar 2011) $ * **/ /* @@ -124,7 +124,7 @@ MemRecTTrainRcvrEnHw ( { UINT8 TempBuffer[64]; UINT8 Count; - UINT32 TestAddrRJ16; + UINT32 TestAddr; UINT8 ChipSel; UINT16 MaxRcvrDly; MEM_NB_BLOCK *NBPtr; @@ -132,12 +132,18 @@ MemRecTTrainRcvrEnHw ( NBPtr = TechPtr->NBPtr; AGESA_TESTPOINT (TpProcMemReceiverEnableTraining , &(NBPtr->MemPtr->StdHeader)); + IDS_HDT_CONSOLE (MEM_STATUS, "\nStart HW RxEn training\n"); // Set environment settings before training MemRecTBeginTraining (TechPtr); ChipSel = NBPtr->DimmToBeUsed << 1; - TestAddrRJ16 = 1 << 21; + TestAddr = 1 << 21; + + IDS_HDT_CONSOLE (MEM_STATUS, "\tDct %d\n", TechPtr->NBPtr->Dct); + IDS_HDT_CONSOLE (MEM_STATUS, "\t\tCS %d\n", ChipSel); + IDS_HDT_CONSOLE (MEM_FLOW, "\t\tTestAddr %x\n", TestAddr); + IDS_HDT_CONSOLE (MEM_FLOW, "\t\t\t Byte: 00 01 02 03 04 05 06 07 ECC\n"); // 1.Prepare the DIMMs for training NBPtr->SetBitField (NBPtr, BFTrDimmSel, ChipSel >> 1); @@ -151,7 +157,7 @@ MemRecTTrainRcvrEnHw ( // 4.BIOS begins sending out of back-to-back reads to create // a continuous stream of DQS edges on the DDR interface. for (Count = 0; Count < 3; Count++) { - NBPtr->ReadPattern (NBPtr, TempBuffer, TestAddrRJ16, 64); + NBPtr->ReadPattern (NBPtr, TempBuffer, TestAddr, 64); } // 6.Wait 200 MEMCLKs. @@ -169,6 +175,7 @@ MemRecTTrainRcvrEnHw ( // Restore environment settings after training MemRecTEndTraining (TechPtr); + IDS_HDT_CONSOLE (MEM_FLOW, "End HW RxEn training\n\n"); } @@ -196,7 +203,11 @@ MemRecTPrepareRcvrEnDlySeed ( UINT16 SeedPreGross; UINT16 DiffSeedGrossSeedPreGross; UINT8 ByteLane; + UINT16 PlatEst; UINT16 *PlatEstSeed; + UINT16 SeedValue[8]; + UINT16 SeedTtl[8]; + UINT16 SeedPre[8]; NBPtr = TechPtr->NBPtr; ChannelPtr = TechPtr->NBPtr->ChannelPtr; @@ -207,9 +218,14 @@ MemRecTPrepareRcvrEnDlySeed ( for (ByteLane = 0; ByteLane < 8; ByteLane++) { // For Pass1, BIOS starts with the delay value obtained from the first pass of write // levelization training that was done in DDR3 Training and add a delay value of 3Bh. - SeedTotal = ChannelPtr->WrDqsDlys[((ChipSel >> 1) * MAX_BYTELANES) + ByteLane] + (PlatEstSeed != NULL) ? PlatEstSeed[ByteLane] : 0x3B; + PlatEst = 0x3B; + NBPtr->FamilySpecificHook[OverrideRcvEnSeed] (NBPtr, &PlatEst); + PlatEst = ((PlatEstSeed != NULL) ? PlatEstSeed[ByteLane] : PlatEst); + SeedTotal = ChannelPtr->WrDqsDlys[((ChipSel >> 1) * MAX_BYTELANES) + ByteLane] + PlatEst; + SeedValue[ByteLane] = PlatEst; + SeedTtl[ByteLane] = SeedTotal; // SeedGross = SeedTotal DIV 32. - SeedGross = (SeedTotal & 0x60) >> 5; + SeedGross = SeedTotal >> 5; // SeedFine = SeedTotal MOD 32. SeedFine = SeedTotal & 0x1F; @@ -233,10 +249,28 @@ MemRecTPrepareRcvrEnDlySeed ( //BIOS programs registers F2x[1, 0]9C_x[51:50] and F2x[1, 0]9C_x52) with SeedPreGrossPass1 //and SeedFinePass1 from the preceding steps. NBPtr->SetTrainDly (NBPtr, AccessPhRecDly, DIMM_BYTE_ACCESS (ChipSel >> 1, ByteLane), (SeedPreGross << 5) | SeedFine); + SeedPre[ByteLane] = (SeedPreGross << 5) | SeedFine; // 202688: Program seed value to RcvEnDly also. NBPtr->SetTrainDly (NBPtr, AccessRcvEnDly, DIMM_BYTE_ACCESS (ChipSel >> 1, ByteLane), SeedGross << 5); } + IDS_HDT_CONSOLE_DEBUG_CODE ( + IDS_HDT_CONSOLE (MEM_FLOW, "\t\t\tSeedValue: "); + for (ByteLane = 0; ByteLane < 8; ByteLane++) { + IDS_HDT_CONSOLE (MEM_FLOW, "%03x ", SeedValue[ByteLane]); + } + IDS_HDT_CONSOLE (MEM_FLOW, "\n"); + + IDS_HDT_CONSOLE (MEM_FLOW, "\t\t\tSeedTotal: "); + for (ByteLane = 0; ByteLane < 8; ByteLane++) { + IDS_HDT_CONSOLE (MEM_FLOW, "%03x ", SeedTtl[ByteLane]); + } + IDS_HDT_CONSOLE (MEM_FLOW, "\n\t\t\t SeedPRE: "); + for (ByteLane = 0; ByteLane < 8; ByteLane++) { + IDS_HDT_CONSOLE (MEM_FLOW, "%03x ", SeedPre[ByteLane]); + } + IDS_HDT_CONSOLE (MEM_FLOW, "\n"); + ); } /* -----------------------------------------------------------------------------*/ @@ -263,17 +297,21 @@ MemRecTProgramRcvrEnDly ( UINT8 ByteLane; UINT16 RcvEnDly; UINT16 MaxDly; + UINT16 RankRcvEnDly[8]; NBPtr = TechPtr->NBPtr; ChannelPtr = TechPtr->NBPtr->ChannelPtr; + IDS_HDT_CONSOLE (MEM_FLOW, "\t\t\t PRE: "); MaxDly = 0; for (ByteLane = 0; ByteLane < 8; ByteLane++) { DiffSeedGrossSeedPreGross = (ChannelPtr->RcvEnDlys[(ChipSel * MAX_BYTELANES) + ByteLane]) & 0x1E0; RcvEnDly = (UINT8) NBPtr->GetTrainDly (NBPtr, AccessPhRecDly, DIMM_BYTE_ACCESS (ChipSel >> 1, ByteLane)); + IDS_HDT_CONSOLE (MEM_FLOW, "%03x ", RcvEnDly); RcvEnDly = RcvEnDly + DiffSeedGrossSeedPreGross; // Add 1 UI to get to the midpoint of preamble RcvEnDly += 0x20; + RankRcvEnDly[ByteLane] = RcvEnDly; if (RcvEnDly > MaxDly) { MaxDly = RcvEnDly; @@ -281,7 +319,13 @@ MemRecTProgramRcvrEnDly ( NBPtr->SetTrainDly (NBPtr, AccessRcvEnDly, DIMM_BYTE_ACCESS ((ChipSel >> 1), ByteLane), RcvEnDly); } - + IDS_HDT_CONSOLE_DEBUG_CODE ( + IDS_HDT_CONSOLE (MEM_FLOW, "\n\t\t\t RxEn: "); + for (ByteLane = 0; ByteLane < 8; ByteLane++) { + IDS_HDT_CONSOLE (MEM_FLOW, "%03x ", RankRcvEnDly[ByteLane]); + } + IDS_HDT_CONSOLE (MEM_FLOW, "\n\n"); + ); return MaxDly; } diff --git a/src/vendorcode/amd/agesa/f14/Proc/Recovery/Mem/Tech/mrttsrc.c b/src/vendorcode/amd/agesa/f14/Proc/Recovery/Mem/Tech/mrttsrc.c index a9adf798ef..afa93798e0 100644 --- a/src/vendorcode/amd/agesa/f14/Proc/Recovery/Mem/Tech/mrttsrc.c +++ b/src/vendorcode/amd/agesa/f14/Proc/Recovery/Mem/Tech/mrttsrc.c @@ -9,7 +9,7 @@ * @xrefitem bom "File Content Label" "Release Content" * @e project: AGESA * @e sub-project: (Proc/Recovery/Mem) - * @e \$Revision: 38442 $ @e \$Date: 2010-09-24 06:39:57 +0800 (Fri, 24 Sep 2010) $ + * @e \$Revision: 48803 $ @e \$Date: 2011-03-10 20:18:28 -0700 (Thu, 10 Mar 2011) $ * **/ /* @@ -263,7 +263,7 @@ MemRecTSetWrDatRdDqs ( for (ByteLane = 0; ByteLane < 8; ByteLane++) { WrDqs = NBPtr->ChannelPtr->WrDqsDlys[(Dimm * MAX_BYTELANES) + ByteLane]; NBPtr->SetTrainDly (NBPtr, AccessWrDatDly, DIMM_BYTE_ACCESS (Dimm, ByteLane), WrDqs + WrDatDly); - RdDqs = (WrDatDly == 0) ? 0x2F : 0x0F; + RdDqs = (WrDatDly == 0) ? 0x2F : 0x012; NBPtr->SetTrainDly (NBPtr, AccessRdDqsDly, DIMM_BYTE_ACCESS (Dimm, ByteLane), RdDqs); } } diff --git a/src/vendorcode/amd/agesa/f14/Proc/Recovery/Mem/mrm.c b/src/vendorcode/amd/agesa/f14/Proc/Recovery/Mem/mrm.c index ce9cb655c0..cc84e47968 100644 --- a/src/vendorcode/amd/agesa/f14/Proc/Recovery/Mem/mrm.c +++ b/src/vendorcode/amd/agesa/f14/Proc/Recovery/Mem/mrm.c @@ -9,7 +9,7 @@ * @xrefitem bom "File Content Label" "Release Content" * @e project: AGESA * @e sub-project: (Proc/Recovery/Mem) - * @e \$Revision: 35136 $ @e \$Date: 2010-07-16 11:29:48 +0800 (Fri, 16 Jul 2010) $ + * @e \$Revision: 48803 $ @e \$Date: 2011-03-10 20:18:28 -0700 (Thu, 10 Mar 2011) $ * **/ /* @@ -270,6 +270,7 @@ MemRecSPDDataProcess ( AgesaStatus = AgesaReadSpdRecovery (0, &SpdParam); if (AgesaStatus == AGESA_SUCCESS) { DimmSPDPtr->DimmPresent = TRUE; + IDS_HDT_CONSOLE (MEM_FLOW, "SPD Socket %d Channel %d Dimm %d: %08x\n", Socket, Channel, Dimm, SpdParam.Buffer); if (!FindSocketWithMem) { FindSocketWithMem = TRUE; } |