diff options
| -rw-r--r-- | src/mainboard/google/volteer/mainboard.c | 20 | ||||
| -rw-r--r-- | src/mainboard/google/volteer/variants/baseboard/devicetree.cb | 8 |
2 files changed, 20 insertions, 8 deletions
diff --git a/src/mainboard/google/volteer/mainboard.c b/src/mainboard/google/volteer/mainboard.c index ead187e0d7..849869a2c8 100644 --- a/src/mainboard/google/volteer/mainboard.c +++ b/src/mainboard/google/volteer/mainboard.c @@ -4,9 +4,12 @@ #include <acpi/acpi.h> #include <baseboard/variants.h> #include <device/device.h> +#include <drivers/spi/tpm/tpm.h> #include <ec/ec.h> #include <fw_config.h> +#include <security/tpm/tss.h> #include <soc/gpio.h> +#include <soc/ramstage.h> #include <vendorcode/google/chromeos/chromeos.h> #include <variant/gpio.h> @@ -38,6 +41,23 @@ static void mainboard_enable(struct device *dev) dev->ops->get_smbios_strings = mainboard_smbios_strings; } +void mainboard_update_soc_chip_config(struct soc_intel_tigerlake_config *cfg) +{ + tlcl_lib_init(); + if (cr50_is_long_interrupt_pulse_enabled()) { + printk(BIOS_INFO, "Enabling S0i3.4\n"); + } else { + /* + * Disable S0i3.4, preventing the GPIO block from switching to + * slow clock. + */ + printk(BIOS_INFO, "Not enabling S0i3.4\n"); + cfg->LpmStateDisableMask |= LPM_S0i3_4; + cfg->gpio_override_pm = 1; + memset(cfg->gpio_pm, 0, sizeof(cfg->gpio_pm)); + } +} + static void mainboard_chip_init(void *chip_info) { const struct pad_config *base_pads; diff --git a/src/mainboard/google/volteer/variants/baseboard/devicetree.cb b/src/mainboard/google/volteer/variants/baseboard/devicetree.cb index 3e9e02ce53..1b8b0d6d03 100644 --- a/src/mainboard/google/volteer/variants/baseboard/devicetree.cb +++ b/src/mainboard/google/volteer/variants/baseboard/devicetree.cb @@ -187,14 +187,6 @@ chip soc/intel/tigerlake register "DdiPort3Ddc" = "0" register "DdiPort4Ddc" = "0" - # Disable PM to allow for shorter irq pulses - register "gpio_override_pm" = "1" - register "gpio_pm[0]" = "0" - register "gpio_pm[1]" = "0" - register "gpio_pm[2]" = "0" - register "gpio_pm[3]" = "0" - register "gpio_pm[4]" = "0" - # Enable "Intel Speed Shift Technology" register "speed_shift_enable" = "1" |