diff options
| -rw-r--r-- | src/northbridge/intel/i945/romstage.c | 3 | ||||
| -rw-r--r-- | src/northbridge/intel/pineview/romstage.c | 2 | ||||
| -rw-r--r-- | src/southbridge/intel/i82801gx/early_init.c | 3 |
3 files changed, 3 insertions, 5 deletions
diff --git a/src/northbridge/intel/i945/romstage.c b/src/northbridge/intel/i945/romstage.c index 479588129d..ff4ccc195e 100644 --- a/src/northbridge/intel/i945/romstage.c +++ b/src/northbridge/intel/i945/romstage.c @@ -61,9 +61,6 @@ void mainboard_romstage_entry(void) s3resume = southbridge_detect_s3_resume(); - /* Enable SPD ROMs and DDR-II DRAM */ - enable_smbus(); - mainboard_pre_raminit_config(s3resume); if (CONFIG(DEBUG_RAM_SETUP)) diff --git a/src/northbridge/intel/pineview/romstage.c b/src/northbridge/intel/pineview/romstage.c index e324c05327..ce4cd5531b 100644 --- a/src/northbridge/intel/pineview/romstage.c +++ b/src/northbridge/intel/pineview/romstage.c @@ -51,8 +51,6 @@ void mainboard_romstage_entry(void) enable_lapic(); - enable_smbus(); - /* Perform some early chipset initialization required * before RAM initialization can work */ diff --git a/src/southbridge/intel/i82801gx/early_init.c b/src/southbridge/intel/i82801gx/early_init.c index f91a5dc1d0..29c45501de 100644 --- a/src/southbridge/intel/i82801gx/early_init.c +++ b/src/southbridge/intel/i82801gx/early_init.c @@ -73,6 +73,9 @@ void i82801gx_early_init(void) { uint8_t reg8; uint32_t reg32; + + enable_smbus(); + /* Setting up Southbridge. In the northbridge code. */ printk(BIOS_DEBUG, "Setting up static southbridge registers..."); i82801gx_setup_bars(); |