aboutsummaryrefslogtreecommitdiff
diff options
context:
space:
mode:
Diffstat
-rw-r--r--src/mainboard/google/reef/variants/baseboard/devicetree.cb12
-rw-r--r--src/mainboard/google/reef/variants/coral/devicetree.cb12
-rw-r--r--src/mainboard/google/reef/variants/pyro/devicetree.cb12
-rw-r--r--src/mainboard/google/reef/variants/sand/devicetree.cb12
-rw-r--r--src/mainboard/google/reef/variants/snappy/devicetree.cb12
-rw-r--r--src/mainboard/intel/apollolake_rvp/devicetree.cb12
-rw-r--r--src/mainboard/intel/glkrvp/variants/baseboard/devicetree.cb12
-rw-r--r--src/mainboard/intel/leafhill/devicetree.cb12
-rw-r--r--src/mainboard/intel/minnow3/devicetree.cb12
-rw-r--r--src/mainboard/siemens/mc_apl1/devicetree.cb12
-rw-r--r--src/soc/intel/apollolake/chip.c8
-rw-r--r--src/soc/intel/apollolake/chip.h8
12 files changed, 64 insertions, 72 deletions
diff --git a/src/mainboard/google/reef/variants/baseboard/devicetree.cb b/src/mainboard/google/reef/variants/baseboard/devicetree.cb
index 0f11f6366c..a8e24cdec9 100644
--- a/src/mainboard/google/reef/variants/baseboard/devicetree.cb
+++ b/src/mainboard/google/reef/variants/baseboard/devicetree.cb
@@ -4,13 +4,13 @@ chip soc/intel/apollolake
device lapic 0 on end
end
- register "pcie_rp0_clkreq_pin" = "0" # wifi/bt
+ register "pcie_rp_clkreq_pin[0]" = "0" # wifi/bt
# Disable unused clkreq of PCIe root ports
- register "pcie_rp1_clkreq_pin" = "CLKREQ_DISABLED"
- register "pcie_rp2_clkreq_pin" = "CLKREQ_DISABLED"
- register "pcie_rp3_clkreq_pin" = "CLKREQ_DISABLED"
- register "pcie_rp4_clkreq_pin" = "CLKREQ_DISABLED"
- register "pcie_rp5_clkreq_pin" = "CLKREQ_DISABLED"
+ register "pcie_rp_clkreq_pin[1]" = "CLKREQ_DISABLED"
+ register "pcie_rp_clkreq_pin[2]" = "CLKREQ_DISABLED"
+ register "pcie_rp_clkreq_pin[3]" = "CLKREQ_DISABLED"
+ register "pcie_rp_clkreq_pin[4]" = "CLKREQ_DISABLED"
+ register "pcie_rp_clkreq_pin[5]" = "CLKREQ_DISABLED"
# GPIO for PERST_0
# If the Board has PERST_0 signal, assign the GPIO
diff --git a/src/mainboard/google/reef/variants/coral/devicetree.cb b/src/mainboard/google/reef/variants/coral/devicetree.cb
index 0a06c76779..c1b7067711 100644
--- a/src/mainboard/google/reef/variants/coral/devicetree.cb
+++ b/src/mainboard/google/reef/variants/coral/devicetree.cb
@@ -4,13 +4,13 @@ chip soc/intel/apollolake
device lapic 0 on end
end
- register "pcie_rp0_clkreq_pin" = "0" # wifi/bt
+ register "pcie_rp_clkreq_pin[0]" = "0" # wifi/bt
# Disable unused clkreq of PCIe root ports
- register "pcie_rp1_clkreq_pin" = "CLKREQ_DISABLED"
- register "pcie_rp2_clkreq_pin" = "CLKREQ_DISABLED"
- register "pcie_rp3_clkreq_pin" = "CLKREQ_DISABLED"
- register "pcie_rp4_clkreq_pin" = "CLKREQ_DISABLED"
- register "pcie_rp5_clkreq_pin" = "CLKREQ_DISABLED"
+ register "pcie_rp_clkreq_pin[1]" = "CLKREQ_DISABLED"
+ register "pcie_rp_clkreq_pin[2]" = "CLKREQ_DISABLED"
+ register "pcie_rp_clkreq_pin[3]" = "CLKREQ_DISABLED"
+ register "pcie_rp_clkreq_pin[4]" = "CLKREQ_DISABLED"
+ register "pcie_rp_clkreq_pin[5]" = "CLKREQ_DISABLED"
# GPIO for PERST_0
# If the Board has PERST_0 signal, assign the GPIO
diff --git a/src/mainboard/google/reef/variants/pyro/devicetree.cb b/src/mainboard/google/reef/variants/pyro/devicetree.cb
index 5bfe2c20f0..cb297d9dce 100644
--- a/src/mainboard/google/reef/variants/pyro/devicetree.cb
+++ b/src/mainboard/google/reef/variants/pyro/devicetree.cb
@@ -4,13 +4,13 @@ chip soc/intel/apollolake
device lapic 0 on end
end
- register "pcie_rp0_clkreq_pin" = "0" # wifi/bt
+ register "pcie_rp_clkreq_pin[0]" = "0" # wifi/bt
# Disable unused clkreq of PCIe root ports
- register "pcie_rp1_clkreq_pin" = "CLKREQ_DISABLED"
- register "pcie_rp2_clkreq_pin" = "CLKREQ_DISABLED"
- register "pcie_rp3_clkreq_pin" = "CLKREQ_DISABLED"
- register "pcie_rp4_clkreq_pin" = "CLKREQ_DISABLED"
- register "pcie_rp5_clkreq_pin" = "CLKREQ_DISABLED"
+ register "pcie_rp_clkreq_pin[1]" = "CLKREQ_DISABLED"
+ register "pcie_rp_clkreq_pin[2]" = "CLKREQ_DISABLED"
+ register "pcie_rp_clkreq_pin[3]" = "CLKREQ_DISABLED"
+ register "pcie_rp_clkreq_pin[4]" = "CLKREQ_DISABLED"
+ register "pcie_rp_clkreq_pin[5]" = "CLKREQ_DISABLED"
# GPIO for PERST_0
# If the Board has PERST_0 signal, assign the GPIO
diff --git a/src/mainboard/google/reef/variants/sand/devicetree.cb b/src/mainboard/google/reef/variants/sand/devicetree.cb
index a6692e6bf7..e53af885e0 100644
--- a/src/mainboard/google/reef/variants/sand/devicetree.cb
+++ b/src/mainboard/google/reef/variants/sand/devicetree.cb
@@ -4,13 +4,13 @@ chip soc/intel/apollolake
device lapic 0 on end
end
- register "pcie_rp0_clkreq_pin" = "0" # wifi/bt
+ register "pcie_rp_clkreq_pin[0]" = "0" # wifi/bt
# Disable unused clkreq of PCIe root ports
- register "pcie_rp1_clkreq_pin" = "CLKREQ_DISABLED"
- register "pcie_rp2_clkreq_pin" = "CLKREQ_DISABLED"
- register "pcie_rp3_clkreq_pin" = "CLKREQ_DISABLED"
- register "pcie_rp4_clkreq_pin" = "CLKREQ_DISABLED"
- register "pcie_rp5_clkreq_pin" = "CLKREQ_DISABLED"
+ register "pcie_rp_clkreq_pin[1]" = "CLKREQ_DISABLED"
+ register "pcie_rp_clkreq_pin[2]" = "CLKREQ_DISABLED"
+ register "pcie_rp_clkreq_pin[3]" = "CLKREQ_DISABLED"
+ register "pcie_rp_clkreq_pin[4]" = "CLKREQ_DISABLED"
+ register "pcie_rp_clkreq_pin[5]" = "CLKREQ_DISABLED"
# GPIO for PERST_0
# If the Board has PERST_0 signal, assign the GPIO
diff --git a/src/mainboard/google/reef/variants/snappy/devicetree.cb b/src/mainboard/google/reef/variants/snappy/devicetree.cb
index 6adf94c1b3..9719368080 100644
--- a/src/mainboard/google/reef/variants/snappy/devicetree.cb
+++ b/src/mainboard/google/reef/variants/snappy/devicetree.cb
@@ -4,13 +4,13 @@ chip soc/intel/apollolake
device lapic 0 on end
end
- register "pcie_rp0_clkreq_pin" = "0" # wifi/bt
+ register "pcie_rp_clkreq_pin[0]" = "0" # wifi/bt
# Disable unused clkreq of PCIe root ports
- register "pcie_rp1_clkreq_pin" = "CLKREQ_DISABLED"
- register "pcie_rp2_clkreq_pin" = "CLKREQ_DISABLED"
- register "pcie_rp3_clkreq_pin" = "CLKREQ_DISABLED"
- register "pcie_rp4_clkreq_pin" = "CLKREQ_DISABLED"
- register "pcie_rp5_clkreq_pin" = "CLKREQ_DISABLED"
+ register "pcie_rp_clkreq_pin[1]" = "CLKREQ_DISABLED"
+ register "pcie_rp_clkreq_pin[2]" = "CLKREQ_DISABLED"
+ register "pcie_rp_clkreq_pin[3]" = "CLKREQ_DISABLED"
+ register "pcie_rp_clkreq_pin[4]" = "CLKREQ_DISABLED"
+ register "pcie_rp_clkreq_pin[5]" = "CLKREQ_DISABLED"
# GPIO for PERST_0
# If the Board has PERST_0 signal, assign the GPIO
diff --git a/src/mainboard/intel/apollolake_rvp/devicetree.cb b/src/mainboard/intel/apollolake_rvp/devicetree.cb
index 746aaf31b2..f7e82a06ca 100644
--- a/src/mainboard/intel/apollolake_rvp/devicetree.cb
+++ b/src/mainboard/intel/apollolake_rvp/devicetree.cb
@@ -1,11 +1,11 @@
chip soc/intel/apollolake
- register "pcie_rp0_clkreq_pin" = "2" # PCIe slot 2
- register "pcie_rp1_clkreq_pin" = "3" # Wifi+BT M2 slot
- register "pcie_rp2_clkreq_pin" = "0" # PCIe slot 1
- register "pcie_rp3_clkreq_pin" = "CLKREQ_DISABLED"
- register "pcie_rp4_clkreq_pin" = "CLKREQ_DISABLED"
- register "pcie_rp5_clkreq_pin" = "CLKREQ_DISABLED"
+ register "pcie_rp_clkreq_pin[0]" = "2" # PCIe slot 2
+ register "pcie_rp_clkreq_pin[1]" = "3" # Wifi+BT M2 slot
+ register "pcie_rp_clkreq_pin[2]" = "0" # PCIe slot 1
+ register "pcie_rp_clkreq_pin[3]" = "CLKREQ_DISABLED"
+ register "pcie_rp_clkreq_pin[4]" = "CLKREQ_DISABLED"
+ register "pcie_rp_clkreq_pin[5]" = "CLKREQ_DISABLED"
device cpu_cluster 0 on
device lapic 0 on end
diff --git a/src/mainboard/intel/glkrvp/variants/baseboard/devicetree.cb b/src/mainboard/intel/glkrvp/variants/baseboard/devicetree.cb
index 45badcddbd..5a544300c0 100644
--- a/src/mainboard/intel/glkrvp/variants/baseboard/devicetree.cb
+++ b/src/mainboard/intel/glkrvp/variants/baseboard/devicetree.cb
@@ -4,13 +4,13 @@ chip soc/intel/apollolake
device lapic 0 on end
end
- register "pcie_rp0_clkreq_pin" = "CLKREQ_DISABLED"
+ register "pcie_rp_clkreq_pin[0]" = "CLKREQ_DISABLED"
# Disable unused clkreq of PCIe root ports
- register "pcie_rp1_clkreq_pin" = "3" # wifi/bt
- register "pcie_rp2_clkreq_pin" = "CLKREQ_DISABLED"
- register "pcie_rp3_clkreq_pin" = "CLKREQ_DISABLED"
- register "pcie_rp4_clkreq_pin" = "1"
- register "pcie_rp5_clkreq_pin" = "CLKREQ_DISABLED"
+ register "pcie_rp_clkreq_pin[1]" = "3" # wifi/bt
+ register "pcie_rp_clkreq_pin[2]" = "CLKREQ_DISABLED"
+ register "pcie_rp_clkreq_pin[3]" = "CLKREQ_DISABLED"
+ register "pcie_rp_clkreq_pin[4]" = "1"
+ register "pcie_rp_clkreq_pin[5]" = "CLKREQ_DISABLED"
# GPIO for PERST_0
# If the Board has PERST_0 signal, assign the GPIO
diff --git a/src/mainboard/intel/leafhill/devicetree.cb b/src/mainboard/intel/leafhill/devicetree.cb
index 2a284d2ee4..6c872b186e 100644
--- a/src/mainboard/intel/leafhill/devicetree.cb
+++ b/src/mainboard/intel/leafhill/devicetree.cb
@@ -1,11 +1,11 @@
chip soc/intel/apollolake
- register "pcie_rp0_clkreq_pin" = "CLKREQ_DISABLED"
- register "pcie_rp1_clkreq_pin" = "CLKREQ_DISABLED"
- register "pcie_rp2_clkreq_pin" = "CLKREQ_DISABLED"
- register "pcie_rp3_clkreq_pin" = "CLKREQ_DISABLED"
- register "pcie_rp4_clkreq_pin" = "CLKREQ_DISABLED"
- register "pcie_rp5_clkreq_pin" = "CLKREQ_DISABLED"
+ register "pcie_rp_clkreq_pin[0]" = "CLKREQ_DISABLED"
+ register "pcie_rp_clkreq_pin[1]" = "CLKREQ_DISABLED"
+ register "pcie_rp_clkreq_pin[2]" = "CLKREQ_DISABLED"
+ register "pcie_rp_clkreq_pin[3]" = "CLKREQ_DISABLED"
+ register "pcie_rp_clkreq_pin[4]" = "CLKREQ_DISABLED"
+ register "pcie_rp_clkreq_pin[5]" = "CLKREQ_DISABLED"
device cpu_cluster 0 on
device lapic 0 on end
diff --git a/src/mainboard/intel/minnow3/devicetree.cb b/src/mainboard/intel/minnow3/devicetree.cb
index 2a284d2ee4..6c872b186e 100644
--- a/src/mainboard/intel/minnow3/devicetree.cb
+++ b/src/mainboard/intel/minnow3/devicetree.cb
@@ -1,11 +1,11 @@
chip soc/intel/apollolake
- register "pcie_rp0_clkreq_pin" = "CLKREQ_DISABLED"
- register "pcie_rp1_clkreq_pin" = "CLKREQ_DISABLED"
- register "pcie_rp2_clkreq_pin" = "CLKREQ_DISABLED"
- register "pcie_rp3_clkreq_pin" = "CLKREQ_DISABLED"
- register "pcie_rp4_clkreq_pin" = "CLKREQ_DISABLED"
- register "pcie_rp5_clkreq_pin" = "CLKREQ_DISABLED"
+ register "pcie_rp_clkreq_pin[0]" = "CLKREQ_DISABLED"
+ register "pcie_rp_clkreq_pin[1]" = "CLKREQ_DISABLED"
+ register "pcie_rp_clkreq_pin[2]" = "CLKREQ_DISABLED"
+ register "pcie_rp_clkreq_pin[3]" = "CLKREQ_DISABLED"
+ register "pcie_rp_clkreq_pin[4]" = "CLKREQ_DISABLED"
+ register "pcie_rp_clkreq_pin[5]" = "CLKREQ_DISABLED"
device cpu_cluster 0 on
device lapic 0 on end
diff --git a/src/mainboard/siemens/mc_apl1/devicetree.cb b/src/mainboard/siemens/mc_apl1/devicetree.cb
index e2b6ceec7f..c1ef76b649 100644
--- a/src/mainboard/siemens/mc_apl1/devicetree.cb
+++ b/src/mainboard/siemens/mc_apl1/devicetree.cb
@@ -7,12 +7,12 @@ chip soc/intel/apollolake
register "sci_irq" = "SCIS_IRQ10"
# Disable unused clkreq of PCIe root ports
- register "pcie_rp0_clkreq_pin" = "3" # PCIe-PCI-Bridge
- register "pcie_rp1_clkreq_pin" = "CLKREQ_DISABLED"
- register "pcie_rp2_clkreq_pin" = "0" # MACPHY
- register "pcie_rp3_clkreq_pin" = "1" # MACPHY
- register "pcie_rp4_clkreq_pin" = "CLKREQ_DISABLED"
- register "pcie_rp5_clkreq_pin" = "CLKREQ_DISABLED"
+ register "pcie_rp_clkreq_pin[0]" = "3" # PCIe-PCI-Bridge
+ register "pcie_rp_clkreq_pin[1]" = "CLKREQ_DISABLED"
+ register "pcie_rp_clkreq_pin[2]" = "0" # MACPHY
+ register "pcie_rp_clkreq_pin[3]" = "1" # MACPHY
+ register "pcie_rp_clkreq_pin[4]" = "CLKREQ_DISABLED"
+ register "pcie_rp_clkreq_pin[5]" = "CLKREQ_DISABLED"
# EMMC TX DATA Delay 1
# Refer to EDS-Vol2-22.3.
diff --git a/src/soc/intel/apollolake/chip.c b/src/soc/intel/apollolake/chip.c
index 53ffdb9f84..60067735ce 100644
--- a/src/soc/intel/apollolake/chip.c
+++ b/src/soc/intel/apollolake/chip.c
@@ -531,12 +531,8 @@ void platform_fsp_silicon_init_params_cb(FSPS_UPD *silupd)
/* Parse device tree and disable unused device*/
parse_devicetree(silconfig);
- silconfig->PcieRpClkReqNumber[0] = cfg->pcie_rp0_clkreq_pin;
- silconfig->PcieRpClkReqNumber[1] = cfg->pcie_rp1_clkreq_pin;
- silconfig->PcieRpClkReqNumber[2] = cfg->pcie_rp2_clkreq_pin;
- silconfig->PcieRpClkReqNumber[3] = cfg->pcie_rp3_clkreq_pin;
- silconfig->PcieRpClkReqNumber[4] = cfg->pcie_rp4_clkreq_pin;
- silconfig->PcieRpClkReqNumber[5] = cfg->pcie_rp5_clkreq_pin;
+ memcpy(silconfig->PcieRpClkReqNumber, cfg->pcie_rp_clkreq_pin,
+ sizeof(silconfig->PcieRpClkReqNumber));
if (cfg->emmc_tx_cmd_cntl != 0)
silconfig->EmmcTxCmdCntl = cfg->emmc_tx_cmd_cntl;
diff --git a/src/soc/intel/apollolake/chip.h b/src/soc/intel/apollolake/chip.h
index 8573cf44b5..7a1d16a1ad 100644
--- a/src/soc/intel/apollolake/chip.h
+++ b/src/soc/intel/apollolake/chip.h
@@ -28,6 +28,7 @@
#include <soc/pm.h>
#include <soc/usb.h>
+#define MAX_PCIE_PORTS 6
#define CLKREQ_DISABLED 0xf
#define APOLLOLAKE_I2C_DEV_MAX 8
@@ -43,12 +44,7 @@ struct soc_intel_apollolake_config {
* four CLKREQ inputs, but six root ports. Root ports without an
* associated CLKREQ signal must be marked with "CLKREQ_DISABLED"
*/
- uint8_t pcie_rp0_clkreq_pin;
- uint8_t pcie_rp1_clkreq_pin;
- uint8_t pcie_rp2_clkreq_pin;
- uint8_t pcie_rp3_clkreq_pin;
- uint8_t pcie_rp4_clkreq_pin;
- uint8_t pcie_rp5_clkreq_pin;
+ uint8_t pcie_rp_clkreq_pin[MAX_PCIE_PORTS];
/* [14:8] DDR mode Number of dealy elements.Each = 125pSec.
* [6:0] SDR mode Number of dealy elements.Each = 125pSec.
generated by cgit v1.2.3 (git 2.39.1) at 2024-07-03 01:38:07 +0000