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-rw-r--r--src/mainboard/google/zork/variants/baseboard/gpio_baseboard_dalboz.c6
-rw-r--r--src/mainboard/google/zork/variants/baseboard/gpio_baseboard_trembyle.c6
2 files changed, 8 insertions, 4 deletions
diff --git a/src/mainboard/google/zork/variants/baseboard/gpio_baseboard_dalboz.c b/src/mainboard/google/zork/variants/baseboard/gpio_baseboard_dalboz.c
index 884862d3dd..a528827879 100644
--- a/src/mainboard/google/zork/variants/baseboard/gpio_baseboard_dalboz.c
+++ b/src/mainboard/google/zork/variants/baseboard/gpio_baseboard_dalboz.c
@@ -30,8 +30,8 @@ static const struct soc_amd_gpio gpio_set_stage_ram[] = {
PAD_NF(GPIO_8, ACP_I2S_LRCLK, PULL_NONE),
/* TOUCHPAD_INT_ODL */
PAD_SCI(GPIO_9, PULL_NONE, EDGE_LOW),
- /* S0iX SLP - (unused - goes to EC */
- PAD_NC(GPIO_10),
+ /* S0iX SLP - goes to EC */
+ PAD_GPO(GPIO_10, HIGH),
/* EC_IN_RW_OD */
PAD_GPI(GPIO_11, PULL_NONE),
/* USI_INT_ODL */
@@ -302,6 +302,8 @@ const __weak struct soc_amd_gpio *variant_bootblock_gpio_table(size_t *size, int
}
static const struct soc_amd_gpio gpio_sleep_table[] = {
+ /* S0iX SLP */
+ PAD_GPO(GPIO_10, LOW),
/* PCIE_RST1_L */
PAD_GPO(GPIO_27, LOW),
/*
diff --git a/src/mainboard/google/zork/variants/baseboard/gpio_baseboard_trembyle.c b/src/mainboard/google/zork/variants/baseboard/gpio_baseboard_trembyle.c
index 818c39bf59..2929c54cdc 100644
--- a/src/mainboard/google/zork/variants/baseboard/gpio_baseboard_trembyle.c
+++ b/src/mainboard/google/zork/variants/baseboard/gpio_baseboard_trembyle.c
@@ -32,8 +32,8 @@ static const struct soc_amd_gpio gpio_set_stage_ram[] = {
PAD_NF(GPIO_8, ACP_I2S_LRCLK, PULL_NONE),
/* TOUCHPAD_INT_ODL */
PAD_SCI(GPIO_9, PULL_NONE, EDGE_LOW),
- /* S0iX SLP - (unused - goes to EC & FPMCU */
- PAD_NC(GPIO_10),
+ /* S0iX SLP - goes to EC & FPMCU */
+ PAD_GPO(GPIO_10, HIGH),
/* USI_INT_ODL */
PAD_GPI(GPIO_12, PULL_NONE),
/* EN_PWR_TOUCHPAD_PS2 */
@@ -342,6 +342,8 @@ const __weak struct soc_amd_gpio *variant_bootblock_gpio_table(size_t *size, int
}
static const struct soc_amd_gpio gpio_sleep_table[] = {
+ /* S0iX SLP */
+ PAD_GPO(GPIO_10, LOW),
/* NVME_AUX_RESET_L */
PAD_GPO(GPIO_40, LOW),
/* EN_PWR_CAMERA */