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-rw-r--r--src/arch/x86/boot/tables.c32
1 files changed, 16 insertions, 16 deletions
diff --git a/src/arch/x86/boot/tables.c b/src/arch/x86/boot/tables.c
index 4448333d61..6355a1b9dc 100644
--- a/src/arch/x86/boot/tables.c
+++ b/src/arch/x86/boot/tables.c
@@ -203,6 +203,22 @@ struct lb_memory *write_tables(void)
}
#endif
+ post_code(0x9e);
+
+#if CONFIG_HAVE_ACPI_RESUME
+/* Only add CBMEM_ID_RESUME when the ramstage isn't relocatable. */
+#if !CONFIG_RELOCATABLE_RAMSTAGE
+ /* Let's prepare the ACPI S3 Resume area now already, so we can rely on
+ * it begin there during reboot time. We don't need the pointer, nor
+ * the result right now. If it fails, ACPI resume will be disabled.
+ */
+ cbmem_add(CBMEM_ID_RESUME, HIGH_MEMORY_SAVE);
+#endif
+#if CONFIG_NORTHBRIDGE_AMD_AGESA_FAMILY14 || CONFIG_NORTHBRIDGE_AMD_AGESA_FAMILY15_TN
+ cbmem_add(CBMEM_ID_RESUME_SCRATCH, CONFIG_HIGH_SCRATCH_MEMORY_SIZE);
+#endif
+#endif
+
#define MAX_COREBOOT_TABLE_SIZE (32 * 1024)
post_code(0x9d);
@@ -230,22 +246,6 @@ struct lb_memory *write_tables(void)
rom_table_start, rom_table_end);
}
- post_code(0x9e);
-
-#if CONFIG_HAVE_ACPI_RESUME
-/* Only add CBMEM_ID_RESUME when the ramstage isn't relocatable. */
-#if !CONFIG_RELOCATABLE_RAMSTAGE
- /* Let's prepare the ACPI S3 Resume area now already, so we can rely on
- * it begin there during reboot time. We don't need the pointer, nor
- * the result right now. If it fails, ACPI resume will be disabled.
- */
- cbmem_add(CBMEM_ID_RESUME, HIGH_MEMORY_SAVE);
-#endif
-#if CONFIG_NORTHBRIDGE_AMD_AGESA_FAMILY14 || CONFIG_NORTHBRIDGE_AMD_AGESA_FAMILY15_TN
- cbmem_add(CBMEM_ID_RESUME_SCRATCH, CONFIG_HIGH_SCRATCH_MEMORY_SIZE);
-#endif
-#endif
-
#if CONFIG_MULTIBOOT
post_code(0x9d);