diff options
55 files changed, 10 insertions, 837 deletions
diff --git a/src/mainboard/advansus/a785e-i/Kconfig b/src/mainboard/advansus/a785e-i/Kconfig index 3753df8eff..fdf08aae3f 100644 --- a/src/mainboard/advansus/a785e-i/Kconfig +++ b/src/mainboard/advansus/a785e-i/Kconfig @@ -15,7 +15,6 @@ config BOARD_SPECIFIC_OPTIONS # dummy select SB_SUPERIO_HWM select HAVE_OPTION_TABLE select HAVE_PIRQ_TABLE - select HAVE_HARD_RESET select SB_HT_CHAIN_UNITID_OFFSET_ONLY select LIFT_BSP_APIC_ID select SERIAL_CPU_INIT diff --git a/src/mainboard/advansus/a785e-i/Makefile.inc b/src/mainboard/advansus/a785e-i/Makefile.inc index d7290afedd..924f9d6a53 100644 --- a/src/mainboard/advansus/a785e-i/Makefile.inc +++ b/src/mainboard/advansus/a785e-i/Makefile.inc @@ -1,5 +1,3 @@ -romstage-y += reset.c -ramstage-y += reset.c #SB800 CIMx share AGESA V5 lib code ifneq ($(CONFIG_CPU_AMD_AGESA),y) diff --git a/src/mainboard/advansus/a785e-i/reset.c b/src/mainboard/advansus/a785e-i/reset.c deleted file mode 100644 index 678bc3d267..0000000000 --- a/src/mainboard/advansus/a785e-i/reset.c +++ /dev/null @@ -1,65 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2011 Advanced Micro Devices, Inc. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA - */ - -#ifndef __PRE_RAM__ -#define __PRE_RAM__ // Use simple device model for this file even in ramstage -#endif -#include <arch/io.h> -#include <reset.h> - -#define HT_INIT_CONTROL 0x6C -#define HTIC_BIOSR_Detect (1<<5) - -#if CONFIG_MAX_PHYSICAL_CPUS > 32 -#define NODE_PCI(x, fn) ((x<32)?(PCI_DEV(CONFIG_CBB,(CONFIG_CDB+x),fn)):(PCI_DEV((CONFIG_CBB-1),(CONFIG_CDB+x-32),fn))) -#else -#define NODE_PCI(x, fn) PCI_DEV(CONFIG_CBB,(CONFIG_CDB+x),fn) -#endif - -static inline void set_bios_reset(void) -{ - u32 nodes, htic; - device_t dev; - int i; - - nodes = ((pci_read_config32(PCI_DEV(CONFIG_CBB, CONFIG_CDB, 0), 0x60) >> 4) & 7) + 1; - for (i = 0; i < nodes; i++) { - dev = NODE_PCI(i, 0); - htic = pci_read_config32(dev, HT_INIT_CONTROL); - htic &= ~HTIC_BIOSR_Detect; - pci_write_config32(dev, HT_INIT_CONTROL, htic); - } -} - -void hard_reset(void) -{ - set_bios_reset(); - /* Try rebooting through port 0xcf9 */ - /* Actually it is not a real hard_reset --- it only reset coherent link table, but not reset link freq and width */ - outb((0 << 3) | (0 << 2) | (1 << 1), 0xcf9); - outb((0 << 3) | (1 << 2) | (1 << 1), 0xcf9); -} - -//SbReset(); -void soft_reset(void) -{ - set_bios_reset(); - /* link reset */ - outb(0x06, 0x0cf9); -} diff --git a/src/mainboard/amd/dinar/Kconfig b/src/mainboard/amd/dinar/Kconfig index 48c1e742c4..3bb225772e 100644 --- a/src/mainboard/amd/dinar/Kconfig +++ b/src/mainboard/amd/dinar/Kconfig @@ -36,7 +36,6 @@ config BOARD_SPECIFIC_OPTIONS # dummy select HAVE_OPTION_TABLE select HAVE_PIRQ_TABLE select HAVE_MP_TABLE - select HAVE_HARD_RESET select HAVE_ACPI_TABLES #TODO select HAVE_ACPI_RESUME select ENABLE_APIC_EXT_ID diff --git a/src/mainboard/amd/dinar/Makefile.inc b/src/mainboard/amd/dinar/Makefile.inc index 42f458b215..8dfe21d499 100644 --- a/src/mainboard/amd/dinar/Makefile.inc +++ b/src/mainboard/amd/dinar/Makefile.inc @@ -29,7 +29,6 @@ ramstage-y += BiosCallOuts.c ramstage-y += sb700_cfg.c ramstage-y += rd890_cfg.c -ramstage-y += reset.c AGESA_PREFIX ?= $(src)/vendorcode/amd/agesa AGESA_ROOT ?= $(AGESA_PREFIX)/$(if $(CONFIG_CPU_AMD_AGESA_FAMILY15),f15,\ diff --git a/src/mainboard/amd/dinar/reset.c b/src/mainboard/amd/dinar/reset.c deleted file mode 100644 index f2a2bcdadc..0000000000 --- a/src/mainboard/amd/dinar/reset.c +++ /dev/null @@ -1,67 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2012 Advanced Micro Devices, Inc. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA - */ - -#ifndef __PRE_RAM__ -#define __PRE_RAM__ // Use simple device model for this file even in ramstage -#endif -#include <arch/io.h> -#include <reset.h> - -#define HT_INIT_CONTROL 0x6C -#define HTIC_BIOSR_Detect (1<<5) - -#if CONFIG_MAX_PHYSICAL_CPUS > 32 -#define NODE_PCI(x, fn) ((x<32)?(PCI_DEV(CONFIG_CBB,(CONFIG_CDB+x),fn)):(PCI_DEV((CONFIG_CBB-1),(CONFIG_CDB+x-32),fn))) -#else -#define NODE_PCI(x, fn) PCI_DEV(CONFIG_CBB,(CONFIG_CDB+x),fn) -#endif - -static inline void set_bios_reset(void) -{ - u32 nodes; - u32 htic; - device_t dev; - int i; - - nodes = ((pci_read_config32(PCI_DEV(CONFIG_CBB, CONFIG_CDB, 0), 0x60) >> 4) & 7) + 1; - for(i = 0; i < nodes; i++) { - dev = NODE_PCI(i, 0); - htic = pci_read_config32(dev, HT_INIT_CONTROL); - htic &= ~HTIC_BIOSR_Detect; - pci_write_config32(dev, HT_INIT_CONTROL, htic); - } -} - -void hard_reset(void) -{ - set_bios_reset(); - /* Try rebooting through port 0xcf9 */ - /* Actually it is not a real hard_reset --- it only reset coherent link table, but not reset link freq and width */ - outb((0 << 3) | (0 << 2) | (1 << 1), 0xcf9); - outb((0 << 3) | (1 << 2) | (1 << 1), 0xcf9); -} - -//SbReset(); -void soft_reset(void) -{ - set_bios_reset(); - /* link reset */ - outb(0x06, 0x0cf9); -} - diff --git a/src/mainboard/amd/inagua/Kconfig b/src/mainboard/amd/inagua/Kconfig index 3c1431efc0..1d8128ec6a 100644 --- a/src/mainboard/amd/inagua/Kconfig +++ b/src/mainboard/amd/inagua/Kconfig @@ -30,7 +30,6 @@ config BOARD_SPECIFIC_OPTIONS # dummy select HAVE_OPTION_TABLE select HAVE_PIRQ_TABLE select HAVE_MP_TABLE - select HAVE_HARD_RESET select SB_HT_CHAIN_UNITID_OFFSET_ONLY select LIFT_BSP_APIC_ID select SERIAL_CPU_INIT diff --git a/src/mainboard/amd/inagua/Makefile.inc b/src/mainboard/amd/inagua/Makefile.inc index b84a03a38b..f5c52f0d2b 100644 --- a/src/mainboard/amd/inagua/Makefile.inc +++ b/src/mainboard/amd/inagua/Makefile.inc @@ -34,5 +34,4 @@ ramstage-y += agesawrapper.c ramstage-y += BiosCallOuts.c ramstage-y += PlatformGnbPcie.c -ramstage-y += reset.c ramstage-y += broadcom.c diff --git a/src/mainboard/amd/inagua/reset.c b/src/mainboard/amd/inagua/reset.c deleted file mode 100644 index bb2482b57b..0000000000 --- a/src/mainboard/amd/inagua/reset.c +++ /dev/null @@ -1,67 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2011 Advanced Micro Devices, Inc. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA - */ - -#ifndef __PRE_RAM__ -#define __PRE_RAM__ // Use simple device model for this file even in ramstage -#endif -#include <arch/io.h> -#include <reset.h> - -#define HT_INIT_CONTROL 0x6C -#define HTIC_BIOSR_Detect (1<<5) - -#if CONFIG_MAX_PHYSICAL_CPUS > 32 -#define NODE_PCI(x, fn) ((x<32)?(PCI_DEV(CONFIG_CBB,(CONFIG_CDB+x),fn)):(PCI_DEV((CONFIG_CBB-1),(CONFIG_CDB+x-32),fn))) -#else -#define NODE_PCI(x, fn) PCI_DEV(CONFIG_CBB,(CONFIG_CDB+x),fn) -#endif - -static inline void set_bios_reset(void) -{ - u32 nodes; - u32 htic; - device_t dev; - int i; - - nodes = ((pci_read_config32(PCI_DEV(CONFIG_CBB, CONFIG_CDB, 0), 0x60) >> 4) & 7) + 1; - for(i = 0; i < nodes; i++) { - dev = NODE_PCI(i, 0); - htic = pci_read_config32(dev, HT_INIT_CONTROL); - htic &= ~HTIC_BIOSR_Detect; - pci_write_config32(dev, HT_INIT_CONTROL, htic); - } -} - -void hard_reset(void) -{ - set_bios_reset(); - /* Try rebooting through port 0xcf9 */ - /* Actually it is not a real hard_reset --- it only reset coherent link table, but not reset link freq and width */ - outb((0 << 3) | (0 << 2) | (1 << 1), 0xcf9); - outb((0 << 3) | (1 << 2) | (1 << 1), 0xcf9); -} - -//SbReset(); -void soft_reset(void) -{ - set_bios_reset(); - /* link reset */ - outb(0x06, 0x0cf9); -} - diff --git a/src/mainboard/amd/parmer/Kconfig b/src/mainboard/amd/parmer/Kconfig index 678432b439..8dd457b9f7 100644 --- a/src/mainboard/amd/parmer/Kconfig +++ b/src/mainboard/amd/parmer/Kconfig @@ -30,7 +30,6 @@ config BOARD_SPECIFIC_OPTIONS # dummy select HAVE_PIRQ_TABLE select HAVE_MP_TABLE select HAVE_ACPI_RESUME - select HAVE_HARD_RESET select SB_HT_CHAIN_UNITID_OFFSET_ONLY select LIFT_BSP_APIC_ID select SERIAL_CPU_INIT diff --git a/src/mainboard/amd/persimmon/Kconfig b/src/mainboard/amd/persimmon/Kconfig index 2e7442c652..5758ecf076 100644 --- a/src/mainboard/amd/persimmon/Kconfig +++ b/src/mainboard/amd/persimmon/Kconfig @@ -31,7 +31,6 @@ config BOARD_SPECIFIC_OPTIONS # dummy select HAVE_PIRQ_TABLE select HAVE_MP_TABLE select HAVE_ACPI_RESUME - select HAVE_HARD_RESET select SB_HT_CHAIN_UNITID_OFFSET_ONLY select LIFT_BSP_APIC_ID select SERIAL_CPU_INIT diff --git a/src/mainboard/amd/persimmon/Makefile.inc b/src/mainboard/amd/persimmon/Makefile.inc index 17443bc23d..e1f18a9836 100644 --- a/src/mainboard/amd/persimmon/Makefile.inc +++ b/src/mainboard/amd/persimmon/Makefile.inc @@ -34,5 +34,4 @@ ramstage-y += agesawrapper.c ramstage-y += BiosCallOuts.c ramstage-y += PlatformGnbPcie.c -ramstage-y += reset.c diff --git a/src/mainboard/amd/persimmon/reset.c b/src/mainboard/amd/persimmon/reset.c deleted file mode 100644 index bb2482b57b..0000000000 --- a/src/mainboard/amd/persimmon/reset.c +++ /dev/null @@ -1,67 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2011 Advanced Micro Devices, Inc. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA - */ - -#ifndef __PRE_RAM__ -#define __PRE_RAM__ // Use simple device model for this file even in ramstage -#endif -#include <arch/io.h> -#include <reset.h> - -#define HT_INIT_CONTROL 0x6C -#define HTIC_BIOSR_Detect (1<<5) - -#if CONFIG_MAX_PHYSICAL_CPUS > 32 -#define NODE_PCI(x, fn) ((x<32)?(PCI_DEV(CONFIG_CBB,(CONFIG_CDB+x),fn)):(PCI_DEV((CONFIG_CBB-1),(CONFIG_CDB+x-32),fn))) -#else -#define NODE_PCI(x, fn) PCI_DEV(CONFIG_CBB,(CONFIG_CDB+x),fn) -#endif - -static inline void set_bios_reset(void) -{ - u32 nodes; - u32 htic; - device_t dev; - int i; - - nodes = ((pci_read_config32(PCI_DEV(CONFIG_CBB, CONFIG_CDB, 0), 0x60) >> 4) & 7) + 1; - for(i = 0; i < nodes; i++) { - dev = NODE_PCI(i, 0); - htic = pci_read_config32(dev, HT_INIT_CONTROL); - htic &= ~HTIC_BIOSR_Detect; - pci_write_config32(dev, HT_INIT_CONTROL, htic); - } -} - -void hard_reset(void) -{ - set_bios_reset(); - /* Try rebooting through port 0xcf9 */ - /* Actually it is not a real hard_reset --- it only reset coherent link table, but not reset link freq and width */ - outb((0 << 3) | (0 << 2) | (1 << 1), 0xcf9); - outb((0 << 3) | (1 << 2) | (1 << 1), 0xcf9); -} - -//SbReset(); -void soft_reset(void) -{ - set_bios_reset(); - /* link reset */ - outb(0x06, 0x0cf9); -} - diff --git a/src/mainboard/amd/south_station/Kconfig b/src/mainboard/amd/south_station/Kconfig index 1c5e401ffa..ec16e6c4b6 100644 --- a/src/mainboard/amd/south_station/Kconfig +++ b/src/mainboard/amd/south_station/Kconfig @@ -30,7 +30,6 @@ config BOARD_SPECIFIC_OPTIONS # dummy select HAVE_OPTION_TABLE select HAVE_PIRQ_TABLE select HAVE_MP_TABLE - select HAVE_HARD_RESET select SB_HT_CHAIN_UNITID_OFFSET_ONLY select LIFT_BSP_APIC_ID select SERIAL_CPU_INIT diff --git a/src/mainboard/amd/south_station/Makefile.inc b/src/mainboard/amd/south_station/Makefile.inc index 59c6cd0ff8..2105082455 100644 --- a/src/mainboard/amd/south_station/Makefile.inc +++ b/src/mainboard/amd/south_station/Makefile.inc @@ -27,5 +27,4 @@ ramstage-y += agesawrapper.c ramstage-y += BiosCallOuts.c ramstage-y += PlatformGnbPcie.c -ramstage-y += reset.c diff --git a/src/mainboard/amd/south_station/reset.c b/src/mainboard/amd/south_station/reset.c deleted file mode 100644 index bb2482b57b..0000000000 --- a/src/mainboard/amd/south_station/reset.c +++ /dev/null @@ -1,67 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2011 Advanced Micro Devices, Inc. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA - */ - -#ifndef __PRE_RAM__ -#define __PRE_RAM__ // Use simple device model for this file even in ramstage -#endif -#include <arch/io.h> -#include <reset.h> - -#define HT_INIT_CONTROL 0x6C -#define HTIC_BIOSR_Detect (1<<5) - -#if CONFIG_MAX_PHYSICAL_CPUS > 32 -#define NODE_PCI(x, fn) ((x<32)?(PCI_DEV(CONFIG_CBB,(CONFIG_CDB+x),fn)):(PCI_DEV((CONFIG_CBB-1),(CONFIG_CDB+x-32),fn))) -#else -#define NODE_PCI(x, fn) PCI_DEV(CONFIG_CBB,(CONFIG_CDB+x),fn) -#endif - -static inline void set_bios_reset(void) -{ - u32 nodes; - u32 htic; - device_t dev; - int i; - - nodes = ((pci_read_config32(PCI_DEV(CONFIG_CBB, CONFIG_CDB, 0), 0x60) >> 4) & 7) + 1; - for(i = 0; i < nodes; i++) { - dev = NODE_PCI(i, 0); - htic = pci_read_config32(dev, HT_INIT_CONTROL); - htic &= ~HTIC_BIOSR_Detect; - pci_write_config32(dev, HT_INIT_CONTROL, htic); - } -} - -void hard_reset(void) -{ - set_bios_reset(); - /* Try rebooting through port 0xcf9 */ - /* Actually it is not a real hard_reset --- it only reset coherent link table, but not reset link freq and width */ - outb((0 << 3) | (0 << 2) | (1 << 1), 0xcf9); - outb((0 << 3) | (1 << 2) | (1 << 1), 0xcf9); -} - -//SbReset(); -void soft_reset(void) -{ - set_bios_reset(); - /* link reset */ - outb(0x06, 0x0cf9); -} - diff --git a/src/mainboard/amd/thatcher/Kconfig b/src/mainboard/amd/thatcher/Kconfig index f619478915..a9227e570f 100644 --- a/src/mainboard/amd/thatcher/Kconfig +++ b/src/mainboard/amd/thatcher/Kconfig @@ -30,7 +30,6 @@ config BOARD_SPECIFIC_OPTIONS # dummy select HAVE_PIRQ_TABLE select HAVE_MP_TABLE select HAVE_ACPI_RESUME - select HAVE_HARD_RESET select SB_HT_CHAIN_UNITID_OFFSET_ONLY select LIFT_BSP_APIC_ID select SERIAL_CPU_INIT diff --git a/src/mainboard/amd/torpedo/Kconfig b/src/mainboard/amd/torpedo/Kconfig index 2c70143ecc..37255f21ff 100644 --- a/src/mainboard/amd/torpedo/Kconfig +++ b/src/mainboard/amd/torpedo/Kconfig @@ -32,7 +32,6 @@ config BOARD_SPECIFIC_OPTIONS # dummy select HAVE_OPTION_TABLE select HAVE_PIRQ_TABLE select HAVE_MP_TABLE - select HAVE_HARD_RESET select SB_HT_CHAIN_UNITID_OFFSET_ONLY select LIFT_BSP_APIC_ID select SERIAL_CPU_INIT diff --git a/src/mainboard/amd/torpedo/Makefile.inc b/src/mainboard/amd/torpedo/Makefile.inc index 26beb37e24..1102ea2619 100644 --- a/src/mainboard/amd/torpedo/Makefile.inc +++ b/src/mainboard/amd/torpedo/Makefile.inc @@ -44,4 +44,3 @@ ramstage-y += dimmSpd.c ramstage-y += BiosCallOuts.c ramstage-y += PlatformGnbPcie.c -ramstage-y += reset.c diff --git a/src/mainboard/amd/torpedo/reset.c b/src/mainboard/amd/torpedo/reset.c deleted file mode 100644 index bb2482b57b..0000000000 --- a/src/mainboard/amd/torpedo/reset.c +++ /dev/null @@ -1,67 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2011 Advanced Micro Devices, Inc. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA - */ - -#ifndef __PRE_RAM__ -#define __PRE_RAM__ // Use simple device model for this file even in ramstage -#endif -#include <arch/io.h> -#include <reset.h> - -#define HT_INIT_CONTROL 0x6C -#define HTIC_BIOSR_Detect (1<<5) - -#if CONFIG_MAX_PHYSICAL_CPUS > 32 -#define NODE_PCI(x, fn) ((x<32)?(PCI_DEV(CONFIG_CBB,(CONFIG_CDB+x),fn)):(PCI_DEV((CONFIG_CBB-1),(CONFIG_CDB+x-32),fn))) -#else -#define NODE_PCI(x, fn) PCI_DEV(CONFIG_CBB,(CONFIG_CDB+x),fn) -#endif - -static inline void set_bios_reset(void) -{ - u32 nodes; - u32 htic; - device_t dev; - int i; - - nodes = ((pci_read_config32(PCI_DEV(CONFIG_CBB, CONFIG_CDB, 0), 0x60) >> 4) & 7) + 1; - for(i = 0; i < nodes; i++) { - dev = NODE_PCI(i, 0); - htic = pci_read_config32(dev, HT_INIT_CONTROL); - htic &= ~HTIC_BIOSR_Detect; - pci_write_config32(dev, HT_INIT_CONTROL, htic); - } -} - -void hard_reset(void) -{ - set_bios_reset(); - /* Try rebooting through port 0xcf9 */ - /* Actually it is not a real hard_reset --- it only reset coherent link table, but not reset link freq and width */ - outb((0 << 3) | (0 << 2) | (1 << 1), 0xcf9); - outb((0 << 3) | (1 << 2) | (1 << 1), 0xcf9); -} - -//SbReset(); -void soft_reset(void) -{ - set_bios_reset(); - /* link reset */ - outb(0x06, 0x0cf9); -} - diff --git a/src/mainboard/amd/union_station/Kconfig b/src/mainboard/amd/union_station/Kconfig index e3e4bfec31..a096d66982 100644 --- a/src/mainboard/amd/union_station/Kconfig +++ b/src/mainboard/amd/union_station/Kconfig @@ -29,7 +29,6 @@ config BOARD_SPECIFIC_OPTIONS # dummy select HAVE_OPTION_TABLE select HAVE_PIRQ_TABLE select HAVE_MP_TABLE - select HAVE_HARD_RESET select SB_HT_CHAIN_UNITID_OFFSET_ONLY select LIFT_BSP_APIC_ID select SERIAL_CPU_INIT diff --git a/src/mainboard/amd/union_station/Makefile.inc b/src/mainboard/amd/union_station/Makefile.inc index 59c6cd0ff8..2105082455 100644 --- a/src/mainboard/amd/union_station/Makefile.inc +++ b/src/mainboard/amd/union_station/Makefile.inc @@ -27,5 +27,4 @@ ramstage-y += agesawrapper.c ramstage-y += BiosCallOuts.c ramstage-y += PlatformGnbPcie.c -ramstage-y += reset.c diff --git a/src/mainboard/amd/union_station/reset.c b/src/mainboard/amd/union_station/reset.c deleted file mode 100644 index bb2482b57b..0000000000 --- a/src/mainboard/amd/union_station/reset.c +++ /dev/null @@ -1,67 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2011 Advanced Micro Devices, Inc. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA - */ - -#ifndef __PRE_RAM__ -#define __PRE_RAM__ // Use simple device model for this file even in ramstage -#endif -#include <arch/io.h> -#include <reset.h> - -#define HT_INIT_CONTROL 0x6C -#define HTIC_BIOSR_Detect (1<<5) - -#if CONFIG_MAX_PHYSICAL_CPUS > 32 -#define NODE_PCI(x, fn) ((x<32)?(PCI_DEV(CONFIG_CBB,(CONFIG_CDB+x),fn)):(PCI_DEV((CONFIG_CBB-1),(CONFIG_CDB+x-32),fn))) -#else -#define NODE_PCI(x, fn) PCI_DEV(CONFIG_CBB,(CONFIG_CDB+x),fn) -#endif - -static inline void set_bios_reset(void) -{ - u32 nodes; - u32 htic; - device_t dev; - int i; - - nodes = ((pci_read_config32(PCI_DEV(CONFIG_CBB, CONFIG_CDB, 0), 0x60) >> 4) & 7) + 1; - for(i = 0; i < nodes; i++) { - dev = NODE_PCI(i, 0); - htic = pci_read_config32(dev, HT_INIT_CONTROL); - htic &= ~HTIC_BIOSR_Detect; - pci_write_config32(dev, HT_INIT_CONTROL, htic); - } -} - -void hard_reset(void) -{ - set_bios_reset(); - /* Try rebooting through port 0xcf9 */ - /* Actually it is not a real hard_reset --- it only reset coherent link table, but not reset link freq and width */ - outb((0 << 3) | (0 << 2) | (1 << 1), 0xcf9); - outb((0 << 3) | (1 << 2) | (1 << 1), 0xcf9); -} - -//SbReset(); -void soft_reset(void) -{ - set_bios_reset(); - /* link reset */ - outb(0x06, 0x0cf9); -} - diff --git a/src/mainboard/asrock/e350m1/Kconfig b/src/mainboard/asrock/e350m1/Kconfig index 4c05037488..bf44af3516 100644 --- a/src/mainboard/asrock/e350m1/Kconfig +++ b/src/mainboard/asrock/e350m1/Kconfig @@ -31,7 +31,6 @@ config BOARD_SPECIFIC_OPTIONS # dummy select HAVE_OPTION_TABLE select HAVE_PIRQ_TABLE select HAVE_MP_TABLE - select HAVE_HARD_RESET select SB_HT_CHAIN_UNITID_OFFSET_ONLY select LIFT_BSP_APIC_ID select SERIAL_CPU_INIT diff --git a/src/mainboard/asrock/e350m1/Makefile.inc b/src/mainboard/asrock/e350m1/Makefile.inc index 59c6cd0ff8..2105082455 100644 --- a/src/mainboard/asrock/e350m1/Makefile.inc +++ b/src/mainboard/asrock/e350m1/Makefile.inc @@ -27,5 +27,4 @@ ramstage-y += agesawrapper.c ramstage-y += BiosCallOuts.c ramstage-y += PlatformGnbPcie.c -ramstage-y += reset.c diff --git a/src/mainboard/asrock/e350m1/reset.c b/src/mainboard/asrock/e350m1/reset.c deleted file mode 100644 index bb2482b57b..0000000000 --- a/src/mainboard/asrock/e350m1/reset.c +++ /dev/null @@ -1,67 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2011 Advanced Micro Devices, Inc. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA - */ - -#ifndef __PRE_RAM__ -#define __PRE_RAM__ // Use simple device model for this file even in ramstage -#endif -#include <arch/io.h> -#include <reset.h> - -#define HT_INIT_CONTROL 0x6C -#define HTIC_BIOSR_Detect (1<<5) - -#if CONFIG_MAX_PHYSICAL_CPUS > 32 -#define NODE_PCI(x, fn) ((x<32)?(PCI_DEV(CONFIG_CBB,(CONFIG_CDB+x),fn)):(PCI_DEV((CONFIG_CBB-1),(CONFIG_CDB+x-32),fn))) -#else -#define NODE_PCI(x, fn) PCI_DEV(CONFIG_CBB,(CONFIG_CDB+x),fn) -#endif - -static inline void set_bios_reset(void) -{ - u32 nodes; - u32 htic; - device_t dev; - int i; - - nodes = ((pci_read_config32(PCI_DEV(CONFIG_CBB, CONFIG_CDB, 0), 0x60) >> 4) & 7) + 1; - for(i = 0; i < nodes; i++) { - dev = NODE_PCI(i, 0); - htic = pci_read_config32(dev, HT_INIT_CONTROL); - htic &= ~HTIC_BIOSR_Detect; - pci_write_config32(dev, HT_INIT_CONTROL, htic); - } -} - -void hard_reset(void) -{ - set_bios_reset(); - /* Try rebooting through port 0xcf9 */ - /* Actually it is not a real hard_reset --- it only reset coherent link table, but not reset link freq and width */ - outb((0 << 3) | (0 << 2) | (1 << 1), 0xcf9); - outb((0 << 3) | (1 << 2) | (1 << 1), 0xcf9); -} - -//SbReset(); -void soft_reset(void) -{ - set_bios_reset(); - /* link reset */ - outb(0x06, 0x0cf9); -} - diff --git a/src/mainboard/asus/f2a85-m/Kconfig b/src/mainboard/asus/f2a85-m/Kconfig index ad2c8b7f3a..f26b8d50b0 100644 --- a/src/mainboard/asus/f2a85-m/Kconfig +++ b/src/mainboard/asus/f2a85-m/Kconfig @@ -31,7 +31,6 @@ config BOARD_SPECIFIC_OPTIONS # dummy select HAVE_PIRQ_TABLE select HAVE_MP_TABLE select HAVE_ACPI_RESUME - select HAVE_HARD_RESET select SB_HT_CHAIN_UNITID_OFFSET_ONLY select LIFT_BSP_APIC_ID select SERIAL_CPU_INIT diff --git a/src/mainboard/asus/m5a88-v/Kconfig b/src/mainboard/asus/m5a88-v/Kconfig index 5318977cb6..942a81d1d1 100644 --- a/src/mainboard/asus/m5a88-v/Kconfig +++ b/src/mainboard/asus/m5a88-v/Kconfig @@ -13,7 +13,6 @@ config BOARD_SPECIFIC_OPTIONS # dummy select SUPERIO_ITE_IT8721F select HAVE_OPTION_TABLE select HAVE_PIRQ_TABLE - select HAVE_HARD_RESET select SB_HT_CHAIN_UNITID_OFFSET_ONLY select LIFT_BSP_APIC_ID select SERIAL_CPU_INIT diff --git a/src/mainboard/asus/m5a88-v/Makefile.inc b/src/mainboard/asus/m5a88-v/Makefile.inc index d7290afedd..924f9d6a53 100644 --- a/src/mainboard/asus/m5a88-v/Makefile.inc +++ b/src/mainboard/asus/m5a88-v/Makefile.inc @@ -1,5 +1,3 @@ -romstage-y += reset.c -ramstage-y += reset.c #SB800 CIMx share AGESA V5 lib code ifneq ($(CONFIG_CPU_AMD_AGESA),y) diff --git a/src/mainboard/asus/m5a88-v/reset.c b/src/mainboard/asus/m5a88-v/reset.c deleted file mode 100644 index 678bc3d267..0000000000 --- a/src/mainboard/asus/m5a88-v/reset.c +++ /dev/null @@ -1,65 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2011 Advanced Micro Devices, Inc. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA - */ - -#ifndef __PRE_RAM__ -#define __PRE_RAM__ // Use simple device model for this file even in ramstage -#endif -#include <arch/io.h> -#include <reset.h> - -#define HT_INIT_CONTROL 0x6C -#define HTIC_BIOSR_Detect (1<<5) - -#if CONFIG_MAX_PHYSICAL_CPUS > 32 -#define NODE_PCI(x, fn) ((x<32)?(PCI_DEV(CONFIG_CBB,(CONFIG_CDB+x),fn)):(PCI_DEV((CONFIG_CBB-1),(CONFIG_CDB+x-32),fn))) -#else -#define NODE_PCI(x, fn) PCI_DEV(CONFIG_CBB,(CONFIG_CDB+x),fn) -#endif - -static inline void set_bios_reset(void) -{ - u32 nodes, htic; - device_t dev; - int i; - - nodes = ((pci_read_config32(PCI_DEV(CONFIG_CBB, CONFIG_CDB, 0), 0x60) >> 4) & 7) + 1; - for (i = 0; i < nodes; i++) { - dev = NODE_PCI(i, 0); - htic = pci_read_config32(dev, HT_INIT_CONTROL); - htic &= ~HTIC_BIOSR_Detect; - pci_write_config32(dev, HT_INIT_CONTROL, htic); - } -} - -void hard_reset(void) -{ - set_bios_reset(); - /* Try rebooting through port 0xcf9 */ - /* Actually it is not a real hard_reset --- it only reset coherent link table, but not reset link freq and width */ - outb((0 << 3) | (0 << 2) | (1 << 1), 0xcf9); - outb((0 << 3) | (1 << 2) | (1 << 1), 0xcf9); -} - -//SbReset(); -void soft_reset(void) -{ - set_bios_reset(); - /* link reset */ - outb(0x06, 0x0cf9); -} diff --git a/src/mainboard/avalue/eax-785e/Kconfig b/src/mainboard/avalue/eax-785e/Kconfig index 11fc657f1d..99b9c67f56 100644 --- a/src/mainboard/avalue/eax-785e/Kconfig +++ b/src/mainboard/avalue/eax-785e/Kconfig @@ -15,7 +15,6 @@ config BOARD_SPECIFIC_OPTIONS # dummy select SB_SUPERIO_HWM select HAVE_OPTION_TABLE select HAVE_PIRQ_TABLE - select HAVE_HARD_RESET select SB_HT_CHAIN_UNITID_OFFSET_ONLY select LIFT_BSP_APIC_ID select SERIAL_CPU_INIT diff --git a/src/mainboard/avalue/eax-785e/Makefile.inc b/src/mainboard/avalue/eax-785e/Makefile.inc index d7290afedd..924f9d6a53 100644 --- a/src/mainboard/avalue/eax-785e/Makefile.inc +++ b/src/mainboard/avalue/eax-785e/Makefile.inc @@ -1,5 +1,3 @@ -romstage-y += reset.c -ramstage-y += reset.c #SB800 CIMx share AGESA V5 lib code ifneq ($(CONFIG_CPU_AMD_AGESA),y) diff --git a/src/mainboard/avalue/eax-785e/reset.c b/src/mainboard/avalue/eax-785e/reset.c deleted file mode 100644 index 678bc3d267..0000000000 --- a/src/mainboard/avalue/eax-785e/reset.c +++ /dev/null @@ -1,65 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2011 Advanced Micro Devices, Inc. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA - */ - -#ifndef __PRE_RAM__ -#define __PRE_RAM__ // Use simple device model for this file even in ramstage -#endif -#include <arch/io.h> -#include <reset.h> - -#define HT_INIT_CONTROL 0x6C -#define HTIC_BIOSR_Detect (1<<5) - -#if CONFIG_MAX_PHYSICAL_CPUS > 32 -#define NODE_PCI(x, fn) ((x<32)?(PCI_DEV(CONFIG_CBB,(CONFIG_CDB+x),fn)):(PCI_DEV((CONFIG_CBB-1),(CONFIG_CDB+x-32),fn))) -#else -#define NODE_PCI(x, fn) PCI_DEV(CONFIG_CBB,(CONFIG_CDB+x),fn) -#endif - -static inline void set_bios_reset(void) -{ - u32 nodes, htic; - device_t dev; - int i; - - nodes = ((pci_read_config32(PCI_DEV(CONFIG_CBB, CONFIG_CDB, 0), 0x60) >> 4) & 7) + 1; - for (i = 0; i < nodes; i++) { - dev = NODE_PCI(i, 0); - htic = pci_read_config32(dev, HT_INIT_CONTROL); - htic &= ~HTIC_BIOSR_Detect; - pci_write_config32(dev, HT_INIT_CONTROL, htic); - } -} - -void hard_reset(void) -{ - set_bios_reset(); - /* Try rebooting through port 0xcf9 */ - /* Actually it is not a real hard_reset --- it only reset coherent link table, but not reset link freq and width */ - outb((0 << 3) | (0 << 2) | (1 << 1), 0xcf9); - outb((0 << 3) | (1 << 2) | (1 << 1), 0xcf9); -} - -//SbReset(); -void soft_reset(void) -{ - set_bios_reset(); - /* link reset */ - outb(0x06, 0x0cf9); -} diff --git a/src/mainboard/lippert/frontrunner-af/Kconfig b/src/mainboard/lippert/frontrunner-af/Kconfig index d326746be3..9ddf97032b 100644 --- a/src/mainboard/lippert/frontrunner-af/Kconfig +++ b/src/mainboard/lippert/frontrunner-af/Kconfig @@ -35,7 +35,6 @@ config BOARD_SPECIFIC_OPTIONS # dummy # erases 28 KB and writes 10 KB register dumps to SPI flash on every # boot, wasting 3 s and causing wear! Therefore disable S3 for now. #select HAVE_ACPI_RESUME - select HAVE_HARD_RESET select SB_HT_CHAIN_UNITID_OFFSET_ONLY select LIFT_BSP_APIC_ID select SERIAL_CPU_INIT diff --git a/src/mainboard/lippert/frontrunner-af/Makefile.inc b/src/mainboard/lippert/frontrunner-af/Makefile.inc index 17443bc23d..e1f18a9836 100644 --- a/src/mainboard/lippert/frontrunner-af/Makefile.inc +++ b/src/mainboard/lippert/frontrunner-af/Makefile.inc @@ -34,5 +34,4 @@ ramstage-y += agesawrapper.c ramstage-y += BiosCallOuts.c ramstage-y += PlatformGnbPcie.c -ramstage-y += reset.c diff --git a/src/mainboard/lippert/frontrunner-af/reset.c b/src/mainboard/lippert/frontrunner-af/reset.c deleted file mode 100644 index bb2482b57b..0000000000 --- a/src/mainboard/lippert/frontrunner-af/reset.c +++ /dev/null @@ -1,67 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2011 Advanced Micro Devices, Inc. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA - */ - -#ifndef __PRE_RAM__ -#define __PRE_RAM__ // Use simple device model for this file even in ramstage -#endif -#include <arch/io.h> -#include <reset.h> - -#define HT_INIT_CONTROL 0x6C -#define HTIC_BIOSR_Detect (1<<5) - -#if CONFIG_MAX_PHYSICAL_CPUS > 32 -#define NODE_PCI(x, fn) ((x<32)?(PCI_DEV(CONFIG_CBB,(CONFIG_CDB+x),fn)):(PCI_DEV((CONFIG_CBB-1),(CONFIG_CDB+x-32),fn))) -#else -#define NODE_PCI(x, fn) PCI_DEV(CONFIG_CBB,(CONFIG_CDB+x),fn) -#endif - -static inline void set_bios_reset(void) -{ - u32 nodes; - u32 htic; - device_t dev; - int i; - - nodes = ((pci_read_config32(PCI_DEV(CONFIG_CBB, CONFIG_CDB, 0), 0x60) >> 4) & 7) + 1; - for(i = 0; i < nodes; i++) { - dev = NODE_PCI(i, 0); - htic = pci_read_config32(dev, HT_INIT_CONTROL); - htic &= ~HTIC_BIOSR_Detect; - pci_write_config32(dev, HT_INIT_CONTROL, htic); - } -} - -void hard_reset(void) -{ - set_bios_reset(); - /* Try rebooting through port 0xcf9 */ - /* Actually it is not a real hard_reset --- it only reset coherent link table, but not reset link freq and width */ - outb((0 << 3) | (0 << 2) | (1 << 1), 0xcf9); - outb((0 << 3) | (1 << 2) | (1 << 1), 0xcf9); -} - -//SbReset(); -void soft_reset(void) -{ - set_bios_reset(); - /* link reset */ - outb(0x06, 0x0cf9); -} - diff --git a/src/mainboard/lippert/toucan-af/Kconfig b/src/mainboard/lippert/toucan-af/Kconfig index e8f5896fbd..07fbbeaeaa 100644 --- a/src/mainboard/lippert/toucan-af/Kconfig +++ b/src/mainboard/lippert/toucan-af/Kconfig @@ -37,7 +37,6 @@ config BOARD_SPECIFIC_OPTIONS # dummy # erases 28 KB and writes 10 KB register dumps to SPI flash on every # boot, wasting 3 s and causing wear! Therefore disable S3 for now. #select HAVE_ACPI_RESUME - select HAVE_HARD_RESET select SB_HT_CHAIN_UNITID_OFFSET_ONLY select LIFT_BSP_APIC_ID select SERIAL_CPU_INIT diff --git a/src/mainboard/lippert/toucan-af/Makefile.inc b/src/mainboard/lippert/toucan-af/Makefile.inc index 17443bc23d..e1f18a9836 100644 --- a/src/mainboard/lippert/toucan-af/Makefile.inc +++ b/src/mainboard/lippert/toucan-af/Makefile.inc @@ -34,5 +34,4 @@ ramstage-y += agesawrapper.c ramstage-y += BiosCallOuts.c ramstage-y += PlatformGnbPcie.c -ramstage-y += reset.c diff --git a/src/mainboard/lippert/toucan-af/reset.c b/src/mainboard/lippert/toucan-af/reset.c deleted file mode 100644 index bb2482b57b..0000000000 --- a/src/mainboard/lippert/toucan-af/reset.c +++ /dev/null @@ -1,67 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2011 Advanced Micro Devices, Inc. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA - */ - -#ifndef __PRE_RAM__ -#define __PRE_RAM__ // Use simple device model for this file even in ramstage -#endif -#include <arch/io.h> -#include <reset.h> - -#define HT_INIT_CONTROL 0x6C -#define HTIC_BIOSR_Detect (1<<5) - -#if CONFIG_MAX_PHYSICAL_CPUS > 32 -#define NODE_PCI(x, fn) ((x<32)?(PCI_DEV(CONFIG_CBB,(CONFIG_CDB+x),fn)):(PCI_DEV((CONFIG_CBB-1),(CONFIG_CDB+x-32),fn))) -#else -#define NODE_PCI(x, fn) PCI_DEV(CONFIG_CBB,(CONFIG_CDB+x),fn) -#endif - -static inline void set_bios_reset(void) -{ - u32 nodes; - u32 htic; - device_t dev; - int i; - - nodes = ((pci_read_config32(PCI_DEV(CONFIG_CBB, CONFIG_CDB, 0), 0x60) >> 4) & 7) + 1; - for(i = 0; i < nodes; i++) { - dev = NODE_PCI(i, 0); - htic = pci_read_config32(dev, HT_INIT_CONTROL); - htic &= ~HTIC_BIOSR_Detect; - pci_write_config32(dev, HT_INIT_CONTROL, htic); - } -} - -void hard_reset(void) -{ - set_bios_reset(); - /* Try rebooting through port 0xcf9 */ - /* Actually it is not a real hard_reset --- it only reset coherent link table, but not reset link freq and width */ - outb((0 << 3) | (0 << 2) | (1 << 1), 0xcf9); - outb((0 << 3) | (1 << 2) | (1 << 1), 0xcf9); -} - -//SbReset(); -void soft_reset(void) -{ - set_bios_reset(); - /* link reset */ - outb(0x06, 0x0cf9); -} - diff --git a/src/mainboard/supermicro/h8qgi/Kconfig b/src/mainboard/supermicro/h8qgi/Kconfig index 1184a93f86..f13593e6e7 100644 --- a/src/mainboard/supermicro/h8qgi/Kconfig +++ b/src/mainboard/supermicro/h8qgi/Kconfig @@ -34,7 +34,6 @@ config BOARD_SPECIFIC_OPTIONS select HAVE_OPTION_TABLE select HAVE_PIRQ_TABLE select HAVE_MP_TABLE - select HAVE_HARD_RESET select SERIAL_CPU_INIT select HAVE_ACPI_TABLES select BOARD_ROMSIZE_KB_2048 diff --git a/src/mainboard/supermicro/h8qgi/Makefile.inc b/src/mainboard/supermicro/h8qgi/Makefile.inc index 451e013ac1..77e87195d8 100644 --- a/src/mainboard/supermicro/h8qgi/Makefile.inc +++ b/src/mainboard/supermicro/h8qgi/Makefile.inc @@ -19,7 +19,6 @@ romstage-y += rd890_cfg.c romstage-y += sb700_cfg.c -romstage-y += reset.c romstage-y += buildOpts.c romstage-y += agesawrapper.c romstage-y += BiosCallOuts.c @@ -27,7 +26,6 @@ romstage-y += platform_oem.c ramstage-y += rd890_cfg.c ramstage-y += sb700_cfg.c -ramstage-y += reset.c ramstage-y += buildOpts.c ramstage-y += agesawrapper.c ramstage-y += BiosCallOuts.c diff --git a/src/mainboard/supermicro/h8scm/Kconfig b/src/mainboard/supermicro/h8scm/Kconfig index 95e6f8183a..1eadc368a9 100644 --- a/src/mainboard/supermicro/h8scm/Kconfig +++ b/src/mainboard/supermicro/h8scm/Kconfig @@ -34,7 +34,6 @@ config BOARD_SPECIFIC_OPTIONS select HAVE_OPTION_TABLE select HAVE_PIRQ_TABLE select HAVE_MP_TABLE - select HAVE_HARD_RESET select SERIAL_CPU_INIT select HAVE_ACPI_TABLES select BOARD_ROMSIZE_KB_4096 diff --git a/src/mainboard/supermicro/h8scm/Makefile.inc b/src/mainboard/supermicro/h8scm/Makefile.inc index 451e013ac1..77e87195d8 100644 --- a/src/mainboard/supermicro/h8scm/Makefile.inc +++ b/src/mainboard/supermicro/h8scm/Makefile.inc @@ -19,7 +19,6 @@ romstage-y += rd890_cfg.c romstage-y += sb700_cfg.c -romstage-y += reset.c romstage-y += buildOpts.c romstage-y += agesawrapper.c romstage-y += BiosCallOuts.c @@ -27,7 +26,6 @@ romstage-y += platform_oem.c ramstage-y += rd890_cfg.c ramstage-y += sb700_cfg.c -ramstage-y += reset.c ramstage-y += buildOpts.c ramstage-y += agesawrapper.c ramstage-y += BiosCallOuts.c diff --git a/src/mainboard/tyan/s8226/Kconfig b/src/mainboard/tyan/s8226/Kconfig index 1db75b3f62..0d832fe9e0 100644 --- a/src/mainboard/tyan/s8226/Kconfig +++ b/src/mainboard/tyan/s8226/Kconfig @@ -34,7 +34,6 @@ config BOARD_SPECIFIC_OPTIONS select HAVE_OPTION_TABLE select HAVE_PIRQ_TABLE select HAVE_MP_TABLE - select HAVE_HARD_RESET select SERIAL_CPU_INIT select HAVE_ACPI_TABLES select BOARD_ROMSIZE_KB_4096 diff --git a/src/mainboard/tyan/s8226/Makefile.inc b/src/mainboard/tyan/s8226/Makefile.inc index 451e013ac1..77e87195d8 100644 --- a/src/mainboard/tyan/s8226/Makefile.inc +++ b/src/mainboard/tyan/s8226/Makefile.inc @@ -19,7 +19,6 @@ romstage-y += rd890_cfg.c romstage-y += sb700_cfg.c -romstage-y += reset.c romstage-y += buildOpts.c romstage-y += agesawrapper.c romstage-y += BiosCallOuts.c @@ -27,7 +26,6 @@ romstage-y += platform_oem.c ramstage-y += rd890_cfg.c ramstage-y += sb700_cfg.c -ramstage-y += reset.c ramstage-y += buildOpts.c ramstage-y += agesawrapper.c ramstage-y += BiosCallOuts.c diff --git a/src/southbridge/amd/agesa/hudson/Kconfig b/src/southbridge/amd/agesa/hudson/Kconfig index b346863d07..af305eed72 100644 --- a/src/southbridge/amd/agesa/hudson/Kconfig +++ b/src/southbridge/amd/agesa/hudson/Kconfig @@ -21,6 +21,7 @@ config SOUTHBRIDGE_AMD_AGESA_HUDSON bool select IOAPIC select HAVE_USBDEBUG + select HAVE_HARD_RESET if SOUTHBRIDGE_AMD_AGESA_HUDSON diff --git a/src/southbridge/amd/cimx/sb700/Kconfig b/src/southbridge/amd/cimx/sb700/Kconfig index e98d3ed22d..97cdf1c229 100644 --- a/src/southbridge/amd/cimx/sb700/Kconfig +++ b/src/southbridge/amd/cimx/sb700/Kconfig @@ -21,6 +21,7 @@ config SOUTHBRIDGE_AMD_CIMX_SB700 bool select IOAPIC select AMD_SB_CIMX + select HAVE_HARD_RESET if SOUTHBRIDGE_AMD_CIMX_SB700 config SATA_CONTROLLER_MODE diff --git a/src/southbridge/amd/cimx/sb700/Makefile.inc b/src/southbridge/amd/cimx/sb700/Makefile.inc index 94a0deadd6..268629f45c 100644 --- a/src/southbridge/amd/cimx/sb700/Makefile.inc +++ b/src/southbridge/amd/cimx/sb700/Makefile.inc @@ -22,8 +22,10 @@ romstage-y += early.c romstage-y += smbus.c +romstage-y += reset.c ramstage-y += late.c +ramstage-y += reset.c ramstage-y += smbus.c ramstage-y += lpc.c diff --git a/src/mainboard/supermicro/h8qgi/reset.c b/src/southbridge/amd/cimx/sb700/reset.c index 7a96aa4595..7a96aa4595 100644 --- a/src/mainboard/supermicro/h8qgi/reset.c +++ b/src/southbridge/amd/cimx/sb700/reset.c diff --git a/src/southbridge/amd/cimx/sb800/Kconfig b/src/southbridge/amd/cimx/sb800/Kconfig index 554d8c7009..b82409d883 100644 --- a/src/southbridge/amd/cimx/sb800/Kconfig +++ b/src/southbridge/amd/cimx/sb800/Kconfig @@ -22,6 +22,7 @@ config SOUTHBRIDGE_AMD_CIMX_SB800 default n select IOAPIC select AMD_SB_CIMX + select HAVE_HARD_RESET if SOUTHBRIDGE_AMD_CIMX_SB800 config BOOTBLOCK_SOUTHBRIDGE_INIT diff --git a/src/southbridge/amd/cimx/sb800/Makefile.inc b/src/southbridge/amd/cimx/sb800/Makefile.inc index 524c2d3274..831cc2ecbd 100644 --- a/src/southbridge/amd/cimx/sb800/Makefile.inc +++ b/src/southbridge/amd/cimx/sb800/Makefile.inc @@ -23,9 +23,11 @@ romstage-y += cfg.c romstage-y += early.c romstage-y += smbus.c +romstage-y += reset.c ramstage-y += cfg.c ramstage-y += late.c +ramstage-y += reset.c ramstage-$(CONFIG_SB800_MANUAL_FAN_CONTROL) += fan.c ramstage-$(CONFIG_SB800_IMC_FAN_CONTROL) += fan.c diff --git a/src/mainboard/supermicro/h8scm/reset.c b/src/southbridge/amd/cimx/sb800/reset.c index 7a96aa4595..7a96aa4595 100644 --- a/src/mainboard/supermicro/h8scm/reset.c +++ b/src/southbridge/amd/cimx/sb800/reset.c diff --git a/src/southbridge/amd/cimx/sb900/Kconfig b/src/southbridge/amd/cimx/sb900/Kconfig index aa30e561c6..5d3b0a1328 100755 --- a/src/southbridge/amd/cimx/sb900/Kconfig +++ b/src/southbridge/amd/cimx/sb900/Kconfig @@ -22,6 +22,7 @@ config SOUTHBRIDGE_AMD_CIMX_SB900 default n select IOAPIC select AMD_SB_CIMX + select HAVE_HARD_RESET if SOUTHBRIDGE_AMD_CIMX_SB900 config SATA_CONTROLLER_MODE diff --git a/src/southbridge/amd/cimx/sb900/Makefile.inc b/src/southbridge/amd/cimx/sb900/Makefile.inc index ebb3e3f62d..cc4c553590 100755 --- a/src/southbridge/amd/cimx/sb900/Makefile.inc +++ b/src/southbridge/amd/cimx/sb900/Makefile.inc @@ -23,10 +23,12 @@ romstage-y += cfg.c romstage-y += early.c romstage-y += smbus.c +romstage-y += reset.c ramstage-y += cfg.c ramstage-y += early.c ramstage-y += late.c +ramstage-y += reset.c ramstage-y += smbus.c ramstage-y += lpc.c diff --git a/src/mainboard/tyan/s8226/reset.c b/src/southbridge/amd/cimx/sb900/reset.c index 7a96aa4595..7a96aa4595 100644 --- a/src/mainboard/tyan/s8226/reset.c +++ b/src/southbridge/amd/cimx/sb900/reset.c |