diff options
| -rw-r--r-- | src/arch/i386/include/arch/romcc_io.h | 71 | ||||
| -rw-r--r-- | src/mainboard/amd/solo/auto.c | 88 | ||||
| -rw-r--r-- | src/northbridge/amd/amdk8/coherent_ht.c | 10 | ||||
| -rw-r--r-- | src/northbridge/amd/amdk8/early_ht.c | 14 | ||||
| -rw-r--r-- | src/northbridge/amd/amdk8/raminit.c | 25 | ||||
| -rw-r--r-- | src/southbridge/amd/amd8111/amd8111_early_smbus.c | 12 | ||||
| -rw-r--r-- | src/southbridge/amd/amd8111/amd8111_enable_rom.c | 9 |
7 files changed, 123 insertions, 106 deletions
diff --git a/src/arch/i386/include/arch/romcc_io.h b/src/arch/i386/include/arch/romcc_io.h index 8366a4d529..677133f2a9 100644 --- a/src/arch/i386/include/arch/romcc_io.h +++ b/src/arch/i386/include/arch/romcc_io.h @@ -53,9 +53,15 @@ static void wrmsr(unsigned long index, msr_t msr) (((FN) & 0x07) << 8) | \ ((WHERE) & 0xFF)) +#define PCI_DEV(BUS, DEV, FN) ( \ + (((BUS) & 0xFF) << 16) | \ + (((DEV) & 0x1f) << 11) | \ + (((FN) & 0x7) << 8)) + #define PCI_ID(VENDOR_ID, DEVICE_ID) \ ((((DEVICE_ID) & 0xFFFF) << 16) | ((VENDOR_ID) & 0xFFFF)) +#if 0 static unsigned char pci_read_config8(unsigned addr) { outl(0x80000000 | (addr & ~3), 0xCF8); @@ -104,3 +110,68 @@ static unsigned pci_locate_device(unsigned pci_id, unsigned addr) } return ~0U; } +#else +typedef unsigned device_t; + +static unsigned char pci_read_config8(device_t dev, unsigned where) +{ + unsigned addr; + addr = dev | where; + outl(0x80000000 | (addr & ~3), 0xCF8); + return inb(0xCFC + (addr & 3)); +} + +static unsigned short pci_read_config16(device_t dev, unsigned where) +{ + unsigned addr; + addr = dev | where; + outl(0x80000000 | (addr & ~3), 0xCF8); + return inw(0xCFC + (addr & 2)); +} + +static unsigned int pci_read_config32(device_t dev, unsigned where) +{ + unsigned addr; + addr = dev | where; + outl(0x80000000 | (addr & ~3), 0xCF8); + return inl(0xCFC); +} + +static void pci_write_config8(device_t dev, unsigned where, unsigned char value) +{ + unsigned addr; + addr = dev | where; + outl(0x80000000 | (addr & ~3), 0xCF8); + outb(value, 0xCFC + (addr & 3)); +} + +static void pci_write_config16(device_t dev, unsigned where, unsigned short value) +{ + unsigned addr; + addr = dev | where; + outl(0x80000000 | (addr & ~3), 0xCF8); + outw(value, 0xCFC + (addr & 2)); +} + +static void pci_write_config32(device_t dev, unsigned where, unsigned int value) +{ + unsigned addr; + addr = dev | where; + outl(0x80000000 | (addr & ~3), 0xCF8); + outl(value, 0xCFC); +} + +#define PCI_DEV_INVALID (0xffffffffU) +static device_t pci_locate_device(unsigned pci_id, device_t dev) +{ + for(; dev <= PCI_DEV(255, 31, 7); dev += PCI_DEV(0,0,1)) { + unsigned int id; + id = pci_read_config32(dev, 0); + if (id == pci_id) { + return dev; + } + } + return PCI_DEV_INVALID; +} + +#endif diff --git a/src/mainboard/amd/solo/auto.c b/src/mainboard/amd/solo/auto.c index 906c3f9137..33dea8e80d 100644 --- a/src/mainboard/amd/solo/auto.c +++ b/src/mainboard/amd/solo/auto.c @@ -33,7 +33,7 @@ static int cpu_init_detected(void) unsigned long htic; - htic = pci_read_config32(PCI_ADDR(0, 0x18, 0, HT_INIT_CONTROL)); + htic = pci_read_config32(PCI_DEV(0, 0x18, 0), HT_INIT_CONTROL); #if 0 print_debug("htic: "); print_debug_hex32(htic); @@ -59,21 +59,21 @@ static int cpu_init_detected(void) static void print_pci_devices(void) { - uint32_t addr; - for(addr = PCI_ADDR(0, 0, 0, 0); - addr <= PCI_ADDR(0, 0x1f, 0x7, 0); - addr += PCI_ADDR(0,0,1,0)) { + device_t dev; + for(dev = PCI_DEV(0, 0, 0); + dev <= PCI_DEV(0, 0x1f, 0x7); + dev += PCI_DEV(0,0,1)) { uint32_t id; - id = pci_read_config32(addr + PCI_VENDOR_ID); + id = pci_read_config32(dev, PCI_VENDOR_ID); if (((id & 0xffff) == 0x0000) || ((id & 0xffff) == 0xffff) || (((id >> 16) & 0xffff) == 0xffff) || (((id >> 16) & 0xffff) == 0x0000)) { continue; } print_debug("PCI: 00:"); - print_debug_hex8(addr >> 11); + print_debug_hex8(dev >> 11); print_debug_char('.'); - print_debug_hex8((addr >> 8) & 7); + print_debug_hex8((dev >> 8) & 7); print_debug("\r\n"); } } @@ -111,82 +111,10 @@ static void dump_spd_registers(void) } -static void pnp_write_config(unsigned char port, unsigned char value, unsigned char reg) -{ - outb(reg, port); - outb(value, port +1); -} - -static unsigned char pnp_read_config(unsigned char port, unsigned char reg) -{ - outb(reg, port); - return inb(port +1); -} - -static void pnp_set_logical_device(unsigned char port, int device) -{ - pnp_write_config(port, device, 0x07); -} - -static void pnp_set_enable(unsigned char port, int enable) -{ - pnp_write_config(port, enable?0x1:0x0, 0x30); -} - -static int pnp_read_enable(unsigned char port) -{ - return !!pnp_read_config(port, 0x30); -} - -static void pnp_set_iobase0(unsigned char port, unsigned iobase) -{ - pnp_write_config(port, (iobase >> 8) & 0xff, 0x60); - pnp_write_config(port, iobase & 0xff, 0x61); -} - -static void pnp_set_iobase1(unsigned char port, unsigned iobase) -{ - pnp_write_config(port, (iobase >> 8) & 0xff, 0x62); - pnp_write_config(port, iobase & 0xff, 0x63); -} - -static void pnp_set_irq0(unsigned char port, unsigned irq) -{ - pnp_write_config(port, irq, 0x70); -} - -static void pnp_set_irq1(unsigned char port, unsigned irq) -{ - pnp_write_config(port, irq, 0x72); -} - -static void pnp_set_drq(unsigned char port, unsigned drq) -{ - pnp_write_config(port, drq & 0xff, 0x74); -} - -#define PC87360_FDC 0x00 -#define PC87360_PP 0x01 -#define PC87360_SP2 0x02 -#define PC87360_SP1 0x03 -#define PC87360_SWC 0x04 -#define PC87360_KBCM 0x05 -#define PC87360_KBCK 0x06 -#define PC87360_GPIO 0x07 -#define PC87360_ACB 0x08 -#define PC87360_FSCM 0x09 -#define PC87360_WDT 0x0A -static void pc87360_enable_serial(void) -{ - pnp_set_logical_device(SIO_BASE, PC87360_SP1); - pnp_set_enable(SIO_BASE, 1); - pnp_set_iobase0(SIO_BASE, 0x3f8); -} static void main(void) { - pc87360_enable_serial(); uart_init(); console_init(); if (boot_cpu() && !cpu_init_detected()) { diff --git a/src/northbridge/amd/amdk8/coherent_ht.c b/src/northbridge/amd/amdk8/coherent_ht.c index 9b799b3d31..81f044cc13 100644 --- a/src/northbridge/amd/amdk8/coherent_ht.c +++ b/src/northbridge/amd/amdk8/coherent_ht.c @@ -574,6 +574,8 @@ static void setup_coherent_ht_domain(void) print_debug("setting up coherent ht domain....\r\n"); max = sizeof(register_values)/sizeof(register_values[0]); for(i = 0; i < max; i += 3) { + device_t dev; + unsigned where; unsigned long reg; #if 0 print_debug_hex32(register_values[i]); @@ -581,10 +583,18 @@ static void setup_coherent_ht_domain(void) print_debug_hex32(register_values[i+2]); print_debug("\r\n"); #endif + dev = register_values[i] & ~0xff; + where = register_values[i] & 0xff; + reg = pci_read_config32(dev, where); + reg &= register_values[i+1]; + reg |= register_values[i+2]; + pci_write_config32(dev, where, reg); +#if 0 reg = pci_read_config32(register_values[i]); reg &= register_values[i+1]; reg |= register_values[i+2] & ~register_values[i+1]; pci_write_config32(register_values[i], reg); +#endif } print_debug("done.\r\n"); } diff --git a/src/northbridge/amd/amdk8/early_ht.c b/src/northbridge/amd/amdk8/early_ht.c index 36e5b9a39f..b8262d519c 100644 --- a/src/northbridge/amd/amdk8/early_ht.c +++ b/src/northbridge/amd/amdk8/early_ht.c @@ -12,38 +12,38 @@ static void enumerate_ht_chain(void) uint8_t hdr_type, pos; last_unitid = next_unitid; - id = pci_read_config32(PCI_ADDR(0,0,0,PCI_VENDOR_ID)); + id = pci_read_config32(PCI_DEV(0,0,0), PCI_VENDOR_ID); /* If the chain is enumerated quit */ if (((id & 0xffff) == 0x0000) || ((id & 0xffff) == 0xffff) || (((id >> 16) & 0xffff) == 0xffff) || (((id >> 16) & 0xffff) == 0x0000)) { break; } - hdr_type = pci_read_config8(PCI_ADDR(0,0,0,PCI_HEADER_TYPE)); + hdr_type = pci_read_config8(PCI_DEV(0,0,0), PCI_HEADER_TYPE); pos = 0; hdr_type &= 0x7f; if ((hdr_type == PCI_HEADER_TYPE_NORMAL) || (hdr_type == PCI_HEADER_TYPE_BRIDGE)) { - pos = pci_read_config8(PCI_ADDR(0,0,0, PCI_CAPABILITY_LIST)); + pos = pci_read_config8(PCI_DEV(0,0,0), PCI_CAPABILITY_LIST); } while(pos != 0) { uint8_t cap; - cap = pci_read_config8(PCI_ADDR(0,0,0, pos + PCI_CAP_LIST_ID)); + cap = pci_read_config8(PCI_DEV(0,0,0), pos + PCI_CAP_LIST_ID); if (cap == PCI_CAP_ID_HT) { uint16_t flags; - flags = pci_read_config16(PCI_ADDR(0,0,0, pos + PCI_CAP_FLAGS)); + flags = pci_read_config16(PCI_DEV(0,0,0), pos + PCI_CAP_FLAGS); if ((flags >> 13) == 0) { unsigned count; flags &= ~0x1f; flags |= next_unitid & 0x1f; count = (flags >> 5) & 0x1f; - pci_write_config16(PCI_ADDR(0, 0, 0, pos + PCI_CAP_FLAGS), flags); + pci_write_config16(PCI_DEV(0, 0, 0), pos + PCI_CAP_FLAGS, flags); next_unitid += count; break; } } - pos = pci_read_config8(PCI_ADDR(0, 0, 0, pos + PCI_CAP_LIST_NEXT)); + pos = pci_read_config8(PCI_DEV(0, 0, 0), pos + PCI_CAP_LIST_NEXT); } } while((last_unitid != next_unitid) && (next_unitid <= 0x1f)); } diff --git a/src/northbridge/amd/amdk8/raminit.c b/src/northbridge/amd/amdk8/raminit.c index 156b80a6a6..1f43e48671 100644 --- a/src/northbridge/amd/amdk8/raminit.c +++ b/src/northbridge/amd/amdk8/raminit.c @@ -692,6 +692,8 @@ static void sdram_set_registers(void) print_debug("setting up CPU0 northbridge registers\r\n"); max = sizeof(register_values)/sizeof(register_values[0]); for(i = 0; i < max; i += 3) { + device_t dev; + unsigned where; unsigned long reg; #if 0 print_debug_hex32(register_values[i]); @@ -699,10 +701,19 @@ static void sdram_set_registers(void) print_debug_hex32(register_values[i+2]); print_debug("\r\n"); #endif + dev = register_values[i] & ~0xff; + where = register_values[i] & 0xff; + reg = pci_read_config32(dev, where); + reg &= register_values[i+1]; + reg |= register_values[i+2]; + pci_write_config32(dev, where, reg); +#if 0 + reg = pci_read_config32(register_values[i]); reg &= register_values[i+1]; reg |= register_values[i+2]; pci_write_config32(register_values[i], reg); +#endif } print_debug("done.\r\n"); } @@ -727,10 +738,10 @@ static void sdram_set_registers(void) static void sdram_set_spd_registers(void) { unsigned long dcl; - dcl = pci_read_config32(PCI_ADDR(0, 0x18, 2, DRAM_CONFIG_LOW)); + dcl = pci_read_config32(PCI_DEV(0, 0x18, 2), DRAM_CONFIG_LOW); /* Until I know what is going on disable ECC support */ dcl &= ~DCL_DimmEcEn; - pci_write_config32(PCI_ADDR(0, 0x18, 2, DRAM_CONFIG_LOW), dcl); + pci_write_config32(PCI_DEV(0, 0x18, 2), DRAM_CONFIG_LOW, dcl); } #define TIMEOUT_LOOPS 300000 @@ -739,23 +750,23 @@ static void sdram_enable(void) unsigned long dcl; /* Toggle DisDqsHys to get it working */ - dcl = pci_read_config32(PCI_ADDR(0, 0x18, 2, DRAM_CONFIG_LOW)); + dcl = pci_read_config32(PCI_DEV(0, 0x18, 2), DRAM_CONFIG_LOW); print_debug("dcl: "); print_debug_hex32(dcl); print_debug("\r\n"); dcl |= DCL_DisDqsHys; - pci_write_config32(PCI_ADDR(0, 0x18, 2, DRAM_CONFIG_LOW), dcl); + pci_write_config32(PCI_DEV(0, 0x18, 2), DRAM_CONFIG_LOW, dcl); dcl &= ~DCL_DisDqsHys; dcl &= ~DCL_DLL_Disable; dcl &= ~DCL_D_DRV; dcl &= ~DCL_QFC_EN; dcl |= DCL_DramInit; - pci_write_config32(PCI_ADDR(0, 0x18, 2, DRAM_CONFIG_LOW), dcl); + pci_write_config32(PCI_DEV(0, 0x18, 2), DRAM_CONFIG_LOW, dcl); print_debug("Initializing memory: "); int loops = 0; do { - dcl = pci_read_config32(PCI_ADDR(0, 0x18, 2, DRAM_CONFIG_LOW)); + dcl = pci_read_config32(PCI_DEV(0, 0x18, 2), DRAM_CONFIG_LOW); loops += 1; if ((loops & 1023) == 0) { print_debug("."); @@ -771,7 +782,7 @@ static void sdram_enable(void) print_debug("Clearing memory: "); loops = 0; do { - dcl = pci_read_config32(PCI_ADDR(0, 0x18, 2, DRAM_CONFIG_LOW)); + dcl = pci_read_config32(PCI_DEV(0, 0x18, 2), DRAM_CONFIG_LOW); loops += 1; if ((loops & 1023) == 0) { print_debug(" "); diff --git a/src/southbridge/amd/amd8111/amd8111_early_smbus.c b/src/southbridge/amd/amd8111/amd8111_early_smbus.c index b0b8e4955f..6b6d9ad144 100644 --- a/src/southbridge/amd/amd8111/amd8111_early_smbus.c +++ b/src/southbridge/amd/amd8111/amd8111_early_smbus.c @@ -11,16 +11,16 @@ static void enable_smbus(void) { - uint32_t addr; - addr = pci_locate_device(PCI_ID(0x1022, 0x746b), 0); - if (addr == ~0U) { + device_t dev; + dev = pci_locate_device(PCI_ID(0x1022, 0x746b), 0); + if (dev == PCI_DEV_INVALID) { die("SMBUS controller not found\r\n"); } uint8_t enable; print_debug("SMBus controller enabled\r\n"); - pci_write_config32(addr + 0x58, SMBUS_IO_BASE | 1); - enable = pci_read_config8(addr + 0x41); - pci_write_config8(addr + 0x41, enable | (1 << 7)); + pci_write_config32(dev, 0x58, SMBUS_IO_BASE | 1); + enable = pci_read_config8(dev, 0x41); + pci_write_config8(dev, 0x41, enable | (1 << 7)); } diff --git a/src/southbridge/amd/amd8111/amd8111_enable_rom.c b/src/southbridge/amd/amd8111/amd8111_enable_rom.c index d6045c3620..4aea04ccf5 100644 --- a/src/southbridge/amd/amd8111/amd8111_enable_rom.c +++ b/src/southbridge/amd/amd8111/amd8111_enable_rom.c @@ -2,17 +2,14 @@ static void amd8111_enable_rom(void) { unsigned char byte; - uint32_t addr; + device_t addr; /* Enable 4MB rom access at 0xFFC00000 - 0xFFFFFFFF */ /* Locate the amd8111 */ addr = pci_locate_device(PCI_ID(0x1022, 0x7468), 0); - /* Refine the address to point at the rom enable byte */ - addr += 0x43; - /* Set the 4MB enable bit bit */ - byte = pci_read_config8(addr); + byte = pci_read_config8(addr, 0x43); byte |= 0x80; - pci_write_config8(addr, byte); + pci_write_config8(addr, 0x43, byte); } |