diff options
| -rw-r--r-- | src/northbridge/intel/sandybridge/early_init.c | 14 | ||||
| -rw-r--r-- | src/northbridge/intel/sandybridge/romstage.c | 14 | ||||
| -rw-r--r-- | src/southbridge/intel/bd82x6x/early_pch.c | 34 | ||||
| -rw-r--r-- | src/southbridge/intel/bd82x6x/pch.h | 1 |
4 files changed, 39 insertions, 24 deletions
diff --git a/src/northbridge/intel/sandybridge/early_init.c b/src/northbridge/intel/sandybridge/early_init.c index ad579c6fc3..b923065091 100644 --- a/src/northbridge/intel/sandybridge/early_init.c +++ b/src/northbridge/intel/sandybridge/early_init.c @@ -27,20 +27,6 @@ static void sandybridge_setup_bars(void) { - /* Setting up Southbridge. In the northbridge code. */ - printk(BIOS_DEBUG, "Setting up static southbridge registers..."); - pci_write_config32(PCH_LPC_DEV, RCBA, (uintptr_t)DEFAULT_RCBA | 1); - - pci_write_config32(PCH_LPC_DEV, PMBASE, DEFAULT_PMBASE | 1); - pci_write_config8(PCH_LPC_DEV, ACPI_CNTL, 0x80); /* Enable ACPI BAR */ - - printk(BIOS_DEBUG, " done.\n"); - - printk(BIOS_DEBUG, "Disabling Watchdog reboot..."); - RCBA32(GCS) = RCBA32(GCS) | (1 << 5); /* No reset */ - outw((1 << 11), DEFAULT_PMBASE | 0x60 | 0x08); /* halt timer */ - printk(BIOS_DEBUG, " done.\n"); - printk(BIOS_DEBUG, "Setting up static northbridge registers..."); /* Set up all hardcoded northbridge BARs */ pci_write_config32(PCI_DEV(0, 0x00, 0), EPBAR, DEFAULT_EPBAR | 1); diff --git a/src/northbridge/intel/sandybridge/romstage.c b/src/northbridge/intel/sandybridge/romstage.c index 6f2a8f1472..3fab3be85d 100644 --- a/src/northbridge/intel/sandybridge/romstage.c +++ b/src/northbridge/intel/sandybridge/romstage.c @@ -28,10 +28,9 @@ #include <device/device.h> #include <northbridge/intel/sandybridge/chip.h> #include <southbridge/intel/bd82x6x/pch.h> -#include <southbridge/intel/common/gpio.h> #include <southbridge/intel/common/pmclib.h> -static void early_pch_init(void) +static void early_pch_reset_pmcon(void) { u8 reg8; @@ -56,13 +55,8 @@ void mainboard_romstage_entry(unsigned long bist) if (bist == 0) enable_lapic(); - pch_enable_lpc(); - - /* Enable GPIOs */ - pci_write_config32(PCH_LPC_DEV, GPIO_BASE, DEFAULT_GPIOBASE|1); - pci_write_config8(PCH_LPC_DEV, GPIO_CNTL, 0x10); - - setup_pch_gpios(&mainboard_gpio_map); + /* Init LPC, GPIO, BARs, disable watchdog ... */ + early_pch_init(); /* Initialize superio */ mainboard_config_superio(); @@ -101,7 +95,7 @@ void mainboard_romstage_entry(unsigned long bist) post_code(0x3b); /* Perform some initialization that must run before stage2 */ - early_pch_init(); + early_pch_reset_pmcon(); post_code(0x3c); southbridge_configure_default_intmap(); diff --git a/src/southbridge/intel/bd82x6x/early_pch.c b/src/southbridge/intel/bd82x6x/early_pch.c index 88436213a0..a50a159668 100644 --- a/src/southbridge/intel/bd82x6x/early_pch.c +++ b/src/southbridge/intel/bd82x6x/early_pch.c @@ -18,6 +18,9 @@ #include <arch/cbfs.h> #include <ip_checksum.h> #include <device/pci_def.h> +#include <southbridge/intel/common/gpio.h> +#include <southbridge/intel/common/pmbase.h> + /* For DMI bar. */ #include <northbridge/intel/sandybridge/sandybridge.h> @@ -367,3 +370,34 @@ early_pch_init_native (void) init_dmi(); } + +static void pch_enable_bars(void) +{ + pci_write_config32(PCH_LPC_DEV, RCBA, (uintptr_t)DEFAULT_RCBA | 1); + + pci_write_config32(PCH_LPC_DEV, PMBASE, DEFAULT_PMBASE | 1); + + pci_write_config8(PCH_LPC_DEV, ACPI_CNTL, 0x80); + + pci_write_config32(PCH_LPC_DEV, GPIO_BASE, DEFAULT_GPIOBASE | 1); + + /* Enable GPIO functionality. */ + pci_write_config8(PCH_LPC_DEV, GPIO_CNTL, 0x10); +} + +static void pch_generic_setup(void) +{ + RCBA32(GCS) = RCBA32(GCS) | (1 << 5); /* No reset */ + write_pmbase16(TCO1_CNT, 1 << 11); /* halt timer */ +} + +void early_pch_init(void) +{ + pch_enable_lpc(); + + pch_enable_bars(); + + pch_generic_setup(); + + setup_pch_gpios(&mainboard_gpio_map); +} diff --git a/src/southbridge/intel/bd82x6x/pch.h b/src/southbridge/intel/bd82x6x/pch.h index 741996531f..21b603108a 100644 --- a/src/southbridge/intel/bd82x6x/pch.h +++ b/src/southbridge/intel/bd82x6x/pch.h @@ -76,6 +76,7 @@ void southbridge_configure_default_intmap(void); void southbridge_rcba_config(void); void mainboard_rcba_config(void); void early_pch_init_native(void); +void early_pch_init(void); struct southbridge_usb_port { |