diff options
| -rw-r--r-- | src/mainboard/google/rush_ryu/Kconfig | 1 | ||||
| -rw-r--r-- | src/soc/nvidia/tegra132/Makefile.inc | 12 | ||||
| -rw-r--r-- | src/soc/nvidia/tegra132/display.c | 32 | ||||
| -rw-r--r-- | src/soc/nvidia/tegra132/soc.c | 2 |
4 files changed, 39 insertions, 8 deletions
diff --git a/src/mainboard/google/rush_ryu/Kconfig b/src/mainboard/google/rush_ryu/Kconfig index da517dab39..ac694a7f7a 100644 --- a/src/mainboard/google/rush_ryu/Kconfig +++ b/src/mainboard/google/rush_ryu/Kconfig @@ -26,6 +26,7 @@ config BOARD_SPECIFIC_OPTIONS # dummy select EC_GOOGLE_CHROMEEC_I2C select EC_GOOGLE_CHROMEEC_I2C_PROTO3 select EC_SOFTWARE_SYNC + select MAINBOARD_DO_NATIVE_VGA_INIT select SPI_FLASH select SOC_NVIDIA_TEGRA132 select MAINBOARD_HAS_BOOTBLOCK_INIT diff --git a/src/soc/nvidia/tegra132/Makefile.inc b/src/soc/nvidia/tegra132/Makefile.inc index a7485fa398..82ac11a7c0 100644 --- a/src/soc/nvidia/tegra132/Makefile.inc +++ b/src/soc/nvidia/tegra132/Makefile.inc @@ -66,12 +66,12 @@ ramstage-y += cbmem.c ramstage-y += cpu.c ramstage-y += cpu_lib.S ramstage-y += clock.c -ramstage-y += display.c -ramstage-y += tegra_dsi.c -ramstage-y += mipi_dsi.c -ramstage-y += mipi.c -ramstage-y += mipi-phy.c -ramstage-y += ./jdi_25x18_display/panel-jdi-lpm102a188a.c +ramstage-$(CONFIG_MAINBOARD_DO_NATIVE_VGA_INIT) += display.c +ramstage-$(CONFIG_MAINBOARD_DO_NATIVE_VGA_INIT) += tegra_dsi.c +ramstage-$(CONFIG_MAINBOARD_DO_NATIVE_VGA_INIT) += mipi_dsi.c +ramstage-$(CONFIG_MAINBOARD_DO_NATIVE_VGA_INIT) += mipi.c +ramstage-$(CONFIG_MAINBOARD_DO_NATIVE_VGA_INIT) += mipi-phy.c +ramstage-$(CONFIG_MAINBOARD_DO_NATIVE_VGA_INIT) += ./jdi_25x18_display/panel-jdi-lpm102a188a.c ramstage-y += soc.c ramstage-y += spi.c diff --git a/src/soc/nvidia/tegra132/display.c b/src/soc/nvidia/tegra132/display.c index 62cea026e5..1708b5a85c 100644 --- a/src/soc/nvidia/tegra132/display.c +++ b/src/soc/nvidia/tegra132/display.c @@ -29,6 +29,7 @@ #include <cpu/cpu.h> #include <boot/tables.h> #include <cbmem.h> +#include <edid.h> #include <soc/clock.h> #include <soc/nvidia/tegra/dc.h> #include <soc/funitcfg.h> @@ -289,9 +290,36 @@ void display_startup(device_t dev) return; } - /* set up window */ + /* Set up window */ update_window(config); - printk(BIOS_INFO, "%s: display init done.\n", __func__); + + /* + * Pass panel information to cb tables + */ + struct edid edid; + /* Align bytes_per_line to 64 bytes as required by dc */ + edid.bytes_per_line = ALIGN_UP((config->xres * + config->framebuffer_bits_per_pixel / 8), 64); + edid.x_resolution = edid.bytes_per_line / + (config->framebuffer_bits_per_pixel / 8); + edid.y_resolution = config->yres; + edid.framebuffer_bits_per_pixel = config->framebuffer_bits_per_pixel; + + printk(BIOS_INFO, "%s: bytes_per_line: %d, bits_per_pixel: %d\n " + " x_res x y_res: %d x %d, size: %d\n", + __func__, edid.bytes_per_line, + edid.framebuffer_bits_per_pixel, + edid.x_resolution, edid.y_resolution, + (edid.bytes_per_line * edid.y_resolution)); + + set_vbe_mode_info_valid(&edid, 0); + + /* + * After this point, it is payload's responsibility to allocate + * framebuffer and sets the base address to dc's + * WINBUF_START_ADDR register and enables window by setting dc's + * DISP_DISP_WIN_OPTIONS register. + */ } diff --git a/src/soc/nvidia/tegra132/soc.c b/src/soc/nvidia/tegra132/soc.c index d80a388f3c..b91260eef3 100644 --- a/src/soc/nvidia/tegra132/soc.c +++ b/src/soc/nvidia/tegra132/soc.c @@ -86,10 +86,12 @@ static void soc_init(device_t dev) spintable_init((void *)cfg->spintable_addr); arch_initialize_cpus(dev, &cntrl_ops); +#if IS_ENABLED(CONFIG_MAINBOARD_DO_NATIVE_VGA_INIT) if (vboot_skip_display_init()) printk(BIOS_INFO, "Skipping display init.\n"); else display_startup(dev); +#endif } static struct device_operations soc_ops = { |