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-rw-r--r--src/mainboard/intel/adlrvp/devicetree.cb10
1 files changed, 5 insertions, 5 deletions
diff --git a/src/mainboard/intel/adlrvp/devicetree.cb b/src/mainboard/intel/adlrvp/devicetree.cb
index daf6ed1fca..12cd47561a 100644
--- a/src/mainboard/intel/adlrvp/devicetree.cb
+++ b/src/mainboard/intel/adlrvp/devicetree.cb
@@ -51,11 +51,11 @@ chip soc/intel/alderlake
register "PcieClkSrcUsage[5]" = "0x5"
register "PcieRpClkReqDetect[5]" = "1"
- # Enable PCH PCIE RP 8 using free running CLK (0x80)
+ # Enable PCH PCIE RP 8 using CLK 6
register "PcieRpEnable[7]" = "1"
- register "PcieClkSrcClkReq[7]" = "7"
- register "PcieClkSrcUsage[7]" = "0x80"
- register "PcieRpClkReqDetect[7]" = "1"
+ register "PcieClkSrcClkReq[7]" = "6" # CLKSRC -> 7 and CLKREQ -> 6
+ register "PcieClkSrcUsage[6]" = "PCIE_CLK_FREE" # CLK 6 is using free running CLK
+ register "PcieRpClkReqDetect[6]" = "1"
# Enable PCH PCIE RP 9 using CLK 1
register "PcieRpEnable[8]" = "1"
@@ -76,7 +76,7 @@ chip soc/intel/alderlake
register "PcieClkSrcUsage[4]" = "0x42"
# Mark LAN CLK pins as unused as GbE 0:0x1f.6 is disabled below
- register "PcieClkSrcUsage[6]" = "0xff"
+ register "PcieClkSrcUsage[7]" = "PCIE_CLK_NOTUSED"
register "SataSalpSupport" = "1"