diff options
| -rw-r--r-- | src/mainboard/google/dedede/Kconfig | 1 | ||||
| -rw-r--r-- | src/mainboard/google/dedede/mainboard.c | 24 | ||||
| -rw-r--r-- | src/mainboard/google/dedede/variants/baseboard/devicetree.cb | 8 |
3 files changed, 25 insertions, 8 deletions
diff --git a/src/mainboard/google/dedede/Kconfig b/src/mainboard/google/dedede/Kconfig index e1b713677d..2892dd16f0 100644 --- a/src/mainboard/google/dedede/Kconfig +++ b/src/mainboard/google/dedede/Kconfig @@ -1,6 +1,7 @@ config BOARD_GOOGLE_BASEBOARD_DEDEDE def_bool n select BOARD_ROMSIZE_KB_16384 if !BOARD_ROMSIZE_KB_32768 + select CR50_USE_LONG_INTERRUPT_PULSES select DPTF_USE_EISA_HID select DRIVERS_I2C_GENERIC select DRIVERS_I2C_HID diff --git a/src/mainboard/google/dedede/mainboard.c b/src/mainboard/google/dedede/mainboard.c index cb84e1f400..45b25809cd 100644 --- a/src/mainboard/google/dedede/mainboard.c +++ b/src/mainboard/google/dedede/mainboard.c @@ -4,9 +4,31 @@ #include <bootstate.h> #include <baseboard/variants.h> #include <device/device.h> +#include <drivers/spi/tpm/tpm.h> #include <ec/ec.h> +#include <security/tpm/tss.h> +#include <soc/soc_chip.h> #include <vendorcode/google/chromeos/chromeos.h> +static void mainboard_update_soc_chip_config(void) +{ + struct soc_intel_jasperlake_config *cfg = config_of_soc(); + int ret; + + ret = tlcl_lib_init(); + if (ret != VB2_SUCCESS) { + printk(BIOS_ERR, "tlcl_lib_init() failed: 0x%x\n", ret); + return; + } + + if (!cr50_is_long_interrupt_pulse_enabled()) { + /* Disable GPIO PM to allow for shorter IRQ pulses */ + printk(BIOS_INFO, "Override GPIO PM\n"); + cfg->gpio_override_pm = 1; + memset(cfg->gpio_pm, 0, sizeof(cfg->gpio_pm)); + } +} + __weak void variant_isst_override(void) { /* @@ -31,6 +53,8 @@ static void mainboard_init(void *chip_info) gpio_configure_pads_with_override(base_pads, base_num, override_pads, override_num); + + mainboard_update_soc_chip_config(); } static void mainboard_dev_init(struct device *dev) diff --git a/src/mainboard/google/dedede/variants/baseboard/devicetree.cb b/src/mainboard/google/dedede/variants/baseboard/devicetree.cb index 73b0c61f1b..fe232e68d3 100644 --- a/src/mainboard/google/dedede/variants/baseboard/devicetree.cb +++ b/src/mainboard/google/dedede/variants/baseboard/devicetree.cb @@ -129,14 +129,6 @@ chip soc/intel/jasperlake # Select eDP for port A register "DdiPortAConfig" = "1" - # Disable PM to allow for shorter irq pulses - register "gpio_override_pm" = "1" - register "gpio_pm[0]" = "0" - register "gpio_pm[1]" = "0" - register "gpio_pm[2]" = "0" - register "gpio_pm[3]" = "0" - register "gpio_pm[4]" = "0" - # Enable HPD for DDI ports B/C register "DdiPortBHpd" = "1" register "DdiPortCHpd" = "1" |