diff options
| -rw-r--r-- | src/soc/amd/stoneyridge/include/soc/iomap.h | 1 | ||||
| -rw-r--r-- | src/soc/amd/stoneyridge/include/soc/southbridge.h | 9 |
2 files changed, 10 insertions, 0 deletions
diff --git a/src/soc/amd/stoneyridge/include/soc/iomap.h b/src/soc/amd/stoneyridge/include/soc/iomap.h index 3e86564e3d..78e8e090a3 100644 --- a/src/soc/amd/stoneyridge/include/soc/iomap.h +++ b/src/soc/amd/stoneyridge/include/soc/iomap.h @@ -37,6 +37,7 @@ #define APU_SMI_BASE 0xfed80200 #define PM_MMIO_BASE 0xfed80300 #define BIOSRAM_MMIO_BASE 0xfed80500 +#define ACPI_REG_MMIO_BASE 0xfed80800 #define GPIO_IOMUX_MMIO_BASE 0xfed80d00 #define MISC_MMIO_BASE 0xfed80e00 #define XHCI_ACPI_PM_MMIO_BASE 0xfed81c00 diff --git a/src/soc/amd/stoneyridge/include/soc/southbridge.h b/src/soc/amd/stoneyridge/include/soc/southbridge.h index 6a66b4c564..32756cd364 100644 --- a/src/soc/amd/stoneyridge/include/soc/southbridge.h +++ b/src/soc/amd/stoneyridge/include/soc/southbridge.h @@ -104,6 +104,15 @@ #define PM_USB_ENABLE 0xef #define PM_USB_ALL_CONTROLLERS 0x7f +/* ACPI MMIO registers 0xfed80800 */ +#define MMIO_ACPI_PM1_STS 0x00 +#define MMIO_ACPI_PM1_EN 0x02 +#define MMIO_ACPI_PM1_CNT_BLK 0x04 +#define MMIO_ACPI_CPU_CONTROL 0x0c +#define MMIO_ACPI_GPE0_STS 0x14 +#define MMIO_ACPI_GPE0_EN 0x18 +#define MMIO_ACPI_PM_TMR_BLK 0x08 + /* FCH MISC Registers 0xfed80e00 */ #define GPP_CLK_CNTRL 0x00 #define GPP_CLK2_REQ_MAP_SHIFT 8 |