diff options
| -rw-r--r-- | src/soc/intel/baytrail/Kconfig | 20 | ||||
| -rw-r--r-- | src/soc/intel/baytrail/Makefile.inc | 10 | ||||
| -rw-r--r-- | src/soc/intel/baytrail/bootblock/bootblock.c | 118 | ||||
| -rw-r--r-- | src/soc/intel/baytrail/include/soc/romstage.h | 2 | ||||
| -rw-r--r-- | src/soc/intel/baytrail/romstage/Makefile.inc | 4 | ||||
| -rw-r--r-- | src/soc/intel/baytrail/romstage/pmc.c | 10 | ||||
| -rw-r--r-- | src/soc/intel/baytrail/romstage/romstage.c | 60 | ||||
| -rw-r--r-- | src/soc/intel/baytrail/romstage/uart.c | 34 |
8 files changed, 98 insertions, 160 deletions
diff --git a/src/soc/intel/baytrail/Kconfig b/src/soc/intel/baytrail/Kconfig index e96b53d321..94ed887d5c 100644 --- a/src/soc/intel/baytrail/Kconfig +++ b/src/soc/intel/baytrail/Kconfig @@ -38,16 +38,11 @@ config CPU_SPECIFIC_OPTIONS select INTEL_GMA_SWSMISCI select CPU_INTEL_COMMON select CPU_HAS_L2_ENABLE_MSR - select ROMCC_BOOTBLOCK config VBOOT select VBOOT_MUST_REQUEST_DISPLAY select VBOOT_STARTS_IN_ROMSTAGE -config BOOTBLOCK_CPU_INIT - string - default "soc/intel/baytrail/bootblock/bootblock.c" - config MMCONF_BASE_ADDRESS hex default 0xe0000000 @@ -97,14 +92,9 @@ config MRC_RMT # +-------------+ DCACHE_RAM_BASE + DCACHE_RAM_SIZE + DCACHE_RAM_MRC_VAR_SIZE # | MRC usage | # | | -# +-------------+ DCACHE_RAM_BASE + DCACHE_RAM_SIZE -# | Stack | -# | | | -# | v | -# +-------------+ -# | ^ | -# | | | -# | CAR Globals | +# -------------+ DCACHE_RAM_BASE + DCACHE_RAM_SIZE +# | coreboot | +# | usage | # +-------------+ DCACHE_RAM_BASE # # Note that the MRC binary is linked to assume the region marked as "MRC usage" @@ -130,6 +120,10 @@ config DCACHE_RAM_MRC_VAR_SIZE help The amount of cache-as-ram region required by the reference code. +config DCACHE_BSP_STACK_SIZE + hex + default 0x2000 + config RESET_ON_INVALID_RAMSTAGE_CACHE bool "Reset the system on S3 wake when ramstage cache invalid." default n diff --git a/src/soc/intel/baytrail/Makefile.inc b/src/soc/intel/baytrail/Makefile.inc index 2c49c63454..1769b53085 100644 --- a/src/soc/intel/baytrail/Makefile.inc +++ b/src/soc/intel/baytrail/Makefile.inc @@ -9,14 +9,19 @@ subdirs-y += ../../../cpu/intel/microcode subdirs-y += ../../../cpu/intel/turbo subdirs-y += ../../../cpu/intel/common +all-y += tsc_freq.c + +bootblock-y += ../../../cpu/intel/car/non-evict/cache_as_ram.S +bootblock-y += ../../../cpu/intel/car/bootblock.c +bootblock-y += ../../../cpu/x86/early_reset.S +bootblock-y += bootblock/bootblock.c + romstage-y += iosf.c romstage-y += memmap.c romstage-y += pmutil.c -romstage-y += tsc_freq.c postcar-y += iosf.c postcar-y += memmap.c -postcar-y += tsc_freq.c ramstage-y += acpi.c ramstage-y += chip.c @@ -41,7 +46,6 @@ ramstage-y += scc.c ramstage-y += sd.c ramstage-y += smm.c ramstage-y += southcluster.c -ramstage-y += tsc_freq.c ramstage-y += xhci.c ramstage-$(CONFIG_ELOG) += elog.c ramstage-$(CONFIG_HAVE_REFCODE_BLOB) += refcode.c diff --git a/src/soc/intel/baytrail/bootblock/bootblock.c b/src/soc/intel/baytrail/bootblock/bootblock.c index b2cdf9d766..1c5bfc54d6 100644 --- a/src/soc/intel/baytrail/bootblock/bootblock.c +++ b/src/soc/intel/baytrail/bootblock/bootblock.c @@ -13,38 +13,14 @@ * GNU General Public License for more details. */ +#include <cpu/intel/car/bootblock.h> #include <device/pci_ops.h> -#include <cpu/x86/cache.h> -#include <cpu/x86/msr.h> -#include <cpu/x86/mtrr.h> #include <soc/iosf.h> -#include <cpu/intel/microcode/microcode.c> - -static void set_var_mtrr(int reg, uint32_t base, uint32_t size, int type) -{ - msr_t basem, maskm; - basem.lo = base | type; - basem.hi = 0; - wrmsr(MTRR_PHYS_BASE(reg), basem); - maskm.lo = ~(size - 1) | MTRR_PHYS_MASK_VALID; - maskm.hi = (1 << (CONFIG_CPU_ADDR_BITS - 32)) - 1; - wrmsr(MTRR_PHYS_MASK(reg), maskm); -} - -static void enable_rom_caching(void) -{ - msr_t msr; - - disable_cache(); - /* Why only top 4MiB ? */ - set_var_mtrr(1, 0xffc00000, 4*1024*1024, MTRR_TYPE_WRPROT); - enable_cache(); - - /* Enable Variable MTRRs */ - msr.hi = 0x00000000; - msr.lo = 0x00000800; - wrmsr(MTRR_DEF_TYPE_MSR, msr); -} +#include <soc/iomap.h> +#include <soc/gpio.h> +#include <soc/lpc.h> +#include <soc/spi.h> +#include <soc/pmc.h> static void setup_mmconfig(void) { @@ -64,12 +40,86 @@ static void setup_mmconfig(void) pci_io_write_config32(IOSF_PCI_DEV, MCR_REG, reg); } -static void bootblock_cpu_init(void) +static void program_base_addresses(void) +{ + uint32_t reg; + const uint32_t lpc_dev = PCI_DEV(0, LPC_DEV, LPC_FUNC); + + /* Memory Mapped IO registers. */ + reg = PMC_BASE_ADDRESS | 2; + pci_write_config32(lpc_dev, PBASE, reg); + reg = IO_BASE_ADDRESS | 2; + pci_write_config32(lpc_dev, IOBASE, reg); + reg = ILB_BASE_ADDRESS | 2; + pci_write_config32(lpc_dev, IBASE, reg); + reg = SPI_BASE_ADDRESS | 2; + pci_write_config32(lpc_dev, SBASE, reg); + reg = MPHY_BASE_ADDRESS | 2; + pci_write_config32(lpc_dev, MPBASE, reg); + reg = PUNIT_BASE_ADDRESS | 2; + pci_write_config32(lpc_dev, PUBASE, reg); + reg = RCBA_BASE_ADDRESS | 1; + pci_write_config32(lpc_dev, RCBA, reg); + + /* IO Port Registers. */ + reg = ACPI_BASE_ADDRESS | 2; + pci_write_config32(lpc_dev, ABASE, reg); + reg = GPIO_BASE_ADDRESS | 2; + pci_write_config32(lpc_dev, GBASE, reg); +} + +static void spi_init(void) +{ + u32 *scs = (u32 *)(SPI_BASE_ADDRESS + SCS); + u32 *bcr = (u32 *)(SPI_BASE_ADDRESS + BCR); + uint32_t reg; + + /* Disable generating SMI when setting WPD bit. */ + write32(scs, read32(scs) & ~SMIWPEN); + /* + * Enable caching and prefetching in the SPI controller. Disable + * the SMM-only BIOS write and set WPD bit. + */ + reg = (read32(bcr) & ~SRC_MASK) | SRC_CACHE_PREFETCH | BCR_WPD; + reg &= ~EISS; + write32(bcr, reg); +} + +static void tco_disable(void) +{ + uint32_t reg; + + reg = inl(ACPI_BASE_ADDRESS + TCO1_CNT); + reg |= TCO_TMR_HALT; + outl(reg, ACPI_BASE_ADDRESS + TCO1_CNT); +} + +static void byt_config_com1_and_enable(void) +{ + uint32_t reg; + + /* Enable the UART hardware for COM1. */ + reg = 1; + pci_write_config32(PCI_DEV(0, LPC_DEV, 0), UART_CONT, reg); + + /* Set up the pads to select the UART function */ + score_select_func(UART_RXD_PAD, 1); + score_select_func(UART_TXD_PAD, 1); +} + +/* The distinction between nb/sb/cpu is not applicable here so + just pick the one that is called first. */ +void bootblock_early_northbridge_init(void) { /* Allow memory-mapped PCI config access. */ setup_mmconfig(); - /* Load microcode before any caching. */ - intel_update_microcode_from_cbfs(); - enable_rom_caching(); + program_base_addresses(); + + tco_disable(); + + if (CONFIG(ENABLE_BUILTIN_COM1)) + byt_config_com1_and_enable(); + + spi_init(); } diff --git a/src/soc/intel/baytrail/include/soc/romstage.h b/src/soc/intel/baytrail/include/soc/romstage.h index e86861c4bf..16f80b4a4f 100644 --- a/src/soc/intel/baytrail/include/soc/romstage.h +++ b/src/soc/intel/baytrail/include/soc/romstage.h @@ -24,8 +24,6 @@ void mainboard_fill_mrc_params(struct mrc_params *mp); void raminit(struct mrc_params *mp, int prev_sleep_state); void gfx_init(void); -void tco_disable(void); void punit_init(void); -void byt_config_com1_and_enable(void); #endif /* _BAYTRAIL_ROMSTAGE_H_ */ diff --git a/src/soc/intel/baytrail/romstage/Makefile.inc b/src/soc/intel/baytrail/romstage/Makefile.inc index 2effbb08f6..58d7889917 100644 --- a/src/soc/intel/baytrail/romstage/Makefile.inc +++ b/src/soc/intel/baytrail/romstage/Makefile.inc @@ -1,9 +1,5 @@ -cpu_incs-y += $(src)/cpu/intel/car/non-evict/cache_as_ram.S -cpu_incs-y += $(obj)/fmap_config.h - romstage-y += ../../../../cpu/intel/car/romstage.c romstage-y += romstage.c romstage-y += raminit.c -romstage-$(CONFIG_ENABLE_BUILTIN_COM1) += uart.c romstage-y += gfx.c romstage-y += pmc.c diff --git a/src/soc/intel/baytrail/romstage/pmc.c b/src/soc/intel/baytrail/romstage/pmc.c index 2eb3846c4f..11b3b0f8bc 100644 --- a/src/soc/intel/baytrail/romstage/pmc.c +++ b/src/soc/intel/baytrail/romstage/pmc.c @@ -14,7 +14,6 @@ */ #include <stddef.h> -#include <arch/io.h> #include <device/pci_ops.h> #include <console/console.h> #include <device/device.h> @@ -27,15 +26,6 @@ #include <soc/romstage.h> #include "../chip.h" -void tco_disable(void) -{ - uint32_t reg; - - reg = inl(ACPI_BASE_ADDRESS + TCO1_CNT); - reg |= TCO_TMR_HALT; - outl(reg, ACPI_BASE_ADDRESS + TCO1_CNT); -} - /* This sequence signals the PUNIT to start running. */ void punit_init(void) { diff --git a/src/soc/intel/baytrail/romstage/romstage.c b/src/soc/intel/baytrail/romstage/romstage.c index 7c129e258e..25cb6617f6 100644 --- a/src/soc/intel/baytrail/romstage/romstage.c +++ b/src/soc/intel/baytrail/romstage/romstage.c @@ -27,60 +27,11 @@ #include <romstage_handoff.h> #include <string.h> #include <timestamp.h> -#include <vendorcode/google/chromeos/chromeos.h> -#include <soc/gpio.h> #include <soc/iomap.h> -#include <soc/lpc.h> #include <soc/msr.h> #include <soc/pci_devs.h> #include <soc/pmc.h> #include <soc/romstage.h> -#include <soc/spi.h> - -static void program_base_addresses(void) -{ - uint32_t reg; - const uint32_t lpc_dev = PCI_DEV(0, LPC_DEV, LPC_FUNC); - - /* Memory Mapped IO registers. */ - reg = PMC_BASE_ADDRESS | 2; - pci_write_config32(lpc_dev, PBASE, reg); - reg = IO_BASE_ADDRESS | 2; - pci_write_config32(lpc_dev, IOBASE, reg); - reg = ILB_BASE_ADDRESS | 2; - pci_write_config32(lpc_dev, IBASE, reg); - reg = SPI_BASE_ADDRESS | 2; - pci_write_config32(lpc_dev, SBASE, reg); - reg = MPHY_BASE_ADDRESS | 2; - pci_write_config32(lpc_dev, MPBASE, reg); - reg = PUNIT_BASE_ADDRESS | 2; - pci_write_config32(lpc_dev, PUBASE, reg); - reg = RCBA_BASE_ADDRESS | 1; - pci_write_config32(lpc_dev, RCBA, reg); - - /* IO Port Registers. */ - reg = ACPI_BASE_ADDRESS | 2; - pci_write_config32(lpc_dev, ABASE, reg); - reg = GPIO_BASE_ADDRESS | 2; - pci_write_config32(lpc_dev, GBASE, reg); -} - -static void spi_init(void) -{ - u32 *scs = (u32 *)(SPI_BASE_ADDRESS + SCS); - u32 *bcr = (u32 *)(SPI_BASE_ADDRESS + BCR); - uint32_t reg; - - /* Disable generating SMI when setting WPD bit. */ - write32(scs, read32(scs) & ~SMIWPEN); - /* - * Enable caching and prefetching in the SPI controller. Disable - * the SMM-only BIOS write and set WPD bit. - */ - reg = (read32(bcr) & ~SRC_MASK) | SRC_CACHE_PREFETCH | BCR_WPD; - reg &= ~EISS; - write32(bcr, reg); -} static struct chipset_power_state power_state; @@ -158,17 +109,6 @@ void mainboard_romstage_entry(void) int prev_sleep_state; struct mrc_params mp; - program_base_addresses(); - - tco_disable(); - - if (CONFIG(ENABLE_BUILTIN_COM1)) - byt_config_com1_and_enable(); - - console_init(); - - spi_init(); - set_max_freq(); punit_init(); diff --git a/src/soc/intel/baytrail/romstage/uart.c b/src/soc/intel/baytrail/romstage/uart.c deleted file mode 100644 index f9f2fe4238..0000000000 --- a/src/soc/intel/baytrail/romstage/uart.c +++ /dev/null @@ -1,34 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2013 Google Inc. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#include <device/pci_ops.h> -#include <soc/gpio.h> -#include <soc/iomap.h> -#include <soc/lpc.h> -#include <soc/pci_devs.h> -#include <soc/romstage.h> - -void byt_config_com1_and_enable(void) -{ - uint32_t reg; - - /* Enable the UART hardware for COM1. */ - reg = 1; - pci_write_config32(PCI_DEV(0, LPC_DEV, 0), UART_CONT, reg); - - /* Set up the pads to select the UART function */ - score_select_func(UART_RXD_PAD, 1); - score_select_func(UART_TXD_PAD, 1); -} |