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-rw-r--r--src/mainboard/google/hatch/variants/baseboard/devicetree.cb12
1 files changed, 6 insertions, 6 deletions
diff --git a/src/mainboard/google/hatch/variants/baseboard/devicetree.cb b/src/mainboard/google/hatch/variants/baseboard/devicetree.cb
index 9a9125396c..a4700321a4 100644
--- a/src/mainboard/google/hatch/variants/baseboard/devicetree.cb
+++ b/src/mainboard/google/hatch/variants/baseboard/devicetree.cb
@@ -95,12 +95,12 @@ chip soc/intel/cannonlake
register "gpio_override_pm" = "1"
# GPIO community PM configuration
- register "gpio_pm[COMM_0]" = "MISCCFG_ENABLE_GPIO_PM_CONFIG"
- register "gpio_pm[COMM_1]" = "MISCCFG_ENABLE_GPIO_PM_CONFIG"
- register "gpio_pm[COMM_2]" = "MISCCFG_ENABLE_GPIO_PM_CONFIG"
- register "gpio_pm[COMM_3]" = "MISCCFG_ENABLE_GPIO_PM_CONFIG"
- # Disable clock gating on this community so that cr50's short irq
- # pulses won't be missed.
+ # Disable dynamic clock gating; with bits 0-5 set in these registers,
+ # some short interrupt pulses were missed (esp. cr50 irq)
+ register "gpio_pm[COMM_0]" = "0"
+ register "gpio_pm[COMM_1]" = "0"
+ register "gpio_pm[COMM_2]" = "0"
+ register "gpio_pm[COMM_3]" = "0"
register "gpio_pm[COMM_4]" = "0"
device cpu_cluster 0 on