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-rw-r--r--src/soc/nvidia/tegra132/chip.h35
1 files changed, 34 insertions, 1 deletions
diff --git a/src/soc/nvidia/tegra132/chip.h b/src/soc/nvidia/tegra132/chip.h
index f2936dde6c..23f2cd8f38 100644
--- a/src/soc/nvidia/tegra132/chip.h
+++ b/src/soc/nvidia/tegra132/chip.h
@@ -1,7 +1,7 @@
/*
* This file is part of the coreboot project.
*
- * Copyright 2013 Google Inc.
+ * Copyright 2014 Google Inc.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
@@ -29,6 +29,39 @@
struct soc_nvidia_tegra132_config {
/* Address to monitor if spintable employed. */
uintptr_t spintable_addr;
+
+ /*
+ * panel default specification
+ */
+ u32 xres; /* the width of H display active area */
+ u32 yres; /* the height of V display active area */
+ u32 framebuffer_bits_per_pixel;
+ u32 color_depth; /* color format */
+
+ u64 display_controller; /* dc block base address */
+ u32 framebuffer_base;
+
+ /*
+ * Technically, we can compute this. At the same time, some platforms
+ * might want to specify a specific size for their own reasons. If it
+ * is zero the soc code will compute it as
+ * xres*yres*framebuffer_bits_per_pixel/8
+ */
+ u32 framebuffer_size;
+
+ int href_to_sync; /* HSYNC position with respect to line start */
+ int hsync_width; /* the width of HSYNC pulses */
+ int hback_porch; /* the distance between HSYNC trailing edge to
+ beginning of H display active area */
+ int hfront_porch; /* the distance between end of H display active
+ area to the leading edge of HSYNC */
+ int vref_to_sync;
+ int vsync_width;
+ int vback_porch;
+ int vfront_porch;
+ int refresh; /* display refresh rate */
+
+ int pixel_clock; /* dc pixel clock source rate */
};
#endif /* __SOC_NVIDIA_TEGRA132_CHIP_H__ */