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-rw-r--r--src/cpu/amd/model_10xxx/init_cpus.c6
-rw-r--r--src/cpu/amd/model_fxx/init_cpus.c2
-rw-r--r--src/cpu/x86/mtrr/earlymtrr.c2
-rw-r--r--src/cpu/x86/mtrr/mtrr.c2
-rw-r--r--src/northbridge/amd/amdfam10/northbridge.c2
-rw-r--r--src/northbridge/amd/amdk8/coherent_ht.c10
-rw-r--r--src/northbridge/amd/amdmct/wrappers/mcti_d.c10
-rw-r--r--src/southbridge/amd/rs780/gfx.c4
-rw-r--r--src/southbridge/amd/sr5650/early_setup.c6
9 files changed, 22 insertions, 22 deletions
diff --git a/src/cpu/amd/model_10xxx/init_cpus.c b/src/cpu/amd/model_10xxx/init_cpus.c
index edc016a758..e2a4a64d0b 100644
--- a/src/cpu/amd/model_10xxx/init_cpus.c
+++ b/src/cpu/amd/model_10xxx/init_cpus.c
@@ -111,7 +111,7 @@ static void for_each_ap(u32 bsp_apicid, u32 core_range, process_ap_t process_ap,
i * (nb_cfg_54 ? (siblings + 1) : 1) +
j * (nb_cfg_54 ? 1 : 64);
-#if (CONFIG_ENABLE_APIC_EXT_ID == 1) && (CONFIG_APIC_ID_OFFSET > 0)
+#if CONFIG_ENABLE_APIC_EXT_ID && (CONFIG_APIC_ID_OFFSET > 0)
#if !CONFIG_LIFT_BSP_APIC_ID
if ((i != 0) || (j != 0)) /* except bsp */
#endif
@@ -274,7 +274,7 @@ static u32 init_cpus(u32 cpu_init_detectedx)
enable_lapic();
-#if (CONFIG_ENABLE_APIC_EXT_ID == 1) && (CONFIG_APIC_ID_OFFSET > 0)
+#if CONFIG_ENABLE_APIC_EXT_ID && (CONFIG_APIC_ID_OFFSET > 0)
u32 initial_apicid = get_initial_apicid();
#if !CONFIG_LIFT_BSP_APIC_ID
@@ -331,7 +331,7 @@ static u32 init_cpus(u32 cpu_init_detectedx)
cpuSetAMDMSR();
#if CONFIG_SET_FIDVID
-#if (CONFIG_LOGICAL_CPUS == 1) && CONFIG_SET_FIDVID_CORE0_ONLY
+#if CONFIG_LOGICAL_CPUS && CONFIG_SET_FIDVID_CORE0_ONLY
// Run on all AP for proper FID/VID setup.
if (id.coreid == 0) // only need set fid for core0
#endif
diff --git a/src/cpu/amd/model_fxx/init_cpus.c b/src/cpu/amd/model_fxx/init_cpus.c
index 2ae9aaced7..7121642605 100644
--- a/src/cpu/amd/model_fxx/init_cpus.c
+++ b/src/cpu/amd/model_fxx/init_cpus.c
@@ -276,7 +276,7 @@ static u32 init_cpus(u32 cpu_init_detectedx)
u32 loop = 100;
#if CONFIG_SET_FIDVID
-#if (CONFIG_LOGICAL_CPUS == 1) && CONFIG_SET_FIDVID_CORE0_ONLY
+#if CONFIG_LOGICAL_CPUS && CONFIG_SET_FIDVID_CORE0_ONLY
if (id.coreid == 0) // only need set fid for core0
#endif
init_fidvid_ap(bsp_apicid, apicid);
diff --git a/src/cpu/x86/mtrr/earlymtrr.c b/src/cpu/x86/mtrr/earlymtrr.c
index f8119d3e59..7a1f51de15 100644
--- a/src/cpu/x86/mtrr/earlymtrr.c
+++ b/src/cpu/x86/mtrr/earlymtrr.c
@@ -20,7 +20,7 @@ static void set_var_mtrr(
wrmsr(MTRRphysMask_MSR(reg), maskm);
}
-#if !defined(CONFIG_CACHE_AS_RAM) || (CONFIG_CACHE_AS_RAM == 0)
+#if !defined(CONFIG_CACHE_AS_RAM) || !CONFIG_CACHE_AS_RAM
static void cache_lbmem(int type)
{
/* Enable caching for 0 - 1MB using variable mtrr */
diff --git a/src/cpu/x86/mtrr/mtrr.c b/src/cpu/x86/mtrr/mtrr.c
index c31090547d..cce526a94d 100644
--- a/src/cpu/x86/mtrr/mtrr.c
+++ b/src/cpu/x86/mtrr/mtrr.c
@@ -464,7 +464,7 @@ void x86_setup_var_mtrrs(unsigned int address_bits, unsigned int above4gb)
IORESOURCE_MEM | IORESOURCE_CACHEABLE, IORESOURCE_MEM | IORESOURCE_CACHEABLE,
set_var_mtrr_resource, &var_state);
-#if (CONFIG_GFXUMA == 1) /* UMA or SP. */
+#if CONFIG_GFXUMA /* UMA or SP. */
/* For now we assume the UMA space is at the end of memory below 4GB */
if (var_state.hole_startk || var_state.hole_sizek) {
printk(BIOS_DEBUG, "Warning: Can't set up MTRR hole for UMA due to pre-existing MTRR hole.\n");
diff --git a/src/northbridge/amd/amdfam10/northbridge.c b/src/northbridge/amd/amdfam10/northbridge.c
index 0e80c71324..3b20684e75 100644
--- a/src/northbridge/amd/amdfam10/northbridge.c
+++ b/src/northbridge/amd/amdfam10/northbridge.c
@@ -1425,7 +1425,7 @@ static u32 cpu_bus_scan(device_t dev, u32 max)
if (cpu) {
cpu->path.apic.node_id = i;
cpu->path.apic.core_id = j;
- #if (CONFIG_ENABLE_APIC_EXT_ID == 1) && (CONFIG_APIC_ID_OFFSET>0)
+ #if CONFIG_ENABLE_APIC_EXT_ID && (CONFIG_APIC_ID_OFFSET>0)
if(sysconf.enabled_apic_ext_id) {
if(sysconf.lift_bsp_apicid) {
cpu->path.apic.apic_id += sysconf.apicid_offset;
diff --git a/src/northbridge/amd/amdk8/coherent_ht.c b/src/northbridge/amd/amdk8/coherent_ht.c
index 636114df15..9ad342367c 100644
--- a/src/northbridge/amd/amdk8/coherent_ht.c
+++ b/src/northbridge/amd/amdk8/coherent_ht.c
@@ -394,7 +394,7 @@ static uint8_t get_linkn_last(uint8_t byte)
}
#endif
-#if (CONFIG_MAX_PHYSICAL_CPUS > 2) || (CONFIG_MAX_PHYSICAL_CPUS_4_BUT_MORE_INSTALLED == 1)
+#if (CONFIG_MAX_PHYSICAL_CPUS > 2) || CONFIG_MAX_PHYSICAL_CPUS_4_BUT_MORE_INSTALLED
static uint8_t get_linkn_last_count(uint8_t byte)
{
byte &= 0x0f;
@@ -563,7 +563,7 @@ static void setup_row_indirect_x(u8 temp, u8 source, u8 dest, u8 gateway, u8 dif
if(diff && (val_s!=(val&0xff)) ) { /* use another connect as response*/
val_s -= val & 0xff;
-#if (CONFIG_MAX_PHYSICAL_CPUS > 4) || (CONFIG_MAX_PHYSICAL_CPUS_4_BUT_MORE_INSTALLED == 1)
+#if (CONFIG_MAX_PHYSICAL_CPUS > 4) || CONFIG_MAX_PHYSICAL_CPUS_4_BUT_MORE_INSTALLED
uint8_t byte;
/* Some node have two links left
* don't worry we only have (2, (3 as source need to handle
@@ -722,7 +722,7 @@ static unsigned setup_smp2(void)
setup_row_local(7,1);
setup_remote_row_direct(1, 0, byte);
-#if (CONFIG_MAX_PHYSICAL_CPUS > 4) || (CONFIG_MAX_PHYSICAL_CPUS_4_BUT_MORE_INSTALLED == 1)
+#if (CONFIG_MAX_PHYSICAL_CPUS > 4) || CONFIG_MAX_PHYSICAL_CPUS_4_BUT_MORE_INSTALLED
val = get_row(7,1);
byte = (val>>16) & 0xfe;
byte = get_linkn_last_count(byte);
@@ -848,7 +848,7 @@ static unsigned setup_smp4(void)
setup_temp_row(2,3);
verify_connection(7); /* to 3*/
-#if (CONFIG_MAX_PHYSICAL_CPUS > 4) || (CONFIG_MAX_PHYSICAL_CPUS_4_BUT_MORE_INSTALLED == 1)
+#if (CONFIG_MAX_PHYSICAL_CPUS > 4) || CONFIG_MAX_PHYSICAL_CPUS_4_BUT_MORE_INSTALLED
/* We need to find out which link is to node3 */
if((byte>>2)==2) { /* one to node3, one to node0, one to node4*/
val = get_row(7,3);
@@ -869,7 +869,7 @@ static unsigned setup_smp4(void)
print_linkn("(3,2) link=", byte);
setup_remote_row_direct(3,2, byte);
-#if (CONFIG_MAX_PHYSICAL_CPUS > 4) || (CONFIG_MAX_PHYSICAL_CPUS_4_BUT_MORE_INSTALLED == 1)
+#if (CONFIG_MAX_PHYSICAL_CPUS > 4) || CONFIG_MAX_PHYSICAL_CPUS_4_BUT_MORE_INSTALLED
/* set link from 3 to 5 before enable it*/
val = get_row(7,3);
byte = ((val>>16) & 0xfe) - link_connection(7,2) - link_connection(7,1);
diff --git a/src/northbridge/amd/amdmct/wrappers/mcti_d.c b/src/northbridge/amd/amdmct/wrappers/mcti_d.c
index 00b15556ca..2440d2e8ed 100644
--- a/src/northbridge/amd/amdmct/wrappers/mcti_d.c
+++ b/src/northbridge/amd/amdmct/wrappers/mcti_d.c
@@ -66,14 +66,14 @@ static u16 mctGet_NVbits(u8 index)
case NV_BYPMAX:
#if !CONFIG_GFXUMA
val = 4;
-#elif (CONFIG_GFXUMA == 1)
+#elif CONFIG_GFXUMA
val = 7;
#endif
break;
case NV_RDWRQBYP:
#if !CONFIG_GFXUMA
val = 2;
-#elif (CONFIG_GFXUMA == 1)
+#elif CONFIG_GFXUMA
val = 3;
#endif
break;
@@ -115,7 +115,7 @@ static u16 mctGet_NVbits(u8 index)
case NV_BurstLen32:
#if !CONFIG_GFXUMA
val = 0; /* 64 byte mode */
-#elif (CONFIG_GFXUMA == 1)
+#elif CONFIG_GFXUMA
val = 1; /* 32 byte mode */
#endif
break;
@@ -134,14 +134,14 @@ static u16 mctGet_NVbits(u8 index)
case NV_BottomIO:
#if !CONFIG_GFXUMA
val = 0xE0; /* address bits [31:24] */
-#elif (CONFIG_GFXUMA == 1)
+#elif CONFIG_GFXUMA
val = 0xC0; /* address bits [31:24] */
#endif
break;
case NV_BottomUMA:
#if !CONFIG_GFXUMA
val = 0xE0; /* address bits [31:24] */
-#elif (CONFIG_GFXUMA == 1)
+#elif CONFIG_GFXUMA
val = 0xC0; /* address bits [31:24] */
#endif
break;
diff --git a/src/southbridge/amd/rs780/gfx.c b/src/southbridge/amd/rs780/gfx.c
index e8d4596adf..e07aa101d5 100644
--- a/src/southbridge/amd/rs780/gfx.c
+++ b/src/southbridge/amd/rs780/gfx.c
@@ -411,7 +411,7 @@ static void internal_gfx_pci_dev_init(struct device *dev)
/* GFX_InitFBAccess finished. */
-#if (CONFIG_GFXUMA == 1) /* for UMA mode. */
+#if CONFIG_GFXUMA /* for UMA mode. */
/* GFX_StartMC. */
set_nbmc_enable_bits(nb_dev, 0x02, 0x00000000, 0x80000000);
set_nbmc_enable_bits(nb_dev, 0x01, 0x00000000, 0x00000001);
@@ -473,7 +473,7 @@ static void internal_gfx_pci_dev_init(struct device *dev)
vgainfo.sHeader.ucTableFormatRevision = 1;
vgainfo.sHeader.ucTableContentRevision = 2;
-#if (CONFIG_GFXUMA == 0) /* SP mode. */
+#if !CONFIG_GFXUMA /* SP mode. */
// Side port support is incomplete, do not use it
// These parameters must match the motherboard
vgainfo.ulBootUpSidePortClock = 667*100;
diff --git a/src/southbridge/amd/sr5650/early_setup.c b/src/southbridge/amd/sr5650/early_setup.c
index 32bdd7f28a..0f54ba356c 100644
--- a/src/southbridge/amd/sr5650/early_setup.c
+++ b/src/southbridge/amd/sr5650/early_setup.c
@@ -51,7 +51,7 @@ static void alink_ax_indx(u32 space, u32 axindc, u32 mask, u32 val)
/* family 10 only, for reg > 0xFF */
-#if (CONFIG_NORTHBRIDGE_AMD_AMDFAM10 == 1) || (CONFIG_NORTHBRIDGE_AMD_AGESA_FAMILY10 == 1)
+#if CONFIG_NORTHBRIDGE_AMD_AMDFAM10 || CONFIG_NORTHBRIDGE_AMD_AGESA_FAMILY10
static void set_fam10_ext_cfg_enable_bits(device_t fam10_dev, u32 reg_pos, u32 mask,
u32 val)
{
@@ -220,7 +220,7 @@ void sr5650_htinit(void)
/* Enable Protocol checker */
set_htiu_enable_bits(sr5650_f0, 0x1E, 0xFFFFFFFF, 0x7FFFFFFC);
-#if (CONFIG_NORTHBRIDGE_AMD_AMDFAM10 == 1) || (CONFIG_NORTHBRIDGE_AMD_AGESA_FAMILY10 == 1) /* save some spaces */
+#if CONFIG_NORTHBRIDGE_AMD_AMDFAM10 || CONFIG_NORTHBRIDGE_AMD_AGESA_FAMILY10 /* save some spaces */
/* HT3 mode, RPR 5.4.3 */
set_nbcfg_enable_bits(sr5650_f0, 0x9c, 0x3 << 16, 0);
@@ -270,7 +270,7 @@ void sr5650_htinit(void)
}
}
-#if (CONFIG_NORTHBRIDGE_AMD_AMDFAM10 == 1) || (CONFIG_NORTHBRIDGE_AMD_AGESA_FAMILY10 == 1) /* save some spaces */
+#if CONFIG_NORTHBRIDGE_AMD_AMDFAM10 || CONFIG_NORTHBRIDGE_AMD_AGESA_FAMILY10 /* save some spaces */
void fam10_optimization(void)
{
device_t cpu_f0, cpu_f2, cpu_f3;
generated by cgit v1.2.3 (git 2.25.1) at 2024-11-28 00:04:27 +0000