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-rw-r--r--src/soc/intel/common/block/include/intelblocks/lpss.h3
-rw-r--r--src/soc/intel/common/block/lpss/lpss.c13
2 files changed, 14 insertions, 2 deletions
diff --git a/src/soc/intel/common/block/include/intelblocks/lpss.h b/src/soc/intel/common/block/include/intelblocks/lpss.h
index 138340df86..c6caae2675 100644
--- a/src/soc/intel/common/block/include/intelblocks/lpss.h
+++ b/src/soc/intel/common/block/include/intelblocks/lpss.h
@@ -30,4 +30,7 @@ void lpss_clk_update(uintptr_t base, uint32_t clk_m_val, uint32_t clk_n_val);
/* Check if controller is in reset. */
bool lpss_is_controller_in_reset(uintptr_t base);
+/* Read LPSS CLK register */
+uint32_t lpss_clk_read(uintptr_t base);
+
#endif /* SOC_INTEL_COMMON_BLOCK_LPSS_H */
diff --git a/src/soc/intel/common/block/lpss/lpss.c b/src/soc/intel/common/block/lpss/lpss.c
index feacef370f..6d4fb336f3 100644
--- a/src/soc/intel/common/block/lpss/lpss.c
+++ b/src/soc/intel/common/block/lpss/lpss.c
@@ -65,7 +65,16 @@ void lpss_clk_update(uintptr_t base, uint32_t clk_m_val, uint32_t clk_n_val)
addr += LPSS_CLOCK_CTL_REG;
clk_sel = LPSS_CLOCK_DIV_N(clk_n_val) | LPSS_CLOCK_DIV_M(clk_m_val);
+ clk_sel |= LPSS_CNT_CLK_UPDATE | LPSS_CNT_CLOCK_EN;
- write32(addr, clk_sel | LPSS_CNT_CLK_UPDATE);
- write32(addr, clk_sel | LPSS_CNT_CLOCK_EN);
+ write32(addr, clk_sel);
+}
+
+uint32_t lpss_clk_read(uintptr_t base)
+{
+ uint8_t *addr = (void *)base;
+
+ addr += LPSS_CLOCK_CTL_REG;
+
+ return read32(addr);
}