diff options
| -rw-r--r-- | src/soc/amd/picasso/aoac.c | 2 | ||||
| -rw-r--r-- | src/soc/amd/picasso/include/soc/southbridge.h | 4 |
2 files changed, 6 insertions, 0 deletions
diff --git a/src/soc/amd/picasso/aoac.c b/src/soc/amd/picasso/aoac.c index 35adc24723..2e00d98900 100644 --- a/src/soc/amd/picasso/aoac.c +++ b/src/soc/amd/picasso/aoac.c @@ -36,6 +36,8 @@ void power_on_aoac_device(int dev) /* Power on the UART and AMBA devices */ byte = aoac_read8(AOAC_DEV_D3_CTL(dev)); byte |= FCH_AOAC_PWR_ON_DEV; + byte &= ~FCH_AOAC_TARGET_DEVICE_STATE; + byte |= FCH_AOAC_D0_INITIALIZED; aoac_write8(AOAC_DEV_D3_CTL(dev), byte); } diff --git a/src/soc/amd/picasso/include/soc/southbridge.h b/src/soc/amd/picasso/include/soc/southbridge.h index 463ca296aa..7265d30a77 100644 --- a/src/soc/amd/picasso/include/soc/southbridge.h +++ b/src/soc/amd/picasso/include/soc/southbridge.h @@ -207,6 +207,10 @@ /* Bit definitions for Device D3 Control AOACx0000[40...7E] step 2 */ #define FCH_AOAC_TARGET_DEVICE_STATE (BIT(0) + BIT(1)) +#define FCH_AOAC_D0_UNINITIALIZED 0 +#define FCH_AOAC_D0_INITIALIZED 1 +#define FCH_AOAC_D1_2_3_WARM 2 +#define FCH_AOAC_D3_COLD 3 #define FCH_AOAC_DEVICE_STATE BIT(2) #define FCH_AOAC_PWR_ON_DEV BIT(3) #define FCH_AOAC_SW_PWR_ON_RSTB BIT(4) |